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AgeCommit message (Expand)Author
2023-12-12Fix whitespace snafu in tc-riscv.cNick Clifton
2023-12-12RISC-V: Emit R_RISCV_RELAX for the la/lga pseudo instructionRui Ueyama
2023-12-12RISC-V: Resolve PCREL_HI20/LO12_I/S fixups with local symbols while `-mno-relax'Lifang Xia
2023-12-11LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">mengqinggang
2023-12-11RISC-V/gas: Clarify the definition of `relaxable' in md_apply_fixNelson Chu
2023-12-01gas: drop unused fields from struct segment_info_structJan Beulich
2023-12-01x86: adjust NOP generation after potential non-insnJan Beulich
2023-12-01x86: i386_cons_align() badly affects diagnosticsJan Beulich
2023-12-01gas: no md_cons_align() for .nop{,s}Jan Beulich
2023-12-01x86: suppress optimization after potential non-insnJan Beulich
2023-12-01x86: last-insn recording should be per-sectionJan Beulich
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich
2023-12-01RISC-V: Update gas/NEWS for RISC-V vendor extension news.Nelson Chu
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner
2023-11-30MIPS/GAS: Add -march=loongson2f to loongson-2f-3 testYunQiang Su
2023-11-30MIPS: Set r6 as default arch if vendor is imgYunQiang Su
2023-11-30gas: support double-slash line comments in BPF assemblyJose E. Marchesi
2023-11-28gas: add NEWS entry for change of comment syntax in BPF assemblerJose E. Marchesi
2023-11-28gas: change meaning of ; in the BPF assemblerJose E. Marchesi
2023-11-28testsuite: Clean up .allow_index_reg in i386 testsHaochen Jiang
2023-11-28testsuite: Clean up #as in dump file for i386 testsHaochen Jiang
2023-11-27as: Add new estimated reciprocal instructions in LoongArch v1.1Jiajie Chen
2023-11-27as: Add new atomic instructions in LoongArch v1.1Jiajie Chen
2023-11-24x86: shrink opcode sets tableJan Beulich
2023-11-24x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possibleJan Beulich
2023-11-24RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich
2023-11-24RISC-V: disallow x0 with certain macro-insnsJan Beulich
2023-11-23s390: Add missing extended mnemonicsJens Remus
2023-11-23s390: Align optional operand definition to specsJens Remus
2023-11-23s390: Add brasl edge test cases from ESA to z/ArchitectureJens Remus
2023-11-23s390: Position independent verification of relative addressingJens Remus
2023-11-23MIPS/GAS: Use addiu instead of addi in test elf-rel.YunQiang Su
2023-11-23MIPS/GAS: Fix test failures due to jr encoding changes on r6YunQiang Su
2023-11-23RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extensionJin Ma
2023-11-23RISC-V: Add vector mask instructions for T-Head VECTOR vendor extensionJin Ma
2023-11-23RISC-V: Add reductions instructions for T-Head VECTOR vendor extensionJin Ma
2023-11-23RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...Jin Ma
2023-11-23RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...Jin Ma
2023-11-23RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extensionJin Ma
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma
2023-11-23RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extensionJin Ma
2023-11-23RISC-V: Add load/store instructions for T-Head VECTOR vendor extensionJin Ma
2023-11-23RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...Jin Ma
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma
2023-11-23RISC-V: Add T-Head VECTOR vendor extension.Jin Ma
2023-11-22LoongArch: fix internal error when as handling unsupported modifier.Lulu Cai
2023-11-21bpf: Fixed register parsing disambiguating with possible symbol.Cupertino Miranda
2023-11-18gas: bpf: do not allow referring to register names as symbols in operandsJose E. Marchesi
2023-11-17bpf: avoid creating wrong symbols while parsingDavid Faust