diff options
author | Andrea Corallo <andrea.corallo@arm.com> | 2023-10-10 16:37:11 +0100 |
---|---|---|
committer | Andrea Corallo <andrea.corallo@arm.com> | 2023-12-19 15:35:49 +0100 |
commit | d645278cdf413ecdfac873528133ae40d927da0c (patch) | |
tree | 511f815339f3bb86f5dc4bb647a3d69cb60e847a /opcodes | |
parent | db168da2e0d7ea01d0a8ed4bdd0e035e47094fed (diff) |
aarch64: Add FEAT_ITE support
This patch add support for FEAT_ITE "Instrumentation Extension" adding
the "trcit" instruction.
This is enabled by the +ite march flag.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/aarch64-asm-2.c | 1 | ||||
-rw-r--r-- | opcodes/aarch64-dis-2.c | 3 | ||||
-rw-r--r-- | opcodes/aarch64-tbl.h | 10 |
3 files changed, 12 insertions, 2 deletions
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index e9b9ce27f8d..b7f27f2305f 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -465,6 +465,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode) case 1236: /* dsb */ value = 1236; /* --> dsb. */ break; + case 3194: /* trcit */ case 1264: /* cosp */ case 1263: /* cpp */ case 1262: /* dvp */ diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 977b1c1303e..9fa1b7687fe 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -31324,7 +31324,7 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode) case 1215: value = 3193; break; /* hint --> clrbhb. */ case 1235: value = 1239; break; /* dsb --> pssbb. */ case 1236: value = 1236; break; /* dsb --> dsb. */ - case 1254: value = 1264; break; /* sys --> cosp. */ + case 1254: value = 3194; break; /* sys --> trcit. */ case 1259: value = 1259; break; /* wfet --> wfet. */ case 1260: value = 1260; break; /* wfit --> wfit. */ case 1325: value = 2078; break; /* and --> bic. */ @@ -31511,6 +31511,7 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode) case 1239: value = 1238; break; /* pssbb --> ssbb. */ case 1238: value = 1237; break; /* ssbb --> dfb. */ case 1237: value = 1235; break; /* dfb --> dsb. */ + case 3194: value = 1264; break; /* trcit --> cosp. */ case 1264: value = 1263; break; /* cosp --> cpp. */ case 1263: value = 1262; break; /* cpp --> dvp. */ case 1262: value = 1261; break; /* dvp --> cfp. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 6734794ba56..5dd0864c0ab 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2580,6 +2580,8 @@ static const aarch64_feature_set aarch64_feature_chk = AARCH64_FEATURE (CHK); static const aarch64_feature_set aarch64_feature_gcs = AARCH64_FEATURE (GCS); +static const aarch64_feature_set aarch64_feature_ite = + AARCH64_FEATURE (ITE); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2642,6 +2644,7 @@ static const aarch64_feature_set aarch64_feature_gcs = #define CSSC &aarch64_feature_cssc #define CHK &aarch64_feature_chk #define GCS &aarch64_feature_gcs +#define ITE &aarch64_feature_ite #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2847,6 +2850,9 @@ static const aarch64_feature_set aarch64_feature_gcs = #define PREDRES2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, PREDRES2, OPS, QUALS, FLAGS, 0, 0, NULL } +#define ITE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, ITE, OPS, QUALS, FLAGS, 0, 0, NULL } + const struct aarch64_opcode aarch64_opcode_table[] = { /* Add/subtract (with carry). */ @@ -4673,7 +4679,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = _SVE_INSN ("ldff1sw", 0xc540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0), _SVE_INSN ("ldff1sw", 0xc560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0), _SVE_INSN ("ldff1sw", 0xc520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0), - + _SVE_INSN ("ldff1w", 0x85006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0), _SVE_INSN ("ldff1w", 0x85206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0), _SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, F_OD(1), 0), @@ -6117,6 +6123,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = command-line flags. */ CORE_INSN ("clrbhb", 0xd50322df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), + ITE_INSN ("trcit", 0xd50b72e0, 0xffffffe0, ic_system, OP1 (Rt), QL_I1X, F_ALIAS), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; |