diff options
| author | srinath <srinath.parvathaneni@arm.com> | 2024-01-08 14:08:58 +0000 |
|---|---|---|
| committer | srinath <srinath.parvathaneni@arm.com> | 2024-01-08 14:09:37 +0000 |
| commit | bde5096397811b8859813afab21dd3e8a5b0082b (patch) | |
| tree | 35cf02928ea71336bf82dfe54b1744c7b97248dd /opcodes | |
| parent | 53ba8c111774d318fa572669ba4d3b76121e102b (diff) | |
aarch64: Add ite feature system registers.
This patch adds ite feature (FEAT_ITE) system registers,
trcitecr_el1, trcitecr_el12, trcitecr_el2 and trciteedcr.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-sys-regs.def | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index b6e3d1a57fa..054c12cb7e5 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -984,6 +984,10 @@ SYSREG ("trcimspec6", CPENC (2,1,0,6,7), 0, AARCH64_NO_FEATURES) SYSREG ("trcimspec7", CPENC (2,1,0,7,7), 0, AARCH64_NO_FEATURES) SYSREG ("trcitctrl", CPENC (2,1,7,0,4), 0, AARCH64_NO_FEATURES) + SYSREG ("trcitecr_el1", CPENC (3,0,1,2,3), F_ARCHEXT, AARCH64_FEATURE (ITE)) + SYSREG ("trcitecr_el12", CPENC (3,5,1,2,3), F_ARCHEXT, AARCH64_FEATURE (ITE)) + SYSREG ("trcitecr_el2", CPENC (3,4,1,2,3), F_ARCHEXT, AARCH64_FEATURE (ITE)) + SYSREG ("trciteedcr", CPENC (2,1,0,2,1), F_ARCHEXT, AARCH64_FEATURE (ITE)) SYSREG ("trclar", CPENC (2,1,7,12,6), F_REG_WRITE, AARCH64_NO_FEATURES) SYSREG ("trclsr", CPENC (2,1,7,13,6), F_REG_READ, AARCH64_NO_FEATURES) SYSREG ("trcoslar", CPENC (2,1,1,0,4), F_REG_WRITE, AARCH64_NO_FEATURES) |