diff options
| author | Tejas Joshi <TejasSanjay.Joshi@amd.com> | 2023-12-20 10:40:21 +0530 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-01-05 09:28:52 +0100 |
| commit | b143c979b45ea646a2b0f61f375b4e92825eb428 (patch) | |
| tree | 4c46f2e0c5d68e3a0b966af26096026e5a22a474 /opcodes | |
| parent | 6d548ee95c12fcff446a51beea5c27f0f8df2166 (diff) | |
Add AMD znver5 processor support
gas/
* config/tc-i386.c (cpu_arch): Add znver5 ARCH.
* doc/c-i386.texi: Add znver5.
* testsuite/gas/i386/arch-15.d: New.
* testsuite/gas/i386/arch-15.s: Likewise.
* testsuite/gas/i386/arch-15-znver5.d: Likewise.
* testsuite/gas/i386/i386.exp: Add new znver5 test cases.
* testsuite/gas/i386/x86-64.exp: Likewise.
* testsuite/gas/i386/x86-64-arch-5.d: Likewise.
* testsuite/gas/i386/x86-64-arch-5.s: Likewise.
* testsuite/gas/i386/x86-64-arch-5-znver5.d: Likewise.
opcodes/
* i386-gen.c (isa_dependencies): Add ZNVER5 dependencies.
* i386-init.h: Re-generated.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/i386-gen.c | 2 | ||||
| -rw-r--r-- | opcodes/i386-init.h | 10 |
2 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index a54635e1084..e8b92e32f45 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -94,6 +94,8 @@ static const dependency isa_dependencies[] = "ZNVER2|INVLPGB|TLBSYNC|VAES|VPCLMULQDQ|INVPCID|SNP|OSPKE" }, { "ZNVER4", "ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" }, + { "ZNVER5", + "ZNVER4|AVX_VNNI|MOVDIRI|MOVDIR64B|AVX512_VP2INTERSECT|PREFETCHI" }, { "BTVER1", "GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" }, { "BTVER2", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index 59bcbf5dc95..9c67063d746 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -1698,6 +1698,16 @@ 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, \ 0, 1, 1, 0, 0, 0 } } +#define CPU_ZNVER5_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ + 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, \ + 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, \ + 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, \ + 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \ + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, \ + 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, \ + 0, 1, 1, 0, 0, 0 } } + #define CPU_BTVER1_FLAGS \ { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |