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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-17 14:20:53 +0800 |
|---|---|---|
| committer | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-12-14 09:54:19 +0100 |
| commit | 8cb16b68584e14aade8de166c75e1d85e38507bd (patch) | |
| tree | 05c2821251d0efffa731fa57d99f10d4b6046770 /opcodes | |
| parent | e20298da05f212c04022c4f1a9991e09e2199c9a (diff) | |
RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the
XTheadFmv extension in T-Head specific is incorrect, and it also has
some impact on the implementation of the binutils, so this patch
corrects this.
For details see:
https://github.com/T-head-Semi/thead-extension-spec/pull/34
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-fmv.d: Correct test.
* testsuite/gas/riscv/x-thead-fmv.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding.
(MASK_TH_FMV_HW_X): Likewise.
(MATCH_TH_FMV_X_HW): Likewise.
(MASK_TH_FMV_X_HW): Likewise.
opcodes/ChangeLog:
* riscv-opc.c: Correct operands.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 24afb360e03..bf388cdaa2f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2157,7 +2157,7 @@ const struct riscv_opcode riscv_opcodes[] = {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadFmv instructions. */ -{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, +{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "D,s", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadInt instructions. */ |