diff options
| author | mengqinggang <mengqinggang@loongson.cn> | 2023-11-23 15:42:49 +0800 |
|---|---|---|
| committer | liuzhensong <liuzhensong@loongson.cn> | 2023-12-18 18:36:29 +0800 |
| commit | 784d5a936a73f0f0676fef782422c54ed280f599 (patch) | |
| tree | 0c41763672e3808fdb6fae3e1f1872c33b2abf2d /opcodes | |
| parent | dc5f359ed6a36d2c895d89c3e4886f3a2b6d9232 (diff) | |
LoongArch: Add call36 and tail36 pseudo instructions for medium code model
For tail36, it is necessary to explicitly indicate the temporary register.
Therefore, the compiler and users will know that the tail will use a register.
call36 func
pcalau18i $ra, %call36(func)
jirl $ra, $ra, 0;
tail36 $t0, func
pcalau18i $t0, %call36(func)
jirl $zero, $t0, 0;
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/loongarch-opc.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index 15c7da6340c..b47817f8f4b 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -293,6 +293,15 @@ const char *const loongarch_x_normal_name[32] = &LARCH_opts.ase_lp64, \ &LARCH_opts.ase_gpcr +#define INSN_LA_CALL \ + "pcaddu18i $ra,%%call36(%1);" \ + "jirl $ra,$ra,0;", \ + 0, 0 + +#define INSN_LA_TAIL \ + "pcaddu18i %1,%%call36(%2);" \ + "jirl $zero,%1,0;", \ + 0, 0 static struct loongarch_opcode loongarch_macro_opcodes[] = { @@ -340,6 +349,8 @@ static struct loongarch_opcode loongarch_macro_opcodes[] = { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 }, { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 }, { 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 }, + { 0, 0, "call36", "la", INSN_LA_CALL, 0 }, + { 0, 0, "tail36", "r,la", INSN_LA_TAIL, 0 }, { 0, 0, "pcaddi", "r,la", "pcaddi %1, %%pcrel_20(%2)", &LARCH_opts.ase_ilp32, 0, 0 }, { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; |