diff options
| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-01-15 09:35:55 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-15 11:45:41 +0000 |
| commit | 88601c2d941b004b443dc4bfdf3b93ea1983d136 (patch) | |
| tree | d2ed31930c0f82a30e5090f3a1b70e3a8f3ca681 /opcodes/aarch64-asm.c | |
| parent | 89e06ec1521898892e27615714f51d30703d5139 (diff) | |
aarch64: Add support for FEAT_SVE2p1.
Hi,
This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature
along with +sve2p1 optional flag to enabe this feature.
Also support for following SVE2p1 instructions is added
addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Diffstat (limited to 'opcodes/aarch64-asm.c')
| -rw-r--r-- | opcodes/aarch64-asm.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 3fac127a589..1dfd59df42d 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1981,6 +1981,20 @@ do_special_encoding (struct aarch64_inst *inst) gen_sub_field (FLD_imm5, 0, num + 1, &field); insert_field_2 (&field, &inst->value, 1 << num, inst->opcode->mask); } + + if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs) + { + enum aarch64_opnd_qualifier qualifier[1]; + aarch64_insn value1 = 0; + idx = 0; + qualifier[0] = inst->operands[idx].qualifier; + qualifier[1] = inst->operands[idx+2].qualifier; + value = aarch64_get_qualifier_standard_value (qualifier[0]); + value1 = aarch64_get_qualifier_standard_value (qualifier[1]); + assert ((value >> 1) == value1); + insert_field (FLD_size, &inst->value, value1, inst->opcode->mask); + } + if (inst->opcode->flags & F_GPRSIZE_IN_Q) { /* Use Rt to encode in the case of e.g. |