aarch64: Add SLC target for PRFM instruction.

This patch adds support for FEAT_PRFMSLC feature which enables
SLC target for PRFM instructions.

3 files changed, 38 insertions, 32 deletions

diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d
index bb1a94cb020..dbb7c0a96ff 100644
--- a/gas/testsuite/gas/aarch64/system.d
+++ b/gas/testsuite/gas/aarch64/system.d
@@ -240,16 +240,16 @@ Disassembly of section \.text:
 .*:	f8af6be5 	prfm	pldl3strm, \[sp, x15\]
 .*:	f8be58e5 	prfm	pldl3strm, \[x7, w30, uxtw #3\]
 .*:	f9800c65 	prfm	pldl3strm, \[x3, #24\]
-.*:	d8000006 	prfm	#0x06, 0 <LABEL1>
+.*:	d8000006 	prfm	pldslckeep, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6be6 	prfm	#0x06, \[sp, x15\]
-.*:	f8be58e6 	prfm	#0x06, \[x7, w30, uxtw #3\]
-.*:	f9800c66 	prfm	#0x06, \[x3, #24\]
-.*:	d8000007 	prfm	#0x07, 0 <LABEL1>
+.*:	f8af6be6 	prfm	pldslckeep, \[sp, x15\]
+.*:	f8be58e6 	prfm	pldslckeep, \[x7, w30, uxtw #3\]
+.*:	f9800c66 	prfm	pldslckeep, \[x3, #24\]
+.*:	d8000007 	prfm	pldslcstrm, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6be7 	prfm	#0x07, \[sp, x15\]
-.*:	f8be58e7 	prfm	#0x07, \[x7, w30, uxtw #3\]
-.*:	f9800c67 	prfm	#0x07, \[x3, #24\]
+.*:	f8af6be7 	prfm	pldslcstrm, \[sp, x15\]
+.*:	f8be58e7 	prfm	pldslcstrm, \[x7, w30, uxtw #3\]
+.*:	f9800c67 	prfm	pldslcstrm, \[x3, #24\]
 .*:	d8000008 	prfm	plil1keep, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
 .*:	f8af6be8 	prfm	plil1keep, \[sp, x15\]
@@ -280,16 +280,16 @@ Disassembly of section \.text:
 .*:	f8af6bed 	prfm	plil3strm, \[sp, x15\]
 .*:	f8be58ed 	prfm	plil3strm, \[x7, w30, uxtw #3\]
 .*:	f9800c6d 	prfm	plil3strm, \[x3, #24\]
-.*:	d800000e 	prfm	#0x0e, 0 <LABEL1>
+.*:	d800000e 	prfm	plislckeep, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bee 	prfm	#0x0e, \[sp, x15\]
-.*:	f8be58ee 	prfm	#0x0e, \[x7, w30, uxtw #3\]
-.*:	f9800c6e 	prfm	#0x0e, \[x3, #24\]
-.*:	d800000f 	prfm	#0x0f, 0 <LABEL1>
+.*:	f8af6bee 	prfm	plislckeep, \[sp, x15\]
+.*:	f8be58ee 	prfm	plislckeep, \[x7, w30, uxtw #3\]
+.*:	f9800c6e 	prfm	plislckeep, \[x3, #24\]
+.*:	d800000f 	prfm	plislcstrm, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bef 	prfm	#0x0f, \[sp, x15\]
-.*:	f8be58ef 	prfm	#0x0f, \[x7, w30, uxtw #3\]
-.*:	f9800c6f 	prfm	#0x0f, \[x3, #24\]
+.*:	f8af6bef 	prfm	plislcstrm, \[sp, x15\]
+.*:	f8be58ef 	prfm	plislcstrm, \[x7, w30, uxtw #3\]
+.*:	f9800c6f 	prfm	plislcstrm, \[x3, #24\]
 .*:	d8000010 	prfm	pstl1keep, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
 .*:	f8af6bf0 	prfm	pstl1keep, \[sp, x15\]
@@ -320,16 +320,16 @@ Disassembly of section \.text:
 .*:	f8af6bf5 	prfm	pstl3strm, \[sp, x15\]
 .*:	f8be58f5 	prfm	pstl3strm, \[x7, w30, uxtw #3\]
 .*:	f9800c75 	prfm	pstl3strm, \[x3, #24\]
-.*:	d8000016 	prfm	#0x16, 0 <LABEL1>
+.*:	d8000016 	prfm	pstslckeep, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bf6 	prfm	#0x16, \[sp, x15\]
-.*:	f8be58f6 	prfm	#0x16, \[x7, w30, uxtw #3\]
-.*:	f9800c76 	prfm	#0x16, \[x3, #24\]
-.*:	d8000017 	prfm	#0x17, 0 <LABEL1>
+.*:	f8af6bf6 	prfm	pstslckeep, \[sp, x15\]
+.*:	f8be58f6 	prfm	pstslckeep, \[x7, w30, uxtw #3\]
+.*:	f9800c76 	prfm	pstslckeep, \[x3, #24\]
+.*:	d8000017 	prfm	pstslcstrm, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bf7 	prfm	#0x17, \[sp, x15\]
-.*:	f8be58f7 	prfm	#0x17, \[x7, w30, uxtw #3\]
-.*:	f9800c77 	prfm	#0x17, \[x3, #24\]
+.*:	f8af6bf7 	prfm	pstslcstrm, \[sp, x15\]
+.*:	f8be58f7 	prfm	pstslcstrm, \[x7, w30, uxtw #3\]
+.*:	f9800c77 	prfm	pstslcstrm, \[x3, #24\]
 .*:	d8000018 	prfm	#0x18, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
 .*:	f9800c78 	prfm	#0x18, \[x3, #24\]
@@ -360,17 +360,23 @@ Disassembly of section \.text:
 .*:	f9800c63 	prfm	pldl2strm, \[x3, #24\]
 .*:	f9800c64 	prfm	pldl3keep, \[x3, #24\]
 .*:	f9800c65 	prfm	pldl3strm, \[x3, #24\]
+.*:	f9800c66 	prfm	pldslckeep, \[x3, #24\]
+.*:	f9800c67 	prfm	pldslcstrm, \[x3, #24\]
 .*:	f9800c68 	prfm	plil1keep, \[x3, #24\]
 .*:	f9800c69 	prfm	plil1strm, \[x3, #24\]
 .*:	f9800c6a 	prfm	plil2keep, \[x3, #24\]
 .*:	f9800c6b 	prfm	plil2strm, \[x3, #24\]
 .*:	f9800c6c 	prfm	plil3keep, \[x3, #24\]
 .*:	f9800c6d 	prfm	plil3strm, \[x3, #24\]
+.*:	f9800c6e 	prfm	plislckeep, \[x3, #24\]
+.*:	f9800c6f 	prfm	plislcstrm, \[x3, #24\]
 .*:	f9800c70 	prfm	pstl1keep, \[x3, #24\]
 .*:	f9800c71 	prfm	pstl1strm, \[x3, #24\]
 .*:	f9800c72 	prfm	pstl2keep, \[x3, #24\]
 .*:	f9800c73 	prfm	pstl2strm, \[x3, #24\]
 .*:	f9800c74 	prfm	pstl3keep, \[x3, #24\]
 .*:	f9800c75 	prfm	pstl3strm, \[x3, #24\]
-.*:	f8a04817 	prfm	#0x17, \[x0, w0, uxtw\]
+.*:	f9800c76 	prfm	pstslckeep, \[x3, #24\]
+.*:	f9800c77 	prfm	pstslcstrm, \[x3, #24\]
+.*:	f8a04817 	prfm	pstslcstrm, \[x0, w0, uxtw\]
 .*:	f8a04818 	rprfm	pldkeep, x0, \[x0\]
diff --git a/gas/testsuite/gas/aarch64/system.s b/gas/testsuite/gas/aarch64/system.s
index 48e7bfeb103..9457b392f78 100644
--- a/gas/testsuite/gas/aarch64/system.s
+++ b/gas/testsuite/gas/aarch64/system.s
@@ -87,7 +87,7 @@
 	//
 
 	.irp op, pld, pli, pst
-	.irp l, l1, l2, l3
+	.irp l, l1, l2, l3, slc
 	.irp t, keep, strm
 	prfm	\op\l\t, [x3, #24]
 	.endr
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index f8d4c1a4d33..e4b3522c02f 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -575,24 +575,24 @@ const struct aarch64_name_value_pair aarch64_prfops[32] =
   { "pldl2strm", B(0, 2, 1) },
   { "pldl3keep", B(0, 3, 0) },
   { "pldl3strm", B(0, 3, 1) },
-  { NULL, 0x06 },
-  { NULL, 0x07 },
+  { "pldslckeep", B(0, 4, 0) },
+  { "pldslcstrm", B(0, 4, 1) },
   { "plil1keep", B(1, 1, 0) },
   { "plil1strm", B(1, 1, 1) },
   { "plil2keep", B(1, 2, 0) },
   { "plil2strm", B(1, 2, 1) },
   { "plil3keep", B(1, 3, 0) },
   { "plil3strm", B(1, 3, 1) },
-  { NULL, 0x0e },
-  { NULL, 0x0f },
+  { "plislckeep", B(1, 4, 0) },
+  { "plislcstrm", B(1, 4, 1) },
   { "pstl1keep", B(2, 1, 0) },
   { "pstl1strm", B(2, 1, 1) },
   { "pstl2keep", B(2, 2, 0) },
   { "pstl2strm", B(2, 2, 1) },
   { "pstl3keep", B(2, 3, 0) },
   { "pstl3strm", B(2, 3, 1) },
-  { NULL, 0x16 },
-  { NULL, 0x17 },
+  { "pstslckeep", B(2, 4, 0) },
+  { "pstslcstrm", B(2, 4, 1) },
   { NULL, 0x18 },
   { NULL, 0x19 },
   { NULL, 0x1a },