aarch64: Fix tlbi and tlbip instructions

There are some tlbi operations that don't have a corresponding tlbip operation,
but we were incorrectly using the same list for both.  Add the missing tlbi
*nxs operations, and use the F_REG_128 flag to filter tlbi operations that
don't have a tlbip analogue.  For increased clarity, I have also used a macro
to reduce duplication between the 'nxs' and non-'nxs' variants, and added a
test to verify that no invalid combinations are accepted.

Additionally, fix two missing checks for AARCH64_OPND_SYSREG_TLBIP that were
preventing disassembly of tlbip instructions.

11 files changed, 335 insertions, 290 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index b455899ccc1..8141ea4823e 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4858,7 +4858,7 @@ parse_sys_reg (char **str, htab_t sys_regs,
    for the option, or NULL.  */
 
 static const aarch64_sys_ins_reg *
-parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
+parse_sys_ins_reg (char **str, htab_t sys_ins_regs, bool sysreg128_p)
 {
   char *p, *q;
   char buf[AARCH64_MAX_SYSREG_NAME_LEN];
@@ -4877,7 +4877,7 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
     return NULL;
 
   o = str_hash_find (sys_ins_regs, buf);
-  if (!o)
+  if (!o || (sysreg128_p && !aarch64_sys_reg_128bit_p (o->flags)))
     return NULL;
 
   if (!aarch64_sys_ins_reg_supported_p (cpu_variant,
@@ -7658,28 +7658,32 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 
 	case AARCH64_OPND_SYSREG_IC:
 	  inst.base.operands[i].sysins_op =
-	    parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
+	    parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh, false);
 	  goto sys_reg_ins;
 
 	case AARCH64_OPND_SYSREG_DC:
 	  inst.base.operands[i].sysins_op =
-	    parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
+	    parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh, false);
 	  goto sys_reg_ins;
 
 	case AARCH64_OPND_SYSREG_AT:
 	  inst.base.operands[i].sysins_op =
-	    parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
+	    parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh, false);
 	  goto sys_reg_ins;
 
 	case AARCH64_OPND_SYSREG_SR:
 	  inst.base.operands[i].sysins_op =
-	    parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh);
+	    parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh, false);
 	  goto sys_reg_ins;
 
 	case AARCH64_OPND_SYSREG_TLBI:
+	  inst.base.operands[i].sysins_op =
+	    parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh, false);
+	  goto sys_reg_ins;
+
 	case AARCH64_OPND_SYSREG_TLBIP:
 	  inst.base.operands[i].sysins_op =
-	    parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
+	    parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh, true);
 	sys_reg_ins:
 	  if (inst.base.operands[i].sysins_op == NULL)
 	    {
diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
index 69450747b15..3d87cdbac4d 100644
--- a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
@@ -1,4 +1,2 @@
 [^:]*: Assembler messages:
 [^:]*:5: Error: missing register at operand 2 -- `tlbip vale3nxs'
-[^:]*:9: Error: extraneous register at operand 2 -- `tlbip paall,x0'
-[^:]*:10: Error: extraneous register at operand 2 -- `tlbip paall,x0,x1'
diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
index 1e02b71fdba..538fe94b796 100644
--- a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
@@ -3,8 +3,3 @@
 	/* TLBIP operands marked with the F_HASXT don not allow xzr to be used
 	as GPR arguments and so require at least one register to be specified.  */
 	tlbip	vale3nxs
-
-	/* Conversely, those without the flag do not allow us to specify registers,
-	so the only accepted alternative is the complete omission of optional ops.  */
-	tlbip	paall, x0
-	tlbip	paall, x0, x1
diff --git a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
index 977dedbf843..0aeeb79a1e7 100644
--- a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
+++ b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
@@ -5,13 +5,12 @@
 Disassembly of section \.text:
 
 0+ <\.text>:
-[^:]*:	d54e97a0 	sysp	#6, C9, C7, #5, x0, x1
-[^:]*:	d54e97a0 	sysp	#6, C9, C7, #5, x0, x1
-[^:]*:	d54e97a2 	sysp	#6, C9, C7, #5, x2, x3
-[^:]*:	d54e97a2 	sysp	#6, C9, C7, #5, x2, x3
-[^:]*:	d54e879f 	sysp	#6, C8, C7, #4
-[^:]*:	d54e97bf 	sysp	#6, C9, C7, #5
-[^:]*:	d54e97a0 	sysp	#6, C9, C7, #5, x0, x1
-[^:]*:	d54e97a0 	sysp	#6, C9, C7, #5, x0, x1
-[^:]*:	d54e97a2 	sysp	#6, C9, C7, #5, x2, x3
-[^:]*:	d54e97a2 	sysp	#6, C9, C7, #5, x2, x3
+[^:]*:	d54e97a0 	tlbip	vale3nxs, x0, x1
+[^:]*:	d54e97a0 	tlbip	vale3nxs, x0, x1
+[^:]*:	d54e97a2 	tlbip	vale3nxs, x2, x3
+[^:]*:	d54e97a2 	tlbip	vale3nxs, x2, x3
+[^:]*:	d54e97bf 	tlbip	vale3nxs, xzr
+[^:]*:	d54e97a0 	tlbip	vale3nxs, x0, x1
+[^:]*:	d54e97a0 	tlbip	vale3nxs, x0, x1
+[^:]*:	d54e97a2 	tlbip	vale3nxs, x2, x3
+[^:]*:	d54e97a2 	tlbip	vale3nxs, x2, x3
diff --git a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
index 3635db1d039..afb5bf385c2 100644
--- a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
+++ b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
@@ -7,11 +7,6 @@
 	tlbip	vale3nxs, x2
 	tlbip	vale3nxs, x2, x3
 
-
-	/* Conversely, those without the flag do not allow us to specify registers,
-	so the only accepted alternative is the complete omission of optional ops.  */
-	tlbip	paall
-
 	/* No such checking is carried out when the same instruction is issued
 	directly via the sysp implementation defined maintenance instruction,
 	such that both GRPs are optional.  */
diff --git a/gas/testsuite/gas/aarch64/tlbip-invalid.d b/gas/testsuite/gas/aarch64/tlbip-invalid.d
new file mode 100644
index 00000000000..46b79cedd53
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbip-invalid.d
@@ -0,0 +1 @@
+#error_output: tlbip-invalid.l
diff --git a/gas/testsuite/gas/aarch64/tlbip-invalid.l b/gas/testsuite/gas/aarch64/tlbip-invalid.l
new file mode 100644
index 00000000000..a104886057d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbip-invalid.l
@@ -0,0 +1,49 @@
+[^:]*: Assembler messages:
+.*: Error: unknown or missing operation name at operand 1 -- `tlbi paallosnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbi paallnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbi rpaosnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbi rpalosnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalle1os'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip aside1os'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalle1is'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip aside1is'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalle1'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip aside1'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle2os'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle1os'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalls12e1os'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle2is'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle1is'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalls12e1is'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle2'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle1'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalls12e1'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle3os'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip paallos'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle3is'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip rpaos'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip rpalos'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle3'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip paall'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalle1osnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip aside1osnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalle1isnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip aside1isnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalle1nxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip aside1nxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle2osnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle1osnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalls12e1osnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle2isnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle1isnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalls12e1isnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle2nxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle1nxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip vmalls12e1nxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle3osnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip paallosnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle3isnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip rpaosnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip rpalosnxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip alle3nxs'
+.*: Error: unknown or missing operation name at operand 1 -- `tlbip paallnxs'
diff --git a/gas/testsuite/gas/aarch64/tlbip-invalid.s b/gas/testsuite/gas/aarch64/tlbip-invalid.s
new file mode 100644
index 00000000000..65eb78d1143
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbip-invalid.s
@@ -0,0 +1,52 @@
+.arch armv8-a+d128+xs
+
+	tlbi paallosnxs
+	tlbi paallnxs
+	tlbi rpaosnxs
+	tlbi rpalosnxs
+
+	tlbip vmalle1os
+	tlbip aside1os
+	tlbip vmalle1is
+	tlbip aside1is
+	tlbip vmalle1
+	tlbip aside1
+	tlbip alle2os
+	tlbip alle1os
+	tlbip vmalls12e1os
+	tlbip alle2is
+	tlbip alle1is
+	tlbip vmalls12e1is
+	tlbip alle2
+	tlbip alle1
+	tlbip vmalls12e1
+	tlbip alle3os
+	tlbip paallos
+	tlbip alle3is
+	tlbip rpaos
+	tlbip rpalos
+	tlbip alle3
+	tlbip paall
+
+	tlbip vmalle1osnxs
+	tlbip aside1osnxs
+	tlbip vmalle1isnxs
+	tlbip aside1isnxs
+	tlbip vmalle1nxs
+	tlbip aside1nxs
+	tlbip alle2osnxs
+	tlbip alle1osnxs
+	tlbip vmalls12e1osnxs
+	tlbip alle2isnxs
+	tlbip alle1isnxs
+	tlbip vmalls12e1isnxs
+	tlbip alle2nxs
+	tlbip alle1nxs
+	tlbip vmalls12e1nxs
+	tlbip alle3osnxs
+	tlbip paallosnxs
+	tlbip alle3isnxs
+	tlbip rpaosnxs
+	tlbip rpalosnxs
+	tlbip alle3nxs
+	tlbip paallnxs
diff --git a/gas/testsuite/gas/aarch64/tlbip.d b/gas/testsuite/gas/aarch64/tlbip.d
index 81c22cf8e20..6acdedb490b 100644
--- a/gas/testsuite/gas/aarch64/tlbip.d
+++ b/gas/testsuite/gas/aarch64/tlbip.d
@@ -5,123 +5,123 @@
 Disassembly of section \.text:
 
 0+ <.*>:
-   0:	d5488120 	sysp	#0, C8, C1, #1, x0, x1
-   4:	d5488160 	sysp	#0, C8, C1, #3, x0, x1
-   8:	d54881a0 	sysp	#0, C8, C1, #5, x0, x1
-   c:	d54881e0 	sysp	#0, C8, C1, #7, x0, x1
-  10:	d5488220 	sysp	#0, C8, C2, #1, x0, x1
-  14:	d5488260 	sysp	#0, C8, C2, #3, x0, x1
-  18:	d54882a0 	sysp	#0, C8, C2, #5, x0, x1
-  1c:	d54882e0 	sysp	#0, C8, C2, #7, x0, x1
-  20:	d5488320 	sysp	#0, C8, C3, #1, x0, x1
-  24:	d5488360 	sysp	#0, C8, C3, #3, x0, x1
-  28:	d54883a0 	sysp	#0, C8, C3, #5, x0, x1
-  2c:	d54883e0 	sysp	#0, C8, C3, #7, x0, x1
-  30:	d5488520 	sysp	#0, C8, C5, #1, x0, x1
-  34:	d5488560 	sysp	#0, C8, C5, #3, x0, x1
-  38:	d54885a0 	sysp	#0, C8, C5, #5, x0, x1
-  3c:	d54885e0 	sysp	#0, C8, C5, #7, x0, x1
-  40:	d5488620 	sysp	#0, C8, C6, #1, x0, x1
-  44:	d5488660 	sysp	#0, C8, C6, #3, x0, x1
-  48:	d54886a0 	sysp	#0, C8, C6, #5, x0, x1
-  4c:	d54886e0 	sysp	#0, C8, C6, #7, x0, x1
-  50:	d5488720 	sysp	#0, C8, C7, #1, x0, x1
-  54:	d5488760 	sysp	#0, C8, C7, #3, x0, x1
-  58:	d54887a0 	sysp	#0, C8, C7, #5, x0, x1
-  5c:	d54887e0 	sysp	#0, C8, C7, #7, x0, x1
-  60:	d5489120 	sysp	#0, C9, C1, #1, x0, x1
-  64:	d5489160 	sysp	#0, C9, C1, #3, x0, x1
-  68:	d54891a0 	sysp	#0, C9, C1, #5, x0, x1
-  6c:	d54891e0 	sysp	#0, C9, C1, #7, x0, x1
-  70:	d5489220 	sysp	#0, C9, C2, #1, x0, x1
-  74:	d5489260 	sysp	#0, C9, C2, #3, x0, x1
-  78:	d54892a0 	sysp	#0, C9, C2, #5, x0, x1
-  7c:	d54892e0 	sysp	#0, C9, C2, #7, x0, x1
-  80:	d5489320 	sysp	#0, C9, C3, #1, x0, x1
-  84:	d5489360 	sysp	#0, C9, C3, #3, x0, x1
-  88:	d54893a0 	sysp	#0, C9, C3, #5, x0, x1
-  8c:	d54893e0 	sysp	#0, C9, C3, #7, x0, x1
-  90:	d5489520 	sysp	#0, C9, C5, #1, x0, x1
-  94:	d5489560 	sysp	#0, C9, C5, #3, x0, x1
-  98:	d54895a0 	sysp	#0, C9, C5, #5, x0, x1
-  9c:	d54895e0 	sysp	#0, C9, C5, #7, x0, x1
-  a0:	d5489620 	sysp	#0, C9, C6, #1, x0, x1
-  a4:	d5489660 	sysp	#0, C9, C6, #3, x0, x1
-  a8:	d54896a0 	sysp	#0, C9, C6, #5, x0, x1
-  ac:	d54896e0 	sysp	#0, C9, C6, #7, x0, x1
-  b0:	d5489720 	sysp	#0, C9, C7, #1, x0, x1
-  b4:	d5489760 	sysp	#0, C9, C7, #3, x0, x1
-  b8:	d54897a0 	sysp	#0, C9, C7, #5, x0, x1
-  bc:	d54897e0 	sysp	#0, C9, C7, #7, x0, x1
-  c0:	d54c8020 	sysp	#4, C8, C0, #1, x0, x1
-  c4:	d54c8040 	sysp	#4, C8, C0, #2, x0, x1
-  c8:	d54c80a0 	sysp	#4, C8, C0, #5, x0, x1
-  cc:	d54c80c0 	sysp	#4, C8, C0, #6, x0, x1
-  d0:	d54c8120 	sysp	#4, C8, C1, #1, x0, x1
-  d4:	d54c81a0 	sysp	#4, C8, C1, #5, x0, x1
-  d8:	d54c8220 	sysp	#4, C8, C2, #1, x0, x1
-  dc:	d54c82a0 	sysp	#4, C8, C2, #5, x0, x1
-  e0:	d54c8320 	sysp	#4, C8, C3, #1, x0, x1
-  e4:	d54c83a0 	sysp	#4, C8, C3, #5, x0, x1
-  e8:	d54c8400 	sysp	#4, C8, C4, #0, x0, x1
-  ec:	d54c8420 	sysp	#4, C8, C4, #1, x0, x1
-  f0:	d54c8440 	sysp	#4, C8, C4, #2, x0, x1
-  f4:	d54c8460 	sysp	#4, C8, C4, #3, x0, x1
-  f8:	d54c8480 	sysp	#4, C8, C4, #4, x0, x1
-  fc:	d54c84a0 	sysp	#4, C8, C4, #5, x0, x1
- 100:	d54c84c0 	sysp	#4, C8, C4, #6, x0, x1
- 104:	d54c84e0 	sysp	#4, C8, C4, #7, x0, x1
- 108:	d54c8520 	sysp	#4, C8, C5, #1, x0, x1
- 10c:	d54c85a0 	sysp	#4, C8, C5, #5, x0, x1
- 110:	d54c8620 	sysp	#4, C8, C6, #1, x0, x1
- 114:	d54c86a0 	sysp	#4, C8, C6, #5, x0, x1
- 118:	d54c8720 	sysp	#4, C8, C7, #1, x0, x1
- 11c:	d54c87a0 	sysp	#4, C8, C7, #5, x0, x1
- 120:	d54c9020 	sysp	#4, C9, C0, #1, x0, x1
- 124:	d54c9040 	sysp	#4, C9, C0, #2, x0, x1
- 128:	d54c90a0 	sysp	#4, C9, C0, #5, x0, x1
- 12c:	d54c90c0 	sysp	#4, C9, C0, #6, x0, x1
- 130:	d54c9120 	sysp	#4, C9, C1, #1, x0, x1
- 134:	d54c91a0 	sysp	#4, C9, C1, #5, x0, x1
- 138:	d54c9220 	sysp	#4, C9, C2, #1, x0, x1
- 13c:	d54c92a0 	sysp	#4, C9, C2, #5, x0, x1
- 140:	d54c9320 	sysp	#4, C9, C3, #1, x0, x1
- 144:	d54c93a0 	sysp	#4, C9, C3, #5, x0, x1
- 148:	d54c9400 	sysp	#4, C9, C4, #0, x0, x1
- 14c:	d54c9420 	sysp	#4, C9, C4, #1, x0, x1
- 150:	d54c9440 	sysp	#4, C9, C4, #2, x0, x1
- 154:	d54c9460 	sysp	#4, C9, C4, #3, x0, x1
- 158:	d54c9480 	sysp	#4, C9, C4, #4, x0, x1
- 15c:	d54c94a0 	sysp	#4, C9, C4, #5, x0, x1
- 160:	d54c94c0 	sysp	#4, C9, C4, #6, x0, x1
- 164:	d54c94e0 	sysp	#4, C9, C4, #7, x0, x1
- 168:	d54c9520 	sysp	#4, C9, C5, #1, x0, x1
- 16c:	d54c95a0 	sysp	#4, C9, C5, #5, x0, x1
- 170:	d54c9620 	sysp	#4, C9, C6, #1, x0, x1
- 174:	d54c96a0 	sysp	#4, C9, C6, #5, x0, x1
- 178:	d54c9720 	sysp	#4, C9, C7, #1, x0, x1
- 17c:	d54c97a0 	sysp	#4, C9, C7, #5, x0, x1
- 180:	d54e8120 	sysp	#6, C8, C1, #1, x0, x1
- 184:	d54e81a0 	sysp	#6, C8, C1, #5, x0, x1
- 188:	d54e8220 	sysp	#6, C8, C2, #1, x0, x1
- 18c:	d54e82a0 	sysp	#6, C8, C2, #5, x0, x1
- 190:	d54e8320 	sysp	#6, C8, C3, #1, x0, x1
- 194:	d54e83a0 	sysp	#6, C8, C3, #5, x0, x1
- 198:	d54e8520 	sysp	#6, C8, C5, #1, x0, x1
- 19c:	d54e85a0 	sysp	#6, C8, C5, #5, x0, x1
- 1a0:	d54e8620 	sysp	#6, C8, C6, #1, x0, x1
- 1a4:	d54e86a0 	sysp	#6, C8, C6, #5, x0, x1
- 1a8:	d54e8720 	sysp	#6, C8, C7, #1, x0, x1
- 1ac:	d54e87a0 	sysp	#6, C8, C7, #5, x0, x1
- 1b0:	d54e9120 	sysp	#6, C9, C1, #1, x0, x1
- 1b4:	d54e91a0 	sysp	#6, C9, C1, #5, x0, x1
- 1b8:	d54e9220 	sysp	#6, C9, C2, #1, x0, x1
- 1bc:	d54e92a0 	sysp	#6, C9, C2, #5, x0, x1
- 1c0:	d54e9320 	sysp	#6, C9, C3, #1, x0, x1
- 1c4:	d54e93a0 	sysp	#6, C9, C3, #5, x0, x1
- 1c8:	d54e9520 	sysp	#6, C9, C5, #1, x0, x1
- 1cc:	d54e95a0 	sysp	#6, C9, C5, #5, x0, x1
- 1d0:	d54e9620 	sysp	#6, C9, C6, #1, x0, x1
- 1d4:	d54e96a0 	sysp	#6, C9, C6, #5, x0, x1
- 1d8:	d54e9720 	sysp	#6, C9, C7, #1, x0, x1
- 1dc:	d54e97a0 	sysp	#6, C9, C7, #5, x0, x1
\ No newline at end of file
+   0:	d5488120 	tlbip	vae1os, x0, x1
+   4:	d5488160 	tlbip	vaae1os, x0, x1
+   8:	d54881a0 	tlbip	vale1os, x0, x1
+   c:	d54881e0 	tlbip	vaale1os, x0, x1
+  10:	d5488220 	tlbip	rvae1is, x0, x1
+  14:	d5488260 	tlbip	rvaae1is, x0, x1
+  18:	d54882a0 	tlbip	rvale1is, x0, x1
+  1c:	d54882e0 	tlbip	rvaale1is, x0, x1
+  20:	d5488320 	tlbip	vae1is, x0, x1
+  24:	d5488360 	tlbip	vaae1is, x0, x1
+  28:	d54883a0 	tlbip	vale1is, x0, x1
+  2c:	d54883e0 	tlbip	vaale1is, x0, x1
+  30:	d5488520 	tlbip	rvae1os, x0, x1
+  34:	d5488560 	tlbip	rvaae1os, x0, x1
+  38:	d54885a0 	tlbip	rvale1os, x0, x1
+  3c:	d54885e0 	tlbip	rvaale1os, x0, x1
+  40:	d5488620 	tlbip	rvae1, x0, x1
+  44:	d5488660 	tlbip	rvaae1, x0, x1
+  48:	d54886a0 	tlbip	rvale1, x0, x1
+  4c:	d54886e0 	tlbip	rvaale1, x0, x1
+  50:	d5488720 	tlbip	vae1, x0, x1
+  54:	d5488760 	tlbip	vaae1, x0, x1
+  58:	d54887a0 	tlbip	vale1, x0, x1
+  5c:	d54887e0 	tlbip	vaale1, x0, x1
+  60:	d5489120 	tlbip	vae1osnxs, x0, x1
+  64:	d5489160 	tlbip	vaae1osnxs, x0, x1
+  68:	d54891a0 	tlbip	vale1osnxs, x0, x1
+  6c:	d54891e0 	tlbip	vaale1osnxs, x0, x1
+  70:	d5489220 	tlbip	rvae1isnxs, x0, x1
+  74:	d5489260 	tlbip	rvaae1isnxs, x0, x1
+  78:	d54892a0 	tlbip	rvale1isnxs, x0, x1
+  7c:	d54892e0 	tlbip	rvaale1isnxs, x0, x1
+  80:	d5489320 	tlbip	vae1isnxs, x0, x1
+  84:	d5489360 	tlbip	vaae1isnxs, x0, x1
+  88:	d54893a0 	tlbip	vale1isnxs, x0, x1
+  8c:	d54893e0 	tlbip	vaale1isnxs, x0, x1
+  90:	d5489520 	tlbip	rvae1osnxs, x0, x1
+  94:	d5489560 	tlbip	rvaae1osnxs, x0, x1
+  98:	d54895a0 	tlbip	rvale1osnxs, x0, x1
+  9c:	d54895e0 	tlbip	rvaale1osnxs, x0, x1
+  a0:	d5489620 	tlbip	rvae1nxs, x0, x1
+  a4:	d5489660 	tlbip	rvaae1nxs, x0, x1
+  a8:	d54896a0 	tlbip	rvale1nxs, x0, x1
+  ac:	d54896e0 	tlbip	rvaale1nxs, x0, x1
+  b0:	d5489720 	tlbip	vae1nxs, x0, x1
+  b4:	d5489760 	tlbip	vaae1nxs, x0, x1
+  b8:	d54897a0 	tlbip	vale1nxs, x0, x1
+  bc:	d54897e0 	tlbip	vaale1nxs, x0, x1
+  c0:	d54c8020 	tlbip	ipas2e1is, x0, x1
+  c4:	d54c8040 	tlbip	ripas2e1is, x0, x1
+  c8:	d54c80a0 	tlbip	ipas2le1is, x0, x1
+  cc:	d54c80c0 	tlbip	ripas2le1is, x0, x1
+  d0:	d54c8120 	tlbip	vae2os, x0, x1
+  d4:	d54c81a0 	tlbip	vale2os, x0, x1
+  d8:	d54c8220 	tlbip	rvae2is, x0, x1
+  dc:	d54c82a0 	tlbip	rvale2is, x0, x1
+  e0:	d54c8320 	tlbip	vae2is, x0, x1
+  e4:	d54c83a0 	tlbip	vale2is, x0, x1
+  e8:	d54c8400 	tlbip	ipas2e1os, x0, x1
+  ec:	d54c8420 	tlbip	ipas2e1, x0, x1
+  f0:	d54c8440 	tlbip	ripas2e1, x0, x1
+  f4:	d54c8460 	tlbip	ripas2e1os, x0, x1
+  f8:	d54c8480 	tlbip	ipas2le1os, x0, x1
+  fc:	d54c84a0 	tlbip	ipas2le1, x0, x1
+ 100:	d54c84c0 	tlbip	ripas2le1, x0, x1
+ 104:	d54c84e0 	tlbip	ripas2le1os, x0, x1
+ 108:	d54c8520 	tlbip	rvae2os, x0, x1
+ 10c:	d54c85a0 	tlbip	rvale2os, x0, x1
+ 110:	d54c8620 	tlbip	rvae2, x0, x1
+ 114:	d54c86a0 	tlbip	rvale2, x0, x1
+ 118:	d54c8720 	tlbip	vae2, x0, x1
+ 11c:	d54c87a0 	tlbip	vale2, x0, x1
+ 120:	d54c9020 	tlbip	ipas2e1isnxs, x0, x1
+ 124:	d54c9040 	tlbip	ripas2e1isnxs, x0, x1
+ 128:	d54c90a0 	tlbip	ipas2le1isnxs, x0, x1
+ 12c:	d54c90c0 	tlbip	ripas2le1isnxs, x0, x1
+ 130:	d54c9120 	tlbip	vae2osnxs, x0, x1
+ 134:	d54c91a0 	tlbip	vale2osnxs, x0, x1
+ 138:	d54c9220 	tlbip	rvae2isnxs, x0, x1
+ 13c:	d54c92a0 	tlbip	rvale2isnxs, x0, x1
+ 140:	d54c9320 	tlbip	vae2isnxs, x0, x1
+ 144:	d54c93a0 	tlbip	vale2isnxs, x0, x1
+ 148:	d54c9400 	tlbip	ipas2e1osnxs, x0, x1
+ 14c:	d54c9420 	tlbip	ipas2e1nxs, x0, x1
+ 150:	d54c9440 	tlbip	ripas2e1nxs, x0, x1
+ 154:	d54c9460 	tlbip	ripas2e1osnxs, x0, x1
+ 158:	d54c9480 	tlbip	ipas2le1osnxs, x0, x1
+ 15c:	d54c94a0 	tlbip	ipas2le1nxs, x0, x1
+ 160:	d54c94c0 	tlbip	ripas2le1nxs, x0, x1
+ 164:	d54c94e0 	tlbip	ripas2le1osnxs, x0, x1
+ 168:	d54c9520 	tlbip	rvae2osnxs, x0, x1
+ 16c:	d54c95a0 	tlbip	rvale2osnxs, x0, x1
+ 170:	d54c9620 	tlbip	rvae2nxs, x0, x1
+ 174:	d54c96a0 	tlbip	rvale2nxs, x0, x1
+ 178:	d54c9720 	tlbip	vae2nxs, x0, x1
+ 17c:	d54c97a0 	tlbip	vale2nxs, x0, x1
+ 180:	d54e8120 	tlbip	vae3os, x0, x1
+ 184:	d54e81a0 	tlbip	vale3os, x0, x1
+ 188:	d54e8220 	tlbip	rvae3is, x0, x1
+ 18c:	d54e82a0 	tlbip	rvale3is, x0, x1
+ 190:	d54e8320 	tlbip	vae3is, x0, x1
+ 194:	d54e83a0 	tlbip	vale3is, x0, x1
+ 198:	d54e8520 	tlbip	rvae3os, x0, x1
+ 19c:	d54e85a0 	tlbip	rvale3os, x0, x1
+ 1a0:	d54e8620 	tlbip	rvae3, x0, x1
+ 1a4:	d54e86a0 	tlbip	rvale3, x0, x1
+ 1a8:	d54e8720 	tlbip	vae3, x0, x1
+ 1ac:	d54e87a0 	tlbip	vale3, x0, x1
+ 1b0:	d54e9120 	tlbip	vae3osnxs, x0, x1
+ 1b4:	d54e91a0 	tlbip	vale3osnxs, x0, x1
+ 1b8:	d54e9220 	tlbip	rvae3isnxs, x0, x1
+ 1bc:	d54e92a0 	tlbip	rvale3isnxs, x0, x1
+ 1c0:	d54e9320 	tlbip	vae3isnxs, x0, x1
+ 1c4:	d54e93a0 	tlbip	vale3isnxs, x0, x1
+ 1c8:	d54e9520 	tlbip	rvae3osnxs, x0, x1
+ 1cc:	d54e95a0 	tlbip	rvale3osnxs, x0, x1
+ 1d0:	d54e9620 	tlbip	rvae3nxs, x0, x1
+ 1d4:	d54e96a0 	tlbip	rvale3nxs, x0, x1
+ 1d8:	d54e9720 	tlbip	vae3nxs, x0, x1
+ 1dc:	d54e97a0 	tlbip	vale3nxs, x0, x1
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index f107eb70a67..2896a119f35 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1302,6 +1302,7 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
     case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
     case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
     case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
+    case AARCH64_OPND_SYSREG_TLBIP: sysins_ops = aarch64_sys_regs_tlbi; break;
     case AARCH64_OPND_SYSREG_SR:
 	sysins_ops = aarch64_sys_regs_sr;
 	 /* Let's remove op2 for rctx.  Refer to comments in the definition of
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index e3770b3f269..11968445550 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4686,6 +4686,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SYSREG_DC:
     case AARCH64_OPND_SYSREG_IC:
     case AARCH64_OPND_SYSREG_TLBI:
+    case AARCH64_OPND_SYSREG_TLBIP:
     case AARCH64_OPND_SYSREG_SR:
       snprintf (buf, size, "%s", style_reg (styler, opnd->sysins_op->name));
       break;
@@ -4940,152 +4941,102 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
 
 const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
 {
-    { "vmalle1",   CPENS(0,C8,C7,0), 0, AARCH64_NO_FEATURES },
-    { "vae1",      CPENS (0, C8, C7, 1), F_HASXT, AARCH64_NO_FEATURES },
-    { "aside1",    CPENS (0, C8, C7, 2), F_HASXT, AARCH64_NO_FEATURES },
-    { "vaae1",     CPENS (0, C8, C7, 3), F_HASXT, AARCH64_NO_FEATURES },
-    { "vmalle1is", CPENS(0,C8,C3,0), 0, AARCH64_NO_FEATURES },
-    { "vae1is",    CPENS (0, C8, C3, 1), F_HASXT, AARCH64_NO_FEATURES },
-    { "aside1is",  CPENS (0, C8, C3, 2), F_HASXT, AARCH64_NO_FEATURES },
-    { "vaae1is",   CPENS (0, C8, C3, 3), F_HASXT, AARCH64_NO_FEATURES },
-    { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT, AARCH64_NO_FEATURES },
-    { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT, AARCH64_NO_FEATURES },
-    { "ipas2e1",   CPENS (4, C8, C4, 1), F_HASXT, AARCH64_NO_FEATURES },
-    { "ipas2le1",  CPENS (4, C8, C4, 5), F_HASXT, AARCH64_NO_FEATURES },
-    { "vae2",      CPENS (4, C8, C7, 1), F_HASXT, AARCH64_NO_FEATURES },
-    { "vae2is",    CPENS (4, C8, C3, 1), F_HASXT, AARCH64_NO_FEATURES },
-    { "vmalls12e1",CPENS(4,C8,C7,6), 0, AARCH64_NO_FEATURES },
-    { "vmalls12e1is",CPENS(4,C8,C3,6), 0, AARCH64_NO_FEATURES },
-    { "vae3",      CPENS (6, C8, C7, 1), F_HASXT, AARCH64_NO_FEATURES },
-    { "vae3is",    CPENS (6, C8, C3, 1), F_HASXT, AARCH64_NO_FEATURES },
-    { "alle2",     CPENS(4,C8,C7,0), 0, AARCH64_NO_FEATURES },
-    { "alle2is",   CPENS(4,C8,C3,0), 0, AARCH64_NO_FEATURES },
-    { "alle1",     CPENS(4,C8,C7,4), 0, AARCH64_NO_FEATURES },
-    { "alle1is",   CPENS(4,C8,C3,4), 0, AARCH64_NO_FEATURES },
-    { "alle3",     CPENS(6,C8,C7,0), 0, AARCH64_NO_FEATURES },
-    { "alle3is",   CPENS(6,C8,C3,0), 0, AARCH64_NO_FEATURES },
-    { "vale1is",   CPENS (0, C8, C3, 5), F_HASXT, AARCH64_NO_FEATURES },
-    { "vale2is",   CPENS (4, C8, C3, 5), F_HASXT, AARCH64_NO_FEATURES },
-    { "vale3is",   CPENS (6, C8, C3, 5), F_HASXT, AARCH64_NO_FEATURES },
-    { "vaale1is",  CPENS (0, C8, C3, 7), F_HASXT, AARCH64_NO_FEATURES },
-    { "vale1",     CPENS (0, C8, C7, 5), F_HASXT, AARCH64_NO_FEATURES },
-    { "vale2",     CPENS (4, C8, C7, 5), F_HASXT, AARCH64_NO_FEATURES },
-    { "vale3",     CPENS (6, C8, C7, 5), F_HASXT, AARCH64_NO_FEATURES },
-    { "vaale1",    CPENS (0, C8, C7, 7), F_HASXT, AARCH64_NO_FEATURES },
-
-    { "vmalle1os",    CPENS (0, C8, C1, 0), F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "vae1os",       CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "aside1os",     CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "vaae1os",      CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "vale1os",      CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "vaale1os",     CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "ipas2e1os",    CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "ipas2le1os",   CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "vae2os",       CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "vale2os",      CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "vae3os",       CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "vale3os",      CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "alle2os",      CPENS (4, C8, C1, 0), F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "alle1os",      CPENS (4, C8, C1, 4), F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "alle3os",      CPENS (6, C8, C1, 0), F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-
-    { "rvae1",      CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvaae1",     CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvale1",     CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvaale1",    CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvae1is",    CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvaae1is",   CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvale1is",   CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvaale1is",  CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvae1os",    CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvaae1os",   CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvale1os",   CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvaale1os",  CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "ripas2e1",   CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "ripas2le1",  CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvae2",      CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvale2",     CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvae2is",    CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvale2is",   CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvae2os",    CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvale2os",   CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvae3",      CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvale3",     CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvae3is",    CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvale3is",   CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvae3os",    CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-    { "rvale3os",   CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_4A) },
-
     { "rpaos",      CPENS (6, C8, C4, 3), F_HASXT, AARCH64_NO_FEATURES },
     { "rpalos",     CPENS (6, C8, C4, 7), F_HASXT, AARCH64_NO_FEATURES },
     { "paallos",    CPENS (6, C8, C1, 4), 0, AARCH64_NO_FEATURES },
     { "paall",      CPENS (6, C8, C7, 4), 0, AARCH64_NO_FEATURES },
 
-    { "vae1osnxs",      CPENS (0, C9, C1, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vaae1osnxs",     CPENS (0, C9, C1, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vale1osnxs",     CPENS (0, C9, C1, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vaale1osnxs",    CPENS (0, C9, C1, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvae1isnxs",     CPENS (0, C9, C2, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvaae1isnxs",    CPENS (0, C9, C2, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvale1isnxs",    CPENS (0, C9, C2, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvaale1isnxs",   CPENS (0, C9, C2, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vae1isnxs",      CPENS (0, C9, C3, 1), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vaae1isnxs",     CPENS (0, C9, C3, 3), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vale1isnxs",     CPENS (0, C9, C3, 5), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vaale1isnxs",    CPENS (0, C9, C3, 7), F_HASXT, AARCH64_FEATURE (XS) },
-    { "rvae1osnxs",     CPENS (0, C9, C5, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvaae1osnxs",    CPENS (0, C9, C5, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvale1osnxs",    CPENS (0, C9, C5, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvaale1osnxs",   CPENS (0, C9, C5, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvae1nxs",       CPENS (0, C9, C6, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvaae1nxs",      CPENS (0, C9, C6, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvale1nxs",      CPENS (0, C9, C6, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvaale1nxs",     CPENS (0, C9, C6, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vae1nxs",        CPENS (0, C9, C7, 1), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vaae1nxs",       CPENS (0, C9, C7, 3), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vale1nxs",       CPENS (0, C9, C7, 5), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vaale1nxs",      CPENS (0, C9, C7, 7), F_HASXT, AARCH64_FEATURE (XS) },
-    { "ipas2e1isnxs",   CPENS (4, C9, C0, 1), F_HASXT, AARCH64_FEATURE (XS) },
-    { "ripas2e1isnxs",  CPENS (4, C9, C0, 2), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "ipas2le1isnxs",  CPENS (4, C9, C0, 5), F_HASXT, AARCH64_FEATURE (XS) },
-    { "ripas2le1isnxs", CPENS (4, C9, C0, 6), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vae2osnxs",      CPENS (4, C9, C1, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vale2osnxs",     CPENS (4, C9, C1, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvae2isnxs",     CPENS (4, C9, C2, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvale2isnxs",    CPENS (4, C9, C2, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vae2isnxs",      CPENS (4, C9, C3, 1), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vale2isnxs",     CPENS (4, C9, C3, 5), F_HASXT, AARCH64_FEATURE (XS) },
-    { "ipas2e1osnxs",   CPENS (4, C9, C4, 0), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "ipas2e1nxs",     CPENS (4, C9, C4, 1), F_HASXT, AARCH64_FEATURE (XS) },
-    { "ripas2e1nxs",    CPENS (4, C9, C4, 2), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "ripas2e1osnxs",  CPENS (4, C9, C4, 3), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "ipas2le1osnxs",  CPENS (4, C9, C4, 4), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "ipas2le1nxs",    CPENS (4, C9, C4, 5), F_HASXT, AARCH64_FEATURE (XS) },
-    { "ripas2le1nxs",   CPENS (4, C9, C4, 6), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "ripas2le1osnxs", CPENS (4, C9, C4, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvae2osnxs",     CPENS (4, C9, C5, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvale2osnxs",    CPENS (4, C9, C5, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvae2nxs",       CPENS (4, C9, C6, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvale2nxs",      CPENS (4, C9, C6, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vae2nxs",        CPENS (4, C9, C7, 1), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vale2nxs",       CPENS (4, C9, C7, 5), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vae3osnxs",      CPENS (6, C9, C1, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vale3osnxs",     CPENS (6, C9, C1, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvae3isnxs",     CPENS (6, C9, C2, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvale3isnxs",    CPENS (6, C9, C2, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vae3isnxs",      CPENS (6, C9, C3, 1), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vale3isnxs",     CPENS (6, C9, C3, 5), F_HASXT, AARCH64_FEATURE (XS) },
-    { "rvae3osnxs",     CPENS (6, C9, C5, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvale3osnxs",    CPENS (6, C9, C5, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvae3nxs",       CPENS (6, C9, C6, 1), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "rvale3nxs",      CPENS (6, C9, C6, 5), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (XS) },
-    { "vae3nxs",        CPENS (6, C9, C7, 1), F_HASXT, AARCH64_FEATURE (XS) },
-    { "vale3nxs",       CPENS (6, C9, C7, 5), F_HASXT, AARCH64_FEATURE (XS) },
+#define TLBI_XS_OP(OP, CODE, FLAGS) \
+    { OP, CODE, FLAGS, AARCH64_NO_FEATURES }, \
+    { OP "nxs", CODE | CPENS (0, C9, 0, 0), FLAGS | F_ARCHEXT, AARCH64_FEATURE (XS) },
+
+    TLBI_XS_OP ( "vmalle1",   CPENS (0, C8, C7, 0), 0)
+    TLBI_XS_OP ( "vae1",      CPENS (0, C8, C7, 1), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "aside1",    CPENS (0, C8, C7, 2), F_HASXT )
+    TLBI_XS_OP ( "vaae1",     CPENS (0, C8, C7, 3), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vmalle1is", CPENS (0, C8, C3, 0), 0)
+    TLBI_XS_OP ( "vae1is",    CPENS (0, C8, C3, 1), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "aside1is",  CPENS (0, C8, C3, 2), F_HASXT )
+    TLBI_XS_OP ( "vaae1is",   CPENS (0, C8, C3, 3), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "ipas2e1",   CPENS (4, C8, C4, 1), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "ipas2le1",  CPENS (4, C8, C4, 5), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vae2",      CPENS (4, C8, C7, 1), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vae2is",    CPENS (4, C8, C3, 1), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vmalls12e1",CPENS (4, C8, C7, 6), 0)
+    TLBI_XS_OP ( "vmalls12e1is",CPENS(4,C8, C3, 6), 0)
+    TLBI_XS_OP ( "vae3",      CPENS (6, C8, C7, 1), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vae3is",    CPENS (6, C8, C3, 1), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "alle2",     CPENS (4, C8, C7, 0), 0)
+    TLBI_XS_OP ( "alle2is",   CPENS (4, C8, C3, 0), 0)
+    TLBI_XS_OP ( "alle1",     CPENS (4, C8, C7, 4), 0)
+    TLBI_XS_OP ( "alle1is",   CPENS (4, C8, C3, 4), 0)
+    TLBI_XS_OP ( "alle3",     CPENS (6, C8, C7, 0), 0)
+    TLBI_XS_OP ( "alle3is",   CPENS (6, C8, C3, 0), 0)
+    TLBI_XS_OP ( "vale1is",   CPENS (0, C8, C3, 5), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vale2is",   CPENS (4, C8, C3, 5), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vale3is",   CPENS (6, C8, C3, 5), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vaale1is",  CPENS (0, C8, C3, 7), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vale1",     CPENS (0, C8, C7, 5), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vale2",     CPENS (4, C8, C7, 5), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vale3",     CPENS (6, C8, C7, 5), F_HASXT | F_REG_128)
+    TLBI_XS_OP ( "vaale1",    CPENS (0, C8, C7, 7), F_HASXT | F_REG_128)
+
+#undef TLBI_XS_OP
+#define TLBI_XS_OP(OP, CODE, FLAGS) \
+    { OP, CODE, FLAGS | F_ARCHEXT, AARCH64_FEATURE (V8_4A) }, \
+    { OP "nxs", CODE | CPENS (0, C9, 0, 0), FLAGS | F_ARCHEXT, AARCH64_FEATURE (XS) },
+
+    TLBI_XS_OP ( "vmalle1os",    CPENS (0, C8, C1, 0), 0 )
+    TLBI_XS_OP ( "vae1os",       CPENS (0, C8, C1, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "aside1os",     CPENS (0, C8, C1, 2), F_HASXT )
+    TLBI_XS_OP ( "vaae1os",      CPENS (0, C8, C1, 3), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "vale1os",      CPENS (0, C8, C1, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "vaale1os",     CPENS (0, C8, C1, 7), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "ipas2e1os",    CPENS (4, C8, C4, 0), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "ipas2le1os",   CPENS (4, C8, C4, 4), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "vae2os",       CPENS (4, C8, C1, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "vale2os",      CPENS (4, C8, C1, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "vmalls12e1os", CPENS (4, C8, C1, 6), 0 )
+    TLBI_XS_OP ( "vae3os",       CPENS (6, C8, C1, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "vale3os",      CPENS (6, C8, C1, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "alle2os",      CPENS (4, C8, C1, 0), 0 )
+    TLBI_XS_OP ( "alle1os",      CPENS (4, C8, C1, 4), 0 )
+    TLBI_XS_OP ( "alle3os",      CPENS (6, C8, C1, 0), 0 )
+
+    TLBI_XS_OP ( "rvae1",      CPENS (0, C8, C6, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvaae1",     CPENS (0, C8, C6, 3), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvale1",     CPENS (0, C8, C6, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvaale1",    CPENS (0, C8, C6, 7), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvae1is",    CPENS (0, C8, C2, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvaae1is",   CPENS (0, C8, C2, 3), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvale1is",   CPENS (0, C8, C2, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvaale1is",  CPENS (0, C8, C2, 7), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvae1os",    CPENS (0, C8, C5, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvaae1os",   CPENS (0, C8, C5, 3), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvale1os",   CPENS (0, C8, C5, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvaale1os",  CPENS (0, C8, C5, 7), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "ripas2e1",   CPENS (4, C8, C4, 2), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "ripas2le1",  CPENS (4, C8, C4, 6), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvae2",      CPENS (4, C8, C6, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvale2",     CPENS (4, C8, C6, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvae2is",    CPENS (4, C8, C2, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvale2is",   CPENS (4, C8, C2, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvae2os",    CPENS (4, C8, C5, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvale2os",   CPENS (4, C8, C5, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvae3",      CPENS (6, C8, C6, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvale3",     CPENS (6, C8, C6, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvae3is",    CPENS (6, C8, C2, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvale3is",   CPENS (6, C8, C2, 5), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvae3os",    CPENS (6, C8, C5, 1), F_HASXT | F_REG_128 )
+    TLBI_XS_OP ( "rvale3os",   CPENS (6, C8, C5, 5), F_HASXT | F_REG_128 )
+
+#undef TLBI_XS_OP
 
     { 0,       CPENS(0,0,0,0), 0, AARCH64_NO_FEATURES }
 };