diff options
| author | Krishna Manikandan <mkrishn@codeaurora.org> | 2021-04-06 11:31:34 +0530 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-04-07 11:05:48 -0700 |
| commit | 7e4526db30c28d1f89c5b168cd7c565fcb4108de (patch) | |
| tree | 02a7207f5de6f75562c0a49d191ed1e8a5869fcd /drivers/gpu/drm/msm/disp/dpu1 | |
| parent | a8eca8a1a524b96a49a8f7f172bfc9a8f4320e40 (diff) | |
drm/msm/disp/dpu1: add vsync and underrun irqs for INTF_5
INTF_5 is used by EDP panel in SC7280 target. Add vsync
and underrun irqs needed by INTF_5 to dpu irq map.
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1617688895-26275-3-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 49c769550749..90f9dc35f079 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -72,10 +72,12 @@ #define DPU_INTR_INTF_1_UNDERRUN BIT(26) #define DPU_INTR_INTF_2_UNDERRUN BIT(28) #define DPU_INTR_INTF_3_UNDERRUN BIT(30) +#define DPU_INTR_INTF_5_UNDERRUN BIT(22) #define DPU_INTR_INTF_0_VSYNC BIT(25) #define DPU_INTR_INTF_1_VSYNC BIT(27) #define DPU_INTR_INTF_2_VSYNC BIT(29) #define DPU_INTR_INTF_3_VSYNC BIT(31) +#define DPU_INTR_INTF_5_VSYNC BIT(23) /** * Pingpong Secondary interrupt status bit definitions @@ -326,7 +328,10 @@ static const struct dpu_irq_type dpu_irq_map[] = { { DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0}, { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0}, { DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0}, - /* irq_idx:32-63 */ + /* irq_idx:32-33 */ + { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0}, + { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0}, + /* irq_idx:34-63 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, |