diff options
| author | Amit Pundir <amit.pundir@linaro.org> | 2019-06-10 12:15:23 +0530 |
|---|---|---|
| committer | Sumit Semwal <sumit.semwal@linaro.org> | 2020-02-21 15:26:19 +0530 |
| commit | dd2eb40d2f89eed64db36fc123518328230c08e7 (patch) | |
| tree | a0c119d0d1df9b105accac2c9a86cd61426098b7 /arch/arm64 | |
| parent | abf8aa53b4a575be82651eda3341873a3c387a37 (diff) | |
blueline: arm64: dts: qcom: Reserve gpio ranges
GPIOs 0 through 3 and 81 through 84 are configured to not be accessible
from the application CPUs. Mark them as reserved to allow the Pixel 3
to boot.
[AmitP: Ref 9134586715e3 arm64: dts: qcom: msm8998: Reserve gpio ranges on MTP")]
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845-blueline.dts | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-blueline.dts index f91119d31349..8770bc302640 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-blueline.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-blueline.dts @@ -383,6 +383,8 @@ }; &tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + pcie0_pwren_state: pcie0-pwren { pins = "gpio90"; function = "gpio"; |