diff options
| author | John Stultz <john.stultz@linaro.org> | 2019-07-30 21:35:11 +0530 |
|---|---|---|
| committer | Sumit Semwal <sumit.semwal@linaro.org> | 2020-02-21 15:26:19 +0530 |
| commit | 0f2dfbf5a10184568623d9c11e1d845e8dd6691d (patch) | |
| tree | fc49deacdf6a9a38681090b8b427496be8b13a7c /arch/arm64/boot | |
| parent | ec5525f71bffc2af35057a3b4cd1abcbb39e2796 (diff) | |
dts: qcom: sdm845: Add suspend/active pinmux bits for DSI
Some DSI panels need the suspend/active pinmux bits; add them.
These were needed for atleast Pixel 3 and Poco F1 devices.
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845.dtsi | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cfdcfefe90b5..97d078ec6012 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2052,6 +2052,58 @@ function = "qup15"; }; }; + + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio6", "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio52"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio6", "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio52"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_active: sde_te_active { + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; mss_pil: remoteproc@4080000 { |