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2018-04-18swr/rast: Optimize late/bindless JIT of samplersGeorge Kyriazis
Add per-worker thread private data to all shader calls Add per-worker sampler cache and jit context Add late LoadTexel JIT support Add per-worker-thread Sampler / LoadTexel JIT Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Implement VROUND intrinsic in x86 lowering passGeorge Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Refactor to improve code sharing.George Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: minimize codegen redundant workGeorge Kyriazis
Move filtering of redundant codegen operations into gen scripts themselves Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: double-pump in x86 lowering passGeorge Kyriazis
Add support for double-pumping a smaller SIMD width intrinsic. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Fix 64bit float loads in x86 lowering passGeorge Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add shader stats infrastructure (WIP)George Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Type-check TemplateArgUnrollerGeorge Kyriazis
Allows direct use of enum values in conversion to template args. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add vgather to x86 lowering pass.George Kyriazis
Add support for generic VGATHERPD intrinsic in x86 lowering pass. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: fix commentGeorge Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: add cvt instructions in x86 lowering passGeorge Kyriazis
Support generic VCVTPD2PS and VCVTPH2PS in x86 lowering pass. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Fix alloca usage in jitterGeorge Kyriazis
Fix issue where temporary allocas were getting hoisted to function entry unnecessarily. We now explicitly mark temporary allocas and skip hoisting during the hoist pass. Shuold reduce stack usage. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Change gfx pointers to gfxptr_tGeorge Kyriazis
Changing type to gfxptr for indices and related changes to fetch and mem builder code. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Fix byte offset for non-indexed drawsGeorge Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add support for setting optimization levelGeorge Kyriazis
for JIT compilation Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Adding translate call to builder_gfx_mem.George Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Fix codegen for typedef typesGeorge Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr: add x86 lowering pass to fragment shaderGeorge Kyriazis
Needed because some FP paths (namely stipple) use gather intrinsics that now need to be lowered to x86. v2: fix typo in commit message Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Enable generalized fetch jitGeorge Kyriazis
Enable generalized fetch jit with 8 or 16 wide SIMD target. Still some work needed to remove some simd8 double pumping for 16-wide target. Also removed unused non-gather load vertices path. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add builder_gfx_mem.{h|cpp}George Kyriazis
Abstract usage scenarios for memory accesses into builder_gfx_mem. Builder_gfx_mem will convert gfxptr_t from 64-bit int to regular pointer types for use by builder_mem. v2: reworded commit message; renamed enum more appropriately Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Lower VGATHERPS and VGATHERPS_16 to x86.George Kyriazis
Some more work to do before we can support simultaneous 8-wide and 16-wide and remove the VGATHERPS_16 version. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Cleanup of JitManager convenience typesGeorge Kyriazis
Small cleanup. Remove convenience types from JitManager and standardize on the Builder's convenience types. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Lower PERMD and PERMPS to x86.George Kyriazis
Add support for providing an emulation callback function for arch/width combinations that don't map cleanly to an x86 intrinsic. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Start refactoring of builder/packetizer.George Kyriazis
Move x86 intrinsic lowering to a separate pass. Builder now instantiates generic intrinsics for features not supported by llvm. The separate x86 lowering pass is responsible for lowering to valid x86 for the target SIMD architecture. Currently it's a port of existing code to get it up and running quickly. Will eventually support optimized x86 for AVX, AVX2 and AVX512. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Simplify #define usage in gen source fileGeorge Kyriazis
Removed preprocessor defines from structures passed to LLVM jitted code. The python scripts do not understand the preprocessor defines and ignores them. So for fields that are compiled out due to a preprocessor define the LLVM script accounts for them anyway because it doesn't know what the defines are set to. The sanitize defines for open source are fine in that they're safely used. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Move CallPrint() to a separate fileGeorge Kyriazis
Needed work for jit code debug. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Fix name mangling for LLVM pow intrinsicGeorge Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add some archrast countersGeorge Kyriazis
Hook up archrast counters for shader stats: instructions executed. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Code cleanupGeorge Kyriazis
Removing some code that doesn't seem to do anything meaningful. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add "Num Instructions Executed" stats intrinsic.George Kyriazis
Added a SWR_SHADER_STATS structure which is passed to each shader. The stats pass will instrument the shader to populate this. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add MEM_ADD helper function to Builder.George Kyriazis
mem[offset] += value This function will be heavily used by all stats intrinsics. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Permute work for simd16George Kyriazis
Fix slow permutes in PA tri lists under SIMD16 emulation on AVX Added missing permute (interlane, immediate) to SIMDLIB Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: WIP builder rewrite (2)George Kyriazis
Finish up the remaining explicit intrinsic uses. At this point all explicit Intrinsic::getDeclaration() usage has been replaced with auto generated macros generated with gen_llvm_ir_macros.py. Going forward, make sure to only use the intrinsics here, adding new ones as needed. Next step is to remove all references to x86 intrinsics to keep the builder target-independent. Any x86 lowering will be handled by a separate pass. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add autogen of helper llvm intrinsics.George Kyriazis
Replace sqrt, maskload, fp min/max, cttz, ctlz with llvm equivalent. Replace AVX maskedstore intrinsic with LLVM intrinsic. Add helper llvm macros for stacksave, stackrestore, popcnt. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: WIP builder rewrite.George Kyriazis
Start removing avx2 macros for functionality that exists in llvm. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: LLVM 6 fixGeorge Kyriazis
for getting masked gather intrinsic (also compatible with LLVM 4) Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Changes to allow jitter to compile with LLVM5George Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add some archrast statsGeorge Kyriazis
Add stats for degenerate and backfacing primitive counts Wire archrast stats for alpha blend and alpha test. pass value to jitter, upon return have archrast event increment a value Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Silence some unused variable warningsGeorge Kyriazis
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add debug type info for i128George Kyriazis
Help support debug info in 16 wide shaders. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Use blend context struct to pass paramsGeorge Kyriazis
Stuff parameters into a blend context struct before passing down through the PFN_BLEND_JIT_FUNC function pointer. Needed for stat changes. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Introduce JIT_MEM_CLIENTGeorge Kyriazis
Add assert for correct usage of memory accesses v2: reworded commit message; renamed enum more appropriately Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-18swr/rast: Add some instructions to jitterGeorge Kyriazis
VPHADDD, PMAXUD, PMINUD Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-04-17meson: Version libMesaOpenCL like autotools doesJan Alexander Steffens (heftig)
This is for parity with autotools. It names the library libMesaOpenCL.so.1.0.0 and points mesa.icd to the .1 symlink. opencl_version now matches configure.ac's OPENCL_VERSION. Signed-off-by: Jan Alexander Steffens (heftig) <jan.steffens@gmail.com> Tested-By: Aaron Watry <awatry@gmail.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-04-17meson: Add library versions to swr driversJan Alexander Steffens (heftig)
This is for parity with autotools. Signed-off-by: Jan Alexander Steffens (heftig) <jan.steffens@gmail.com> Acked-by: Dylan Baker <dylan@pnwbakers.com>
2018-04-17radv: fix scissor computation when using half-pixel viewport offsetSamuel Pitoiset
'scale[i]' can be non-integer. Original patch by Philip Rebohle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106074 Fixes: 0f3de89a56a ("radv: Use the guard band.") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Niuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-17spirv: Accept doubles in FaceForward, Reflect and RefractNeil Roberts
The SPIR-V spec doesn’t specify a size requirement for these and the equivalent functions in the GLSL spec have explicit alternatives for doubles. Refract is a little bit more complicated due to the fact that the final argument is always supposed to be a scalar 32- or 16- bit float regardless of the other operands. However in practice it seems there is a bug in glslang that makes it convert the argument to 64-bit if you actually try to pass it a 32-bit value while the other arguments are 64-bit. This adds an optional conversion of the final argument in order to support any type. These have been tested against the automatically generated tests of glsl-4.00/execution/built-in-functions using the ARB_gl_spirv branch which tests it with quite a large range of combinations. The issue with glslang has been filed here: https://github.com/KhronosGroup/glslang/issues/1279 v2: Convert the eta operand of Refract from any size in order to make it eventually cope with 16-bit floats. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-17spirv: Add a 64-bit implementation of OpIsInfNeil Roberts
The only change neccessary is to change the type of the constant used to compare against. This has been tested against the arb_gpu_shader_fp64/execution/ fs-isinf-dvec tests using the ARB_gl_spirv branch. v2: Use nir_imm_floatN_t for the constant. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-17spirv: Use nir_imm_floatN_t for constants for GLSL450 builtinsNeil Roberts
There is an existing macro that is used to choose between either a float or a double immediate constant based on the bit size of the first operand to the builtin. This is now changed to use the new nir_imm_floatN_t helper function to reduce the number of places that make this decision. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-17nir/builder: Add a nir_imm_floatN_t helperNeil Roberts
This lets you easily build float immediates just given the bit size. If we have this single place here to handle this then it will be easier to add support for 16-bit floats later. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>