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2018-04-12vl: add VP9 profile2 supportLeo Liu
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12vl: add VP9 picture descriptionLeo Liu
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12vl: add VP9 profile0 and formatLeo Liu
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-03-26gallium: Correct minor typo in header commentsAlyssa Rosenzweig
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-03-23tgsi: convert opcode macros to enumsBrian Paul
Enums are nicer in gdb. Reviewed-by: Eric Anholt <eric@anholt.net>
2018-03-20gallium: add packed uniform CAPTimothy Arceri
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-03-06gallium: increase PIPE_MAX_SHADER_SAMPLER_VIEWS to 128Roland Scheidegger
Some state trackers require 128. (There are no plans to increase PIPE_MAX_SAMPLERS too, since with gl state tracker it's unlikely more than 32 will be needed, if you need more use bindless.)
2018-03-01gallium: remove llvm from ir structTimothy Arceri
This was added in 425dc4c4b366 but never used. Also since 100796c15c3a native has superseded llvm. Acked-by: Dave Airlie <airlied@redhat.com>
2018-02-17gallium: allow drivers to impose BO flags restrictions on constant buffer 0Marek Olšák
Required by radeonsi for optimal behavior.
2018-02-14gallium: drop all the guard band float caps.Dave Airlie
Nobody queries these and nobody sets them to anything useful, the docs say TODO. Drop them until a use appears. Reviewed-by: Roland Scheidegger <sroland@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-02-05vl: add parameters for HEVC encodeBoyuan Zhang
Add HEVC encode interface Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-02-02gallium: Add a new A4B4G4R4 pipe format for Broadcom.Eric Anholt
The VC5 HW puts A in the low bits and R in the high bits. We can't just swizzle in the shaders because the blending HW can't pick what channel A is in, so make a new format to match it. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-02-01gallium/st/clover: remove unused PIPE_SHADER_IR_LLVMTimothy Arceri
This has been unused since 100796c15c3a. Acked-by: Marek Olšák <marek.olsak@amd.com>
2018-01-30gallium: add fence_server_signal() v2Andres Rodriguez
Calling this function will emit a fence signal operation into the GPU's command stream. v2: documentation typos Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-30gallium: introduce PIPE_FD_TYPE_SYNCOBJAndres Rodriguez
Denotes that a fd is backed by a synobj. For example, radv shared semaphores. Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-30gallium: introduce PIPE_CAP_FENCE_SIGNAL v2Andres Rodriguez
Protects semaphore signaling functionality required by GL_EXT_semaphore. v2: s/semaphore/fence Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-30gallium: add type parameter to create_fence_fdAndres Rodriguez
An fd can potentially have different types of objects backing it. Specifying the type helps us make sure we treat the FD correctly. This is in preparation to allow importing syncobj fence FDs in addition to native sync FDs. Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-19gallium: Make (num_)samples an unsigned intGert Wollny
According to the ARB_multisample num_samples is a non-negative integer. Consequently define it as such, fail in glx/choose_visual if a negative number is given. v2: split patch into gallium and mesa part Signed-off-by: Gert Wollny <gw.fossdev@gmail.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-17gallium: remove PIPE_CAP_USER_CONSTANT_BUFFERSMarek Olšák
Reviewed-by: Roland Scheidegger <sroland@vmware.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-01-17gallium: remove PIPE_CAP_TEXTURE_SHADOW_MAPMarek Olšák
Reviewed-by: Roland Scheidegger <sroland@vmware.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-01-17gallium: remove PIPE_CAP_TWO_SIDED_STENCILMarek Olšák
Reviewed-by: Roland Scheidegger <sroland@vmware.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-12-19gallium: plumb context priority through to driverRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Andres Rodriguez <andresx7@gmail.com> Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-12-15vl: remove is idr flagBoyuan Zhang
Remove is_idr flag since not being used anymore. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2017-12-15gallium/util: add u_transfer_helperRob Clark
Add a new helper that drivers can use to emulate various things that need special handling in particular in transfer_map: 1) z32_s8x24.. gl/gallium treats this as a single buffer with depth and stencil interleaved but hardware frequently treats this as separate z32 and s8 buffers. Special pack/unpack handling is needed in transfer_map/unmap to pack/unpack the exposed buffer 2) fake RGTC.. GPUs designed with GLES in mind, but which can other- wise do GL3, if native RGTC is not supported it can be emulated by converting to uncompressed internally, but needs pack/unpack in transfer_map/unmap 3) MSAA resolves in the transfer_map() case v2: add MSAA resolve based on Eric's "gallium: Add helpers for MSAA resolves in pipe_transfer_map()/unmap()." patch; avoid wrapping pipe_resource, to make it possible for drivers to use both this and threaded_context. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-11-30mesa: add AllowGLSLCrossStageInterpolationMismatch workaroundTapani Pälli
This fixes issues seen with certain versions of Unreal Engine 4 editor and games built with that using GLSL 4.30. v2: add driinfo_gallium change (Emil Velikov) Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97852 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103801 Acked-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-17vl: add poc typeBoyuan Zhang
Different from vce encoding, vcn encoding requires driver side to encode bitstream header, such as pps, sps and slice header. pic_order_cnt_type is a required variable when encoding both sps and slice header, therefore we need to add this new variable here, and hold the value passed from st, e.g. vaapi interface Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2017-11-11st/dri: fix deadlock when waiting on android fencesMarek Olšák
Android fences can't be deferred, because st/dri calls fence_finish with ctx = NULL, so the driver can't flush u_threaded_context. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-10st/dri: fix android fence regressionMarek Olšák
Fixes piglit - egl_khr_fence_sync/android_native tests. Broken by 884a0b2a9e55d4c1ca39475b50d9af598d7d7280. Introduce state-tracker flush flags, analogous to the pipe ones. Use the former when with stapi->flush(). Fixes: 884a0b2a9e5 ("st/dri: use stapi flush instead of pipe flush when creating fences") Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-10gallium: add hw atomic buffer binding API.Dave Airlie
This API binds atomic buffers for all bound shaders (as per the GL semantics). This is needed to support cross shader hw atomic counters. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Tested-By: Gert Wollny <gw.fossdev@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10gallium/tgsi: start adding hw atomics (v3.2)Dave Airlie
This adds support for a hw atomic counters to TGSI. A new register file for storing atomic counters is added, along with a new atomic counter semantic, along with docs for both. v2: drop semantic, move hw counter to backend, Ilia pointed out SSO would have busted my plan, and he was right. v3: drop BUFFER decls. (Marek) v3.1: minor fixups for whitespace, set ureg error if we overflow the hw atomic limits. (nha) v3.2: fix some docs inconsistencies (Ilia) Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Tested-By: Gert Wollny <gw.fossdev@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-10gallium: add CAPs to support HW atomic counters. (v3)Dave Airlie
This looks like an evergreen specific feature, but with atomic counters AMD have hw specific counters they use instead of operating on buffers directly. These are separate to the buffer atomics, so require different limits and code paths. I've left the CAP for atomic type extensible in case someone else has a variant on this sort of thing (freedreno maybe?) and needs to change it. This adds all the CAPs required to add support for those atomic counters, along with a related CAP for limiting the number of output resources. I'd like to land this and the st patch then I can start to upstream the evergreen support for these and other GL4.x features. v2: drop the ATOMIC_COUNTER_MODE cap, just use the return from the HW counters. If 0 we use the current mode. v3: fix some rebase errors (Gert Wollny) Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Tested-By: Gert Wollny <gw.fossdev@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-09gallium: add pipe_context::callbackNicolai Hähnle
For running post-draw operations inside the driver thread. ddebug will use it. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09gallium: add PIPE_FLUSH_{TOP,BOTTOM}_OF_PIPE bitsNicolai Hähnle
These bits are intended to be used by the ddebug hang detection and are named in analogy to the Vulkan stage bits (and the corresponding Radeon pipeline event). Hang detection needs fences on the granularity of individual commands, which nothing else really covers. The closest alternative would have been PIPE_QUERY_GPU_FINISHED, but (a) queries are a per-context object and we really want a per-screen object, (b) queries don't offer a wait with timeout, and (c) in any case, PIPE_QUERY_GPU_FINISHED is meant to imply that GPU caches are flushed, which the new bits explicitly aren't. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09gallium: add PIPE_FLUSH_ASYNC and PIPE_FLUSH_HINT_FINISHNicolai Hähnle
Also document some subtleties of pipe_context::flush. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-09gallium: clarify the constraints on sampler_view_destroyNicolai Hähnle
r600 expects the context that created the sampler view to still be alive (there is a per-context list of sampler views). svga currently bails when the context of destruction is not the same as creation. The GL state tracker, which is the only one that runs into the multi-context subtleties (due to share groups), already guarantees that sampler views are destroyed before their context of creation is destroyed. Most drivers are context-agnostic, so the warning message in pipe_sampler_view_release doesn't really make sense. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-06gallium: Wire up flush controlAdam Jackson
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Adam Jackson <ajax@redhat.com>
2017-11-06gallium: add PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSETMarek Olšák
2017-11-01gallium: increase pipe_sampler_view::target bitfield size for MSVCBrian Paul
MSVC treats enums as being signed. The 4-bit target field isn't large enough to correctly store the value 8 (for PIPE_TEXTURE_CUBE_ARRAY). The bitfield value 0x8 was being interpreted as -8 so matching the target with PIPE_TEXTURE_CUBE_ARRAY in switch statements, etc. was failing. To keep the structure size the same, we reduce the format field from 16 bits to 15. There don't appear to be any other enum bitfields which need to be adjusted. This fixes a number of Piglit cube map array tests. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-11-01gallium: add cap for driver specified max combined shader resources.Dave Airlie
Some hw (evergreen) has a limit on how many combined (images/buffers/mrts) a fragment shader can access. Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-12gallium: add pipe_screen::check_resource_capabilityMarek Olšák
This is optional (and no CAP). Implemented by radeonsi, ddebug, rbug, trace. Reviewed-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-10gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.Eric Anholt
Because vc4 can control the order that tiles are rasterized in, we can use it to implement overlapping blits using normal drawing and GL_ARB_texture_barrier, as long as we can tell the kernel what order to render the tiles in. This commit introduces the core gallium support, vc4 changes will follow. v2: Fix on the simulator. v3: Add the cap (disabled) to other drivers, add rst docs for the cap. v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS v5: Drop vc4 changes from this commit, for clarity. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)
2017-10-10gallium: Add support for 5551 with the 1-bit field in the low bit.Eric Anholt
This is how VC4 stores 5551 textures, which we need to support for GL_OES_required_internalformat. v2: Extend commit message, fix svga driver build, add BE ordering from Roland. v3: Rebase on PIPE_FORMAT_R10G10B10X2_UNORM addition. Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2) Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v2)
2017-10-10st_api: remove unused get_resource_for_egl_imageNicolai Hähnle
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-10-06gallium: add PIPE_CAP_TGSI_ANY_REG_AS_ADDRESSMarek Olšák
Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-02mesa: Remove force_s3tc_enable driconf variableMatt Turner
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-02gallium: add PIPE_FORMAT_R10G10B10X2_UNORMNicolai Hähnle
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-30gallium: add new LOD opcodeRoland Scheidegger
The operation performed is all the same as LODQ, but with the usual differences between dx10 and GL texture opcodes, that is separate resource and sampler indices (plus result swizzling, and setting z/w channels to zero). Reviewed-by: Jose Fonseca <jfonseca@vmware.com> Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-29gallium: add LDEXP TGSI instruction and corresponding capNicolai Hähnle
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-09-21gallium: Add PIPE_SHADER_CAP_INT64_ATOMICSJan Vesely
Denotes availability of 64bit int atomic instructions Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-18gallium: Add PIPE_SHADER_CAP_FP16Jan Vesely
Denotes native half precision float operations capability v2: PIPE_CAP_HALFS -> PIPE_SHADER_CAP_FP16 fix indentation Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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