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AgeCommit message (Expand)Author
2014-05-23Add enable mmu platform porting interfacesDan Handley
2014-05-23Rename FVP specific files and functionsDan Handley
2014-05-23Move BL porting functions into platform.hDan Handley
2014-05-23Split platform.h into separate headersDan Handley
2014-05-23Remove unused data declarationsDan Handley
2014-05-23Remove extern keyword from function declarationsDan Handley
2014-05-23Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2Andrew Thoelke
2014-05-23doc: Update information about the memory layoutSandrine Bailleux
2014-05-23Make the memory layout more flexibleSandrine Bailleux
2014-05-23Make BL1 RO and RW base addresses configurableSandrine Bailleux
2014-05-23Merge pull request #104 from athoelke:at/tsp-entrypoints-v2Andrew Thoelke
2014-05-23Merge pull request #105 from athoelke:sm/support_normal_irq_in_tsp-v2Andrew Thoelke
2014-05-23Merge pull request #102 from achingupta:ag/tf-issues#104-v2Andrew Thoelke
2014-05-23Merge pull request #100 from jcastillo-arm:jc/tf-issues/149-v4Andrew Thoelke
2014-05-23Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2Andrew Thoelke
2014-05-23Merge pull request #103 from athoelke:dh/tf-issues#68-v3Andrew Thoelke
2014-05-23Merge pull request #99 from vikramkanigiri:vk/tf-issues-133_V3Andrew Thoelke
2014-05-23Merge pull request #67 from achingupta:ag/psci_standby_bug_fixAndrew Thoelke
2014-05-23Limit BL3-1 read/write access to SRAMAndrew Thoelke
2014-05-23Use a vector table for TSP entrypointsAndrew Thoelke
2014-05-23Non-Secure Interrupt support during Standard SMC processing in TSPSoby Mathew
2014-05-22Allow BL3-2 platform definitions to be optionalDan Handley
2014-05-22Enable secure timer to generate S-EL1 interruptsAchin Gupta
2014-05-22Add S-EL1 interrupt handling support in the TSPDAchin Gupta
2014-05-22Add support for asynchronous FIQ handling in TSPAchin Gupta
2014-05-22Add support for synchronous FIQ handling in TSPAchin Gupta
2014-05-22Use secure timer to generate S-EL1 interruptsAchin Gupta
2014-05-22Introduce interrupt handling framework in BL3-1Achin Gupta
2014-05-22Introduce platform api to access an ARM GICAchin Gupta
2014-05-22Introduce interrupt registration framework in BL3-1Achin Gupta
2014-05-22Add context library API to change a bit in SCR_EL3Achin Gupta
2014-05-22Rework 'state' field usage in per-cpu TSP contextAchin Gupta
2014-05-22Doc: Add the "Building the Test Secure Payload" sectionSandrine Bailleux
2014-05-22fvp: Move TSP from Secure DRAM to Secure SRAMSandrine Bailleux
2014-05-22TSP: Let the platform decide which secure memory to useSandrine Bailleux
2014-05-22Reserve some DDR DRAM for secure use on FVP platformsJuan Castillo
2014-05-22Add support for BL3-1 as a reset vectorVikram Kanigiri
2014-05-22Rework memory information passing to BL3-x imagesVikram Kanigiri
2014-05-22Populate BL31 input parameters as per new specVikram Kanigiri
2014-05-22Rework handover interface between BL stagesVikram Kanigiri
2014-05-22Introduce macros to manipulate the SPSRVikram Kanigiri
2014-05-22Merge pull request #91 from linmaonly/lin_devAndrew Thoelke
2014-05-22Merge pull request #83 from athoelke/at/tf-issues-126Andrew Thoelke
2014-05-22Merge pull request #85 from hliebel/hl/bl30-docAndrew Thoelke
2014-05-20Address issue 156: 64-bit addresses get truncatedLin Ma
2014-05-19Improve BL3-0 documentationHarry Liebel
2014-05-19Merge pull request #78 from jeenuv:tf-issues-148Andrew Thoelke
2014-05-16Add build configuration for timer save/restoreJeenu Viswambharan
2014-05-16Document summary of build options in user guideJeenu Viswambharan
2014-05-16Reorganize build optionsJeenu Viswambharan
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