diff options
author | Dan Handley <dan.handley@arm.com> | 2014-04-09 12:48:25 +0100 |
---|---|---|
committer | Dan Handley <dan.handley@arm.com> | 2014-05-06 12:35:02 +0100 |
commit | 4ecca33988b90de43ec4f4a929094a38a23fda31 (patch) | |
tree | ad1fa01314b562bfbdac77a39451ef7967c0ff03 /drivers | |
parent | b495bdef190acf166c713e138b61c5bb25402fc0 (diff) |
Move include and source files to logical locations
Move almost all system include files to a logical sub-directory
under ./include. The only remaining system include directories
not under ./include are specific to the platform. Move the
corresponding source files to match the include directory
structure.
Also remove pm.h as it is no longer used.
Change-Id: Ie5ea6368ec5fad459f3e8a802ad129135527f0b3
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/arm/cci400/cci400.c (renamed from drivers/arm/interconnect/cci-400/cci400.c) | 6 | ||||
-rw-r--r-- | drivers/arm/gic/aarch64/gic_v3_sysregs.S (renamed from drivers/console/console.h) | 62 | ||||
-rw-r--r-- | drivers/arm/gic/gic_v2.c | 298 | ||||
-rw-r--r-- | drivers/arm/gic/gic_v3.c (renamed from drivers/io/io_memmap.h) | 55 | ||||
-rw-r--r-- | drivers/arm/interconnect/cci-400/cci400.h | 72 | ||||
-rw-r--r-- | drivers/arm/interconnect/tzc-400/tzc400.h | 211 | ||||
-rw-r--r-- | drivers/arm/peripherals/pl011/pl011.h | 161 | ||||
-rw-r--r-- | drivers/arm/pl011/pl011.c (renamed from drivers/arm/peripherals/pl011/pl011.c) | 0 | ||||
-rw-r--r-- | drivers/arm/pl011/pl011_console.c (renamed from drivers/arm/peripherals/pl011/pl011_console.c) | 0 | ||||
-rw-r--r-- | drivers/arm/tzc400/tzc400.c (renamed from drivers/arm/interconnect/tzc-400/tzc400.c) | 0 | ||||
-rw-r--r-- | drivers/io/io_driver.h | 93 | ||||
-rw-r--r-- | drivers/io/io_fip.h | 36 | ||||
-rw-r--r-- | drivers/io/io_semihosting.h | 36 | ||||
-rw-r--r-- | drivers/power/fvp_pwrc.h | 77 |
14 files changed, 409 insertions, 698 deletions
diff --git a/drivers/arm/interconnect/cci-400/cci400.c b/drivers/arm/cci400/cci400.c index cd5446fa..4ca55b18 100644 --- a/drivers/arm/interconnect/cci-400/cci400.c +++ b/drivers/arm/cci400/cci400.c @@ -44,7 +44,8 @@ void cci_enable_coherency(unsigned long mpidr) DVM_EN_BIT | SNOOP_EN_BIT); /* Wait for the dust to settle down */ - while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT); + while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT) + ; } void cci_disable_coherency(unsigned long mpidr) @@ -54,6 +55,7 @@ void cci_disable_coherency(unsigned long mpidr) ~(DVM_EN_BIT | SNOOP_EN_BIT)); /* Wait for the dust to settle down */ - while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT); + while (mmio_read_32(CCI400_BASE + STATUS_REG) & CHANGE_PENDING_BIT) + ; } diff --git a/drivers/console/console.h b/drivers/arm/gic/aarch64/gic_v3_sysregs.S index e2859092..2a96da76 100644 --- a/drivers/console/console.h +++ b/drivers/arm/gic/aarch64/gic_v3_sysregs.S @@ -28,12 +28,62 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CONSOLE_H__ -#define __CONSOLE_H__ +#include <asm_macros.S> -void console_init(unsigned long base_addr); -int console_putc(int c); -int console_getc(void); + .globl read_icc_sre_el1 + .globl read_icc_sre_el2 + .globl read_icc_sre_el3 + .globl write_icc_sre_el1 + .globl write_icc_sre_el2 + .globl write_icc_sre_el3 + .globl write_icc_pmr_el1 -#endif /* __CONSOLE_H__ */ +/* + * Register definitions used by GCC for GICv3 access. + * These are defined by ARMCC, so keep them in the GCC specific code for now. + */ +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_PMR_EL1 S3_0_C4_C6_0 + +func read_icc_sre_el1 + mrs x0, ICC_SRE_EL1 + ret + + +func read_icc_sre_el2 + mrs x0, ICC_SRE_EL2 + ret + + +func read_icc_sre_el3 + mrs x0, ICC_SRE_EL3 + ret + + +func write_icc_sre_el1 + msr ICC_SRE_EL1, x0 + isb + ret + + +func write_icc_sre_el2 + msr ICC_SRE_EL2, x0 + isb + ret + + +func write_icc_sre_el3 + msr ICC_SRE_EL3, x0 + isb + ret + + +func write_icc_pmr_el1 + msr ICC_PMR_EL1, x0 + isb + ret diff --git a/drivers/arm/gic/gic_v2.c b/drivers/arm/gic/gic_v2.c new file mode 100644 index 00000000..6af03782 --- /dev/null +++ b/drivers/arm/gic/gic_v2.c @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <assert.h> +#include <gic.h> +#include <mmio.h> + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ + +unsigned int gicd_read_igroupr(unsigned int base, unsigned int id) +{ + unsigned n = id >> IGROUPR_SHIFT; + return mmio_read_32(base + GICD_IGROUPR + (n << 2)); +} + +unsigned int gicd_read_isenabler(unsigned int base, unsigned int id) +{ + unsigned n = id >> ISENABLER_SHIFT; + return mmio_read_32(base + GICD_ISENABLER + (n << 2)); +} + +unsigned int gicd_read_icenabler(unsigned int base, unsigned int id) +{ + unsigned n = id >> ICENABLER_SHIFT; + return mmio_read_32(base + GICD_ICENABLER + (n << 2)); +} + +unsigned int gicd_read_ispendr(unsigned int base, unsigned int id) +{ + unsigned n = id >> ISPENDR_SHIFT; + return mmio_read_32(base + GICD_ISPENDR + (n << 2)); +} + +unsigned int gicd_read_icpendr(unsigned int base, unsigned int id) +{ + unsigned n = id >> ICPENDR_SHIFT; + return mmio_read_32(base + GICD_ICPENDR + (n << 2)); +} + +unsigned int gicd_read_isactiver(unsigned int base, unsigned int id) +{ + unsigned n = id >> ISACTIVER_SHIFT; + return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); +} + +unsigned int gicd_read_icactiver(unsigned int base, unsigned int id) +{ + unsigned n = id >> ICACTIVER_SHIFT; + return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); +} + +unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int id) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); +} + +unsigned int gicd_read_itargetsr(unsigned int base, unsigned int id) +{ + unsigned n = id >> ITARGETSR_SHIFT; + return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); +} + +unsigned int gicd_read_icfgr(unsigned int base, unsigned int id) +{ + unsigned n = id >> ICFGR_SHIFT; + return mmio_read_32(base + GICD_ICFGR + (n << 2)); +} + +unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int id) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); +} + +unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); +} + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ + +void gicd_write_igroupr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IGROUPR_SHIFT; + mmio_write_32(base + GICD_IGROUPR + (n << 2), val); +} + +void gicd_write_isenabler(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISENABLER_SHIFT; + mmio_write_32(base + GICD_ISENABLER + (n << 2), val); +} + +void gicd_write_icenabler(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICENABLER_SHIFT; + mmio_write_32(base + GICD_ICENABLER + (n << 2), val); +} + +void gicd_write_ispendr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISPENDR_SHIFT; + mmio_write_32(base + GICD_ISPENDR + (n << 2), val); +} + +void gicd_write_icpendr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICPENDR_SHIFT; + mmio_write_32(base + GICD_ICPENDR + (n << 2), val); +} + +void gicd_write_isactiver(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISACTIVER_SHIFT; + mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); +} + +void gicd_write_icactiver(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICACTIVER_SHIFT; + mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); +} + +void gicd_write_ipriorityr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); +} + +void gicd_write_itargetsr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ITARGETSR_SHIFT; + mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); +} + +void gicd_write_icfgr(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICFGR_SHIFT; + mmio_write_32(base + GICD_ICFGR + (n << 2), val); +} + +void gicd_write_cpendsgir(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); +} + +void gicd_write_spendsgir(unsigned int base, unsigned int id, unsigned int val) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); +} + +/******************************************************************************* + * GIC Distributor interface accessors for individual interrupt manipulation + ******************************************************************************/ +unsigned int gicd_get_igroupr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + return (reg_val >> bit_num) & 0x1; +} + +void gicd_set_igroupr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); +} + +void gicd_clr_igroupr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); +} + +void gicd_set_isenabler(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); + unsigned int reg_val = gicd_read_isenabler(base, id); + + gicd_write_isenabler(base, id, reg_val | (1 << bit_num)); +} + +void gicd_set_icenabler(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); + unsigned int reg_val = gicd_read_icenabler(base, id); + + gicd_write_icenabler(base, id, reg_val & ~(1 << bit_num)); +} + +void gicd_set_ispendr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); + unsigned int reg_val = gicd_read_ispendr(base, id); + + gicd_write_ispendr(base, id, reg_val | (1 << bit_num)); +} + +void gicd_set_icpendr(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); + unsigned int reg_val = gicd_read_icpendr(base, id); + + gicd_write_icpendr(base, id, reg_val & ~(1 << bit_num)); +} + +void gicd_set_isactiver(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); + unsigned int reg_val = gicd_read_isactiver(base, id); + + gicd_write_isactiver(base, id, reg_val | (1 << bit_num)); +} + +void gicd_set_icactiver(unsigned int base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); + unsigned int reg_val = gicd_read_icactiver(base, id); + + gicd_write_icactiver(base, id, reg_val & ~(1 << bit_num)); +} + +/* + * Make sure that the interrupt's group is set before expecting + * this function to do its job correctly. + */ +void gicd_set_ipriorityr(unsigned int base, unsigned int id, unsigned int pri) +{ + unsigned int reg = base + GICD_IPRIORITYR + (id & ~3); + unsigned int shift = (id & 3) << 3; + unsigned int reg_val = mmio_read_32(reg); + + /* + * Enforce ARM recommendation to manage priority values such + * that group1 interrupts always have a lower priority than + * group0 interrupts. + * Note, lower numerical values are higher priorities so the comparison + * checks below are reversed from what might be expected. + */ + assert(gicd_get_igroupr(base, id) == GRP1 ? + pri >= GIC_HIGHEST_NS_PRIORITY && + pri <= GIC_LOWEST_NS_PRIORITY : + pri >= GIC_HIGHEST_SEC_PRIORITY && + pri <= GIC_LOWEST_SEC_PRIORITY); + + reg_val &= ~(GIC_PRI_MASK << shift); + reg_val |= (pri & GIC_PRI_MASK) << shift; + mmio_write_32(reg, reg_val); +} + +void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int iface) +{ + unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1); + unsigned int reg_val = gicd_read_itargetsr(base, id); + + gicd_write_itargetsr(base, id, reg_val | + (1 << iface) << (byte_off << 3)); +} + diff --git a/drivers/io/io_memmap.h b/drivers/arm/gic/gic_v3.c index 5fa7bc98..b7db1f0d 100644 --- a/drivers/io/io_memmap.h +++ b/drivers/arm/gic/gic_v3.c @@ -28,9 +28,56 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __IO_MEMMAP_H__ -#define __IO_MEMMAP_H__ +#include <stdint.h> +#include <arch.h> +#include <platform.h> +#include <gic.h> +#include <gic_v3.h> +#include <debug.h> -int register_io_dev_memmap(struct io_dev_connector **dev_con); +uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr) +{ + uint32_t cpu_aff, gicr_aff; + uint64_t gicr_typer; + uintptr_t addr; -#endif /* __IO_MEMMAP_H__ */ + /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level + * mask is the same. + */ + cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF0_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF1_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF2_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF3_SHIFT; + + addr = gicr_base; + do { + gicr_typer = gicr_read_typer(addr); + + gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) & + GICR_TYPER_AFF_MASK; + if (cpu_aff == gicr_aff) { + /* Disable this print for now as it appears every time + * when using PSCI CPU_SUSPEND. + * TODO: Print this only the first time for each CPU. + * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n", + * mpidr, addr); + */ + return addr; + } + + /* TODO: + * For GICv4 we need to adjust the Base address based on + * GICR_TYPER.VLPIS + */ + addr += (1 << GICR_PCPUBASE_SHIFT); + + } while (!(gicr_typer & GICR_TYPER_LAST)); + + /* If we get here we did not find a match. */ + ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr); + return (uintptr_t)NULL; +} diff --git a/drivers/arm/interconnect/cci-400/cci400.h b/drivers/arm/interconnect/cci-400/cci400.h deleted file mode 100644 index 3921675f..00000000 --- a/drivers/arm/interconnect/cci-400/cci400.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __CCI_400_H__ -#define __CCI_400_H__ - -/* Slave interface offsets from PERIPHBASE */ -#define SLAVE_IFACE4_OFFSET 0x5000 -#define SLAVE_IFACE3_OFFSET 0x4000 -#define SLAVE_IFACE2_OFFSET 0x3000 -#define SLAVE_IFACE1_OFFSET 0x2000 -#define SLAVE_IFACE0_OFFSET 0x1000 -#define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + (0x1000 * index) - -/* Control and ID register offsets */ -#define CTRL_OVERRIDE_REG 0x0 -#define SPEC_CTRL_REG 0x4 -#define SECURE_ACCESS_REG 0x8 -#define STATUS_REG 0xc -#define IMPRECISE_ERR_REG 0x10 -#define PERFMON_CTRL_REG 0x100 - -/* Slave interface register offsets */ -#define SNOOP_CTRL_REG 0x0 -#define SH_OVERRIDE_REG 0x4 -#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 -#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 -#define QOS_CTRL_REG 0x10c -#define MAX_OT_REG 0x110 -#define TARGET_LATENCY_REG 0x130 -#define LATENCY_REGULATION_REG 0x134 -#define QOS_RANGE_REG 0x138 - -/* Snoop Control register bit definitions */ -#define DVM_EN_BIT (1 << 1) -#define SNOOP_EN_BIT (1 << 0) - -/* Status register bit definitions */ -#define CHANGE_PENDING_BIT (1 << 0) - -/* Function declarations */ -extern void cci_enable_coherency(unsigned long mpidr); -extern void cci_disable_coherency(unsigned long mpidr); - -#endif /* __CCI_400_H__ */ diff --git a/drivers/arm/interconnect/tzc-400/tzc400.h b/drivers/arm/interconnect/tzc-400/tzc400.h deleted file mode 100644 index 7eaafd2e..00000000 --- a/drivers/arm/interconnect/tzc-400/tzc400.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __TZC400_H__ -#define __TZC400_H__ - -#include <stdint.h> - -#define BUILD_CONFIG_OFF 0x000 -#define ACTION_OFF 0x004 -#define GATE_KEEPER_OFF 0x008 -#define SPECULATION_CTRL_OFF 0x00c -#define INT_STATUS 0x010 -#define INT_CLEAR 0x014 - -#define FAIL_ADDRESS_LOW_OFF 0x020 -#define FAIL_ADDRESS_HIGH_OFF 0x024 -#define FAIL_CONTROL_OFF 0x028 -#define FAIL_ID 0x02c - -#define REGION_BASE_LOW_OFF 0x100 -#define REGION_BASE_HIGH_OFF 0x104 -#define REGION_TOP_LOW_OFF 0x108 -#define REGION_TOP_HIGH_OFF 0x10c -#define REGION_ATTRIBUTES_OFF 0x110 -#define REGION_ID_ACCESS_OFF 0x114 -#define REGION_NUM_OFF(region) (0x20 * region) - -/* ID Registers */ -#define PID0_OFF 0xfe0 -#define PID1_OFF 0xfe4 -#define PID2_OFF 0xfe8 -#define PID3_OFF 0xfec -#define PID4_OFF 0xfd0 -#define PID5_OFF 0xfd4 -#define PID6_OFF 0xfd8 -#define PID7_OFF 0xfdc -#define CID0_OFF 0xff0 -#define CID1_OFF 0xff4 -#define CID2_OFF 0xff8 -#define CID3_OFF 0xffc - -#define BUILD_CONFIG_NF_SHIFT 24 -#define BUILD_CONFIG_NF_MASK 0x3 -#define BUILD_CONFIG_AW_SHIFT 8 -#define BUILD_CONFIG_AW_MASK 0x3f -#define BUILD_CONFIG_NR_SHIFT 0 -#define BUILD_CONFIG_NR_MASK 0x1f - -/* Not describing the case where regions 1 to 8 overlap */ -#define ACTION_RV_SHIFT 0 -#define ACTION_RV_MASK 0x3 -#define ACTION_RV_LOWOK 0x0 -#define ACTION_RV_LOWERR 0x1 -#define ACTION_RV_HIGHOK 0x2 -#define ACTION_RV_HIGHERR 0x3 - -/* - * Number of gate keepers is implementation defined. But we know the max for - * this device is 4. Get implementation details from BUILD_CONFIG. - */ -#define GATE_KEEPER_OS_SHIFT 16 -#define GATE_KEEPER_OS_MASK 0xf -#define GATE_KEEPER_OR_SHIFT 0 -#define GATE_KEEPER_OR_MASK 0xf - -/* Speculation is enabled by default. */ -#define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) -#define SPECULATION_CTRL_READ_DISABLE (1 << 0) - -/* Max number of filters allowed is 4. */ -#define INT_STATUS_OVERLAP_SHIFT 16 -#define INT_STATUS_OVERLAP_MASK 0xf -#define INT_STATUS_OVERRUN_SHIFT 8 -#define INT_STATUS_OVERRUN_MASK 0xf -#define INT_STATUS_STATUS_SHIFT 0 -#define INT_STATUS_STATUS_MASK 0xf - -#define INT_CLEAR_CLEAR_SHIFT 0 -#define INT_CLEAR_CLEAR_MASK 0xf - -#define FAIL_CONTROL_DIR_SHIFT (1 << 24) -#define FAIL_CONTROL_DIR_READ 0x0 -#define FAIL_CONTROL_DIR_WRITE 0x1 -#define FAIL_CONTROL_NS_SHIFT (1 << 21) -#define FAIL_CONTROL_NS_SECURE 0x0 -#define FAIL_CONTROL_NS_NONSECURE 0x1 -#define FAIL_CONTROL_PRIV_SHIFT (1 << 20) -#define FAIL_CONTROL_PRIV_PRIV 0x0 -#define FAIL_CONTROL_PRIV_UNPRIV 0x1 - -/* - * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. - * Platform should provide the value on initialisation. - */ -#define FAIL_ID_VNET_SHIFT 24 -#define FAIL_ID_VNET_MASK 0xf -#define FAIL_ID_ID_SHIFT 0 - -/* Used along with 'tzc_region_attributes_t' below */ -#define REGION_ATTRIBUTES_SEC_SHIFT 30 -#define REGION_ATTRIBUTES_F_EN_SHIFT 0 -#define REGION_ATTRIBUTES_F_EN_MASK 0xf - -#define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 -#define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 -#define REGION_ID_ACCESS_NSAID_ID_MASK 0xf - - -/* Macros for setting Region ID access permissions based on NSAID */ -#define TZC_REGION_ACCESS_RD(id) \ - ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ - REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) -#define TZC_REGION_ACCESS_WR(id) \ - ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ - REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) -#define TZC_REGION_ACCESS_RDWR(id) \ - (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) - -/* Filters are bit mapped 0 to 3. */ -#define TZC400_COMPONENT_ID 0xb105f00d - -#ifndef __ASSEMBLY__ - -/******************************************************************************* - * Function & variable prototypes - ******************************************************************************/ - -/* - * What type of action is expected when an access violation occurs. - * The memory requested is zeroed. But we can also raise and event to - * let the system know it happened. - * We can raise an interrupt(INT) and/or cause an exception(ERR). - * TZC_ACTION_NONE - No interrupt, no Exception - * TZC_ACTION_ERR - No interrupt, raise exception -> sync external - * data abort - * TZC_ACTION_INT - Raise interrupt, no exception - * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync - * external data abort - */ -enum tzc_action { - TZC_ACTION_NONE = 0, - TZC_ACTION_ERR = 1, - TZC_ACTION_INT = 2, - TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) -}; - -/* - * Controls secure access to a region. If not enabled secure access is not - * allowed to region. - */ -enum tzc_region_attributes { - TZC_REGION_S_NONE = 0, - TZC_REGION_S_RD = 1, - TZC_REGION_S_WR = 2, - TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) -}; - -/* - * Implementation defined values used to validate inputs later. - * Filters : max of 4 ; 0 to 3 - * Regions : max of 9 ; 0 to 8 - * Address width : Values between 32 to 64 - */ -struct tzc_instance { - uint64_t base; - uint32_t aid_width; - uint8_t addr_width; - uint8_t num_filters; - uint8_t num_regions; -}; - -void tzc_init(struct tzc_instance *controller); -void tzc_configure_region(const struct tzc_instance *controller, uint32_t filters, - uint8_t region, uint64_t region_base, uint64_t region_top, - enum tzc_region_attributes sec_attr, uint32_t ns_device_access); -void tzc_enable_filters(const struct tzc_instance *controller); -void tzc_disable_filters(const struct tzc_instance *controller); -void tzc_set_action(const struct tzc_instance *controller, - enum tzc_action action); - -#endif /*__ASSEMBLY__*/ - -#endif /* __TZC400__ */ diff --git a/drivers/arm/peripherals/pl011/pl011.h b/drivers/arm/peripherals/pl011/pl011.h deleted file mode 100644 index 5ad2fc7d..00000000 --- a/drivers/arm/peripherals/pl011/pl011.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __PL011_H__ -#define __PL011_H__ - -/* PL011 Registers */ -#define UARTDR 0x000 -#define UARTRSR 0x004 -#define UARTECR 0x004 -#define UARTFR 0x018 -#define UARTILPR 0x020 -#define UARTIBRD 0x024 -#define UARTFBRD 0x028 -#define UARTLCR_H 0x02C -#define UARTCR 0x030 -#define UARTIFLS 0x034 -#define UARTIMSC 0x038 -#define UARTRIS 0x03C -#define UARTMIS 0x040 -#define UARTICR 0x044 -#define UARTDMACR 0x048 - -/* Data status bits */ -#define UART_DATA_ERROR_MASK 0x0F00 - -/* Status reg bits */ -#define UART_STATUS_ERROR_MASK 0x0F - -/* Flag reg bits */ -#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ -#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ -#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ -#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ -#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ -#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ -#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ -#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ -#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ - -/* Control reg bits */ -#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ -#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ -#define PL011_UARTCR_RTS (1 << 11) /* Request to send */ -#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ -#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ -#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ -#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ -#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ - -#if !defined(PL011_BASE) -#error "The PL011_BASE macro must be defined." -#endif - -#if !defined(PL011_BAUDRATE) -#define PL011_BAUDRATE 115200 -#endif - -#if !defined(PL011_CLK_IN_HZ) -#define PL011_CLK_IN_HZ 24000000 -#endif - -#if !defined(PL011_LINE_CONTROL) -/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ -#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) -#endif - -/* Line Control Register Bits */ -#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ -#define PL011_UARTLCR_H_WLEN_8 (3 << 5) -#define PL011_UARTLCR_H_WLEN_7 (2 << 5) -#define PL011_UARTLCR_H_WLEN_6 (1 << 5) -#define PL011_UARTLCR_H_WLEN_5 (0 << 5) -#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ -#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ -#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ -#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ -#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ - -/******************************************************************************* - * Pl011 CPU interface accessors for writing registers - ******************************************************************************/ - -static inline void pl011_write_ibrd(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTIBRD, val); -} - -static inline void pl011_write_fbrd(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTFBRD, val); -} - -static inline void pl011_write_lcr_h(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTLCR_H, val); -} - -static inline void pl011_write_ecr(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTECR, val); -} - -static inline void pl011_write_cr(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTCR, val); -} - -static inline void pl011_write_dr(unsigned int base, unsigned int val) -{ - mmio_write_32(base + UARTDR, val); -} - -/******************************************************************************* - * Pl011 CPU interface accessors for reading registers - ******************************************************************************/ - -static inline unsigned int pl011_read_fr(unsigned int base) -{ - return mmio_read_32(base + UARTFR); -} - -static inline unsigned int pl011_read_dr(unsigned int base) -{ - return mmio_read_32(base + UARTDR); -} - -/******************************************************************************* - * Function prototypes - ******************************************************************************/ - -void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate); - -#endif /* __PL011_H__ */ diff --git a/drivers/arm/peripherals/pl011/pl011.c b/drivers/arm/pl011/pl011.c index 8288cd81..8288cd81 100644 --- a/drivers/arm/peripherals/pl011/pl011.c +++ b/drivers/arm/pl011/pl011.c diff --git a/drivers/arm/peripherals/pl011/pl011_console.c b/drivers/arm/pl011/pl011_console.c index 1a684ff6..1a684ff6 100644 --- a/drivers/arm/peripherals/pl011/pl011_console.c +++ b/drivers/arm/pl011/pl011_console.c diff --git a/drivers/arm/interconnect/tzc-400/tzc400.c b/drivers/arm/tzc400/tzc400.c index b88e34a9..b88e34a9 100644 --- a/drivers/arm/interconnect/tzc-400/tzc400.c +++ b/drivers/arm/tzc400/tzc400.c diff --git a/drivers/io/io_driver.h b/drivers/io/io_driver.h deleted file mode 100644 index 82dbbf12..00000000 --- a/drivers/io/io_driver.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IO_DRIVER_H__ -#define __IO_DRIVER_H__ - -#include "platform.h" /* For MAX_IO_DEVICES */ - - -/* Generic IO entity structure,representing an accessible IO construct on the - * device, such as a file */ -struct io_entity { - io_dev_handle dev_handle; - uintptr_t info; -}; - - -/* Device info structure, providing device-specific functions and a means of - * adding driver-specific state */ -struct io_dev_info { - struct io_dev_funcs *funcs; - uintptr_t info; -}; - - -/* Structure used to create a connection to a type of device */ -struct io_dev_connector { - /* dev_open opens a connection to a particular device driver */ - int (*dev_open)(void *spec, struct io_dev_info **dev_info); -}; - - -/* Structure to hold device driver function pointers */ -struct io_dev_funcs { - io_type (*type)(void); - int (*open)(struct io_dev_info *dev_info, const void *spec, - struct io_entity *entity); - int (*seek)(struct io_entity *entity, int mode, ssize_t offset); - int (*size)(struct io_entity *entity, size_t *length); - int (*read)(struct io_entity *entity, void *buffer, size_t length, - size_t *length_read); - int (*write)(struct io_entity *entity, const void *buffer, - size_t length, size_t *length_written); - int (*close)(struct io_entity *entity); - int (*dev_init)(struct io_dev_info *dev_info, const void *init_params); - int (*dev_close)(struct io_dev_info *dev_info); -}; - - -/* IO platform data - used to track devices registered for a specific - * platform */ -struct io_plat_data { - struct io_dev_info *devices[MAX_IO_DEVICES]; - unsigned int dev_count; -}; - - -/* Operations intended to be performed during platform initialisation */ - -/* Initialise the IO layer */ -void io_init(struct io_plat_data *data); - -/* Register a device driver */ -int io_register_device(struct io_dev_info *dev_info); - -#endif /* __IO_DRIVER_H__ */ diff --git a/drivers/io/io_fip.h b/drivers/io/io_fip.h deleted file mode 100644 index 56dd1e0f..00000000 --- a/drivers/io/io_fip.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IO_FIP_H__ -#define __IO_FIP_H__ - -int register_io_dev_fip(struct io_dev_connector **dev_con); - -#endif /* __IO_FIP_H__ */ diff --git a/drivers/io/io_semihosting.h b/drivers/io/io_semihosting.h deleted file mode 100644 index 7dc632dd..00000000 --- a/drivers/io/io_semihosting.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __IO_SH_H__ -#define __IO_SH_H__ - -int register_io_dev_sh(struct io_dev_connector **dev_con); - -#endif /* __IO_SH_H__ */ diff --git a/drivers/power/fvp_pwrc.h b/drivers/power/fvp_pwrc.h deleted file mode 100644 index f600a241..00000000 --- a/drivers/power/fvp_pwrc.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __FVP_PWRC_H__ -#define __FVP_PWRC_H__ - -/* FVP Power controller register offset etc */ -#define PPOFFR_OFF 0x0 -#define PPONR_OFF 0x4 -#define PCOFFR_OFF 0x8 -#define PWKUPR_OFF 0xc -#define PSYSR_OFF 0x10 - -#define PWKUPR_WEN (1ull << 31) - -#define PSYSR_AFF_L2 (1 << 31) -#define PSYSR_AFF_L1 (1 << 30) -#define PSYSR_AFF_L0 (1 << 29) -#define PSYSR_WEN (1 << 28) -#define PSYSR_PC (1 << 27) -#define PSYSR_PP (1 << 26) - -#define PSYSR_WK_SHIFT 24 -#define PSYSR_WK_MASK 0x3 -#define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK - -#define WKUP_COLD 0x0 -#define WKUP_RESET 0x1 -#define WKUP_PPONR 0x2 -#define WKUP_GICREQ 0x3 - -#define PSYSR_INVALID 0xffffffff - -#ifndef __ASSEMBLY__ - -/******************************************************************************* - * Function & variable prototypes - ******************************************************************************/ -extern int fvp_pwrc_setup(void); -extern void fvp_pwrc_write_pcoffr(unsigned long); -extern void fvp_pwrc_write_ppoffr(unsigned long); -extern void fvp_pwrc_write_pponr(unsigned long); -extern void fvp_pwrc_set_wen(unsigned long); -extern void fvp_pwrc_clr_wen(unsigned long); -extern unsigned int fvp_pwrc_read_psysr(unsigned long); -extern unsigned int fvp_pwrc_get_cpu_wkr(unsigned long); - -#endif /*__ASSEMBLY__*/ - -#endif /* __FVP_PWRC_H__ */ |