Merge pull request #99 from vikramkanigiri:vk/tf-issues-133_V3

3 files changed, 45 insertions, 32 deletions

diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 763303b3..f582e764 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -44,13 +44,34 @@
 	 */
 
 func bl31_entrypoint
+	/* ---------------------------------------------------------------
+	 * Preceding bootloader has populated x0 with a pointer to a
+	 * 'bl31_params' structure & x1 with a pointer to platform
+	 * specific structure
+	 * ---------------------------------------------------------------
+	 */
+#if !RESET_TO_BL31
+	mov	x20, x0
+	mov	x21, x1
+#else
+
+	/* -----------------------------------------------------
+	 * Perform any processor specific actions upon reset
+	 * e.g. cache, tlb invalidations etc. Override the
+	 * Boot ROM(BL0) programming sequence
+	 * -----------------------------------------------------
+	 */
+	bl	cpu_reset_handler
+#endif
+
 	/* ---------------------------------------------
-	 * BL2 has populated x0 with the opcode
-	 * indicating BL31 should be run, x3 with
-	 * a pointer to a 'bl31_args' structure & x4
- 	 * with any other optional information
+	 * Enable the instruction cache.
 	 * ---------------------------------------------
 	 */
+	mrs	x1, sctlr_el3
+	orr	x1, x1, #SCTLR_I_BIT
+	msr	sctlr_el3, x1
+	isb
 
 	/* ---------------------------------------------
 	 * Set the exception vector to something sane.
@@ -82,25 +103,10 @@ func bl31_entrypoint
 	bic	w1, w1, #TFP_BIT
 	msr	cptr_el3, x1
 
-	/* ---------------------------------------------
-	 * Enable the instruction cache.
-	 * ---------------------------------------------
-	 */
-	mrs	x1, sctlr_el3
-	orr	x1, x1, #SCTLR_I_BIT
-	msr	sctlr_el3, x1
-	isb
-
-	/* ---------------------------------------------
-	 * Check the opcodes out of paranoia.
-	 * ---------------------------------------------
-	 */
-	mov	x19, #RUN_IMAGE
-	cmp	x0, x19
-	b.ne	_panic
-	mov	x20, x3
-	mov	x21, x4
-
+#if RESET_TO_BL31
+	wait_for_entrypoint
+	bl	platform_mem_init
+#else
 	/* ---------------------------------------------
 	 * This is BL31 which is expected to be executed
 	 * only by the primary cpu (at least for now).
@@ -110,6 +116,7 @@ func bl31_entrypoint
 	mrs	x0, mpidr_el1
 	bl	platform_is_primary_cpu
 	cbz	x0, _panic
+#endif
 
 	/* ---------------------------------------------
 	 * Zero out NOBITS sections. There are 2 of them:
@@ -143,8 +150,14 @@ func bl31_entrypoint
 	 * Perform platform specific early arch. setup
 	 * ---------------------------------------------
 	 */
+#if RESET_TO_BL31
+	mov	x0, 0
+	mov	x1, 0
+#else
 	mov	x0, x20
 	mov	x1, x21
+#endif
+
 	bl	bl31_early_platform_setup
 	bl	bl31_plat_arch_setup
 
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index c0dc2fd1..6c9650f0 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -37,6 +37,7 @@ BL31_SOURCES		+=	bl31/bl31_main.c				\
 				bl31/aarch64/runtime_exceptions.S		\
 				bl31/aarch64/crash_reporting.S	\
 				common/aarch64/early_exceptions.S		\
+				lib/aarch64/cpu_helpers.S			\
 				lib/locks/bakery/bakery_lock.c			\
 				lib/locks/exclusive/spinlock.S			\
 				services/std_svc/std_svc_setup.c		\
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 561dbab8..ff7caf1d 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -43,7 +43,7 @@
  * for SP execution. In cases where both SPD and SP are absent, or when SPD
  * finds it impossible to execute SP, this pointer is left as NULL
  ******************************************************************************/
-static int32_t (*bl32_init)(meminfo_t *);
+static int32_t (*bl32_init)(void);
 
 /*******************************************************************************
  * Variable to indicate whether next image to execute after BL31 is BL33
@@ -114,11 +114,10 @@ void bl31_main(void)
 	 */
 
 	/*
-	 * If SPD had registerd an init hook, invoke it. Pass it the information
-	 * about memory extents
+	 * If SPD had registerd an init hook, invoke it.
 	 */
 	if (bl32_init)
-		(*bl32_init)(bl31_plat_get_bl32_mem_layout());
+		(*bl32_init)();
 
 	/*
 	 * We are ready to enter the next EL. Prepare entry into the image
@@ -152,7 +151,7 @@ uint32_t bl31_get_next_image_type(void)
  ******************************************************************************/
 void bl31_prepare_next_image_entry()
 {
-	el_change_info_t *next_image_info;
+	entry_point_info_t *next_image_info;
 	uint32_t scr, image_type;
 
 	/* Determine which image to execute next */
@@ -182,20 +181,20 @@ void bl31_prepare_next_image_entry()
 	 * Tell the context mgmt. library to ensure that SP_EL3 points to
 	 * the right context to exit from EL3 correctly.
 	 */
-	cm_set_el3_eret_context(next_image_info->security_state,
-			next_image_info->entrypoint,
+	cm_set_el3_eret_context(GET_SECURITY_STATE(next_image_info->h.attr),
+			next_image_info->pc,
 			next_image_info->spsr,
 			scr);
 
 	/* Finally set the next context */
-	cm_set_next_eret_context(next_image_info->security_state);
+	cm_set_next_eret_context(GET_SECURITY_STATE(next_image_info->h.attr));
 }
 
 /*******************************************************************************
  * This function initializes the pointer to BL32 init function. This is expected
  * to be called by the SPD after it finishes all its initialization
  ******************************************************************************/
-void bl31_register_bl32_init(int32_t (*func)(meminfo_t *))
+void bl31_register_bl32_init(int32_t (*func)(void))
 {
 	bl32_init = func;
 }