diff options
| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-04-24 15:33:24 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-07 09:27:36 +0100 |
| commit | 40fd072548ab47ce21bc48dc8059513048693f4e (patch) | |
| tree | 732fbe956cc63f9ba9ede13439c37c91c27df8a9 /bl31 | |
| parent | e404d7f44a190b82332bb96daffa0c6239732218 (diff) | |
Set processor endianness immediately after RESET
SCTLR_EL3.EE is being configured too late in bl1_arch_setup() and
bl31_arch_setup() after data accesses have already occured on
the cold and warm boot paths.
This control bit must be configured immediately on CPU reset to
match the endian state of the firmware (little endian).
Fixes ARM-software/tf-issues#145
Change-Id: Ie12e46fbbed6baf024c30beb50751591bb8c8655
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/aarch64/bl31_arch_setup.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c index acaa6b57..ad73de02 100644 --- a/bl31/aarch64/bl31_arch_setup.c +++ b/bl31/aarch64/bl31_arch_setup.c @@ -45,10 +45,9 @@ void bl31_arch_setup(void) unsigned long tmp_reg = 0; uint64_t counter_freq; - /* Enable alignment checks and set the exception endianness to LE */ + /* Enable alignment checks */ tmp_reg = read_sctlr_el3(); tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - tmp_reg &= ~SCTLR_EE_BIT; write_sctlr_el3(tmp_reg); /* |