diff options
author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-03-18 13:46:55 +0000 |
---|---|---|
committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-03-26 21:54:37 +0000 |
commit | 0a30cf54af7bb1f77b405062b1d5b44e809d0290 (patch) | |
tree | 9b7acf35e8b41803fb7a836dce428a9924ba1587 /bl31 | |
parent | dccc537a7243d784e0b8b81ce1634e385c3b048b (diff) |
Place assembler functions in separate sections
This extends the --gc-sections behaviour to the many assembler
support functions in the firmware images by placing each function
into its own code section. This is achieved by creating a 'func'
macro used to declare each function label.
Fixes ARM-software/tf-issues#80
Change-Id: I301937b630add292d2dec6d2561a7fcfa6fec690
Diffstat (limited to 'bl31')
-rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 5 | ||||
-rw-r--r-- | bl31/aarch64/context.S | 13 | ||||
-rw-r--r-- | bl31/aarch64/runtime_exceptions.S | 11 |
3 files changed, 16 insertions, 13 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 97f59f3e..d35b50a5 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -32,20 +32,19 @@ #include <platform.h> #include <arch.h> #include "cm_macros.S" +#include <asm_macros.S> .globl bl31_entrypoint - .section .text, "ax"; .align 3 - /* ----------------------------------------------------- * bl31_entrypoint() is the cold boot entrypoint, * executed only by the primary cpu. * ----------------------------------------------------- */ -bl31_entrypoint: ; .type bl31_entrypoint, %function +func bl31_entrypoint /* --------------------------------------------- * BL2 has populated x0 with the opcode * indicating BL31 should be run, x3 with diff --git a/bl31/aarch64/context.S b/bl31/aarch64/context.S index 5fe8bab0..2b2e7bf8 100644 --- a/bl31/aarch64/context.S +++ b/bl31/aarch64/context.S @@ -29,6 +29,7 @@ */ #include <context.h> +#include <asm_macros.S> /* ----------------------------------------------------- * The following function strictly follows the AArch64 @@ -39,7 +40,7 @@ * ----------------------------------------------------- */ .global el3_sysregs_context_save -el3_sysregs_context_save: +func el3_sysregs_context_save mrs x9, scr_el3 mrs x10, sctlr_el3 @@ -75,7 +76,7 @@ el3_sysregs_context_save: * ----------------------------------------------------- */ .global el3_sysregs_context_restore -el3_sysregs_context_restore: +func el3_sysregs_context_restore ldp x11, xzr, [x0, #CTX_CPTR_EL3] msr cptr_el3, x11 @@ -112,7 +113,7 @@ el3_sysregs_context_restore: * ----------------------------------------------------- */ .global el1_sysregs_context_save -el1_sysregs_context_save: +func el1_sysregs_context_save mrs x9, spsr_el1 mrs x10, elr_el1 @@ -193,7 +194,7 @@ el1_sysregs_context_save: * ----------------------------------------------------- */ .global el1_sysregs_context_restore -el1_sysregs_context_restore: +func el1_sysregs_context_restore ldp x9, x10, [x0, #CTX_SPSR_EL1] msr spsr_el1, x9 @@ -284,7 +285,7 @@ el1_sysregs_context_restore: * ----------------------------------------------------- */ .global fpregs_context_save -fpregs_context_save: +func fpregs_context_save stp q0, q1, [x0, #CTX_FP_Q0] stp q2, q3, [x0, #CTX_FP_Q2] stp q4, q5, [x0, #CTX_FP_Q4] @@ -327,7 +328,7 @@ fpregs_context_save: * ----------------------------------------------------- */ .global fpregs_context_restore -fpregs_context_restore: +func fpregs_context_restore ldp q0, q1, [x0, #CTX_FP_Q0] ldp q2, q3, [x0, #CTX_FP_Q2] ldp q4, q5, [x0, #CTX_FP_Q4] diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 223514e1..e16d8d95 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -203,7 +203,6 @@ serror_aarch32: .align 7 - .section .text, "ax" /* ----------------------------------------------------- * The following code handles secure monitor calls. * Depending upon the execution state from where the SMC @@ -217,6 +216,7 @@ serror_aarch32: * used here * ----------------------------------------------------- */ +func smc_handler smc_handler32: /* Check whether aarch32 issued an SMC64 */ tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited @@ -330,6 +330,9 @@ smc_handler64: * This routine assumes that the SP_EL3 is pointing to * a valid context structure from where the gp regs and * other special registers can be retrieved. + * + * Keep it in the same section as smc_handler as this + * function uses a fall-through to el3_exit * ----------------------------------------------------- */ el3_exit: ; .type el3_exit, %function @@ -383,7 +386,7 @@ rt_svc_fw_critical_error: * within the 32 instructions per exception vector. * ----------------------------------------------------- */ -save_scratch_registers: ; .type save_scratch_registers, %function +func save_scratch_registers stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] @@ -397,7 +400,7 @@ save_scratch_registers: ; .type save_scratch_registers, %function stp x18, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] ret -restore_scratch_registers: ; .type restore_scratch_registers, %function +func restore_scratch_registers ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] @@ -430,7 +433,7 @@ restore_scratch_registers_callee: * reporting unhandled exceptions * ----------------------------------------------------- */ -get_exception_stack: ; .type get_exception_stack, %function +func get_exception_stack mov x10, x30 // lr bl platform_get_core_pos add x0, x0, #1 |