diff options
| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2013-11-18 17:26:59 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2013-11-27 15:31:06 +0000 |
| commit | 3738274dc1b40ad846d41d7bfd6a597bcfba9e70 (patch) | |
| tree | 136c4d81d7b4f285ee37f1fdf674df5332a238d4 /bl1 | |
| parent | 204aa03da7d8a34d5e06fba3ccc9e565ed01d305 (diff) | |
Unmask SError and Debug exceptions.
Any asynchronous exception caused by the firmware should be handled
in the firmware itself. For this reason, unmask SError exceptions
(and Debug ones as well) on all boot paths. Also route external
abort and SError interrupts to EL3, otherwise they will target EL1.
Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index d4be9d6b..7085f778 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -48,11 +48,19 @@ void bl1_arch_setup(void) write_sctlr(tmp_reg); /* - * Enable HVCs, route FIQs to EL3, set the next EL to be aarch64 + * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route + * external abort and SError interrupts to EL3 */ - tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_FIQ_BIT; + tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT | + SCR_FIQ_BIT; write_scr(tmp_reg); + /* + * Enable SError and Debug exceptions + */ + enable_serror(); + enable_debug_exceptions(); + /* Do not trap coprocessor accesses from lower ELs to EL3 */ write_cptr_el3(0); |