blob: 38892e30e13443ee633c94bf0cd43c501a106705 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
|
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2015, Linaro Limited
*/
#ifndef PLATFORM_CONFIG_H
#define PLATFORM_CONFIG_H
/* Make stacks aligned to data cache line length */
#define STACK_ALIGNMENT 64
/* UART */
#define PERI_SUB_CTRL_ADDR 0x80000000
#define CONSOLE_UART_BASE (PERI_SUB_CTRL_ADDR + 0x00300000)
#define CONSOLE_BAUDRATE 115200
#define CONSOLE_UART_CLK_IN_HZ 200000000
/* ALG sub-controller */
#define ALG_SC_BASE 0xD0000000
#define ALG_SC_REG_SIZE 0xF010
/* RNG */
#define RNG_BASE 0xD1010000
#define RNG_REG_SIZE 0x18
/*
* HiSilicon D02 memory map
*
* Note: the physical address ranges below correspond to DRAM which is
* non-secure by default. Therefore, the terms TZDRAM and TZSRAM may not
* reflect the reality and only indicate areas that "would normally be"
* secure DRAM and secure SRAM in a more complete implementation.
* The memory map was defined like this for lack of better documentation.
* It is good enough for development/testing purposes.
*
* CFG_WITH_PAGER=n
*
* 0x7FC0_0000 -
* Linux/other | DRAM1
* 0x5180_0000 -
* TA RAM: 16 MiB |
* 0x5080_0000 | TZDRAM
* TEE RAM: 4 MiB (CFG_TEE_RAM_VA_SIZE) |
* 0x5040_0000 [TZDRAM_BASE, CFG_TEE_LOAD_ADDR] -
* Shared memory: 4 MiB | SHMEM
* 0x5000_0000 -
* Linux/other | DRAM0
* 0x0000_0000 [DRAM0_BASE] -
*
* CFG_WITH_PAGER=y
*
* 0x7FC0_0000 -
* Linux/other | DRAM1
* 0x5180_0000 -
* TA RAM: 20096 KiB (TZDRAM_SIZE) | TZDRAM
* 0x5046_0000 -
* TEE RAM: 384 KiB (TZSRAM_SIZE) | TZSRAM
* 0x5040_0000 [TZSRAM_BASE, CFG_TEE_LOAD_ADDR] -
* Shared memory: 4 MiB | SHMEM
* 0x5000_0000 -
* Linux/other | DRAM0
* 0x0000_0000 [DRAM0_BASE] -
*/
#define DRAM0_BASE 0x00000000
#define DRAM0_SIZE 0x50000000
#define DRAM1_BASE 0x51800000
#define DRAM1_SIZE 0x2E400000
#ifdef CFG_WITH_PAGER
#define TZSRAM_BASE 0x50400000
#define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE
#define TZDRAM_BASE 0x50460000
#define TZDRAM_SIZE (20096 * 1024)
#define CFG_TEE_RAM_START TZSRAM_BASE
#define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE
#define CFG_TA_RAM_START ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE)
#define CFG_TA_RAM_SIZE ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_DEVICE_SIZE)
#define CFG_TEE_RAM_VA_SIZE (2 * 1024 * 1024)
#else /* CFG_WITH_PAGER */
#define TZDRAM_BASE 0x50400000
#define TZDRAM_SIZE (20 * 1024 * 1024)
#define CFG_TEE_RAM_START TZDRAM_BASE
#define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE
#define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
CORE_MMU_DEVICE_SIZE)
#define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE),\
CORE_MMU_DEVICE_SIZE)
#define CFG_TEE_RAM_VA_SIZE (4 * 1024 * 1024)
#endif /* CFG_WITH_PAGER */
#define CFG_SHMEM_START 0x50000000
#define CFG_SHMEM_SIZE (4 * 1024 * 1024)
#define CFG_TEE_CORE_NB_CORE 16
#define CFG_TEE_LOAD_ADDR 0x50400000
#endif /* PLATFORM_CONFIG_H */
|