From 9eb3913636d5e7a78df087d5fce83825474c2d66 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 6 Dec 2018 00:26:41 +0100 Subject: Silicon/AMD/Styx: merge ACPI table drivers ACPI table support on Seattle is split into two parts for no good reason: AcpiPlatformDxe and AmdStyxAcpiLib. Let's merge them together, and clean up the code that iterates over the tables and installs them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 1 - Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 1 + Platform/LeMaker/CelloBoard/CelloBoard.dsc | 1 - Platform/LeMaker/CelloBoard/CelloBoard.fdf | 1 + .../Overdrive1000Board/Overdrive1000Board.dsc | 1 - .../Overdrive1000Board/Overdrive1000Board.fdf | 1 + Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 85 ----- Silicon/AMD/Styx/AcpiTables/Csrt.c | 107 ------ Silicon/AMD/Styx/AcpiTables/Dbg2.c | 114 ------- Silicon/AMD/Styx/AcpiTables/Fadt.c | 101 ------ Silicon/AMD/Styx/AcpiTables/Gtdt.c | 189 ----------- Silicon/AMD/Styx/AcpiTables/Iort.c | 371 --------------------- Silicon/AMD/Styx/AcpiTables/Madt.c | 318 ------------------ Silicon/AMD/Styx/AcpiTables/Mcfg.c | 51 --- Silicon/AMD/Styx/AcpiTables/Pptt.c | 225 ------------- Silicon/AMD/Styx/AcpiTables/Spcr.c | 124 ------- Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h | 62 ---- .../Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 117 +++---- .../Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.h | 53 +++ .../Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 31 +- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Csrt.aslc | 100 ++++++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dbg2.aslc | 108 ++++++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Fadt.aslc | 94 ++++++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Gtdt.aslc | 173 ++++++++++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Iort.aslc | 358 ++++++++++++++++++++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Madt.c | 319 ++++++++++++++++++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Mcfg.aslc | 46 +++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc | 219 ++++++++++++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Spcr.aslc | 118 +++++++ 29 files changed, 1672 insertions(+), 1817 deletions(-) delete mode 100644 Silicon/AMD/Styx/AcpiTables/AcpiTables.inf delete mode 100644 Silicon/AMD/Styx/AcpiTables/Csrt.c delete mode 100644 Silicon/AMD/Styx/AcpiTables/Dbg2.c delete mode 100644 Silicon/AMD/Styx/AcpiTables/Fadt.c delete mode 100644 Silicon/AMD/Styx/AcpiTables/Gtdt.c delete mode 100644 Silicon/AMD/Styx/AcpiTables/Iort.c delete mode 100644 Silicon/AMD/Styx/AcpiTables/Madt.c delete mode 100644 Silicon/AMD/Styx/AcpiTables/Mcfg.c delete mode 100644 Silicon/AMD/Styx/AcpiTables/Pptt.c delete mode 100644 Silicon/AMD/Styx/AcpiTables/Spcr.c delete mode 100644 Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.h create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Csrt.aslc create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dbg2.aslc create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Fadt.aslc create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Gtdt.aslc create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Iort.aslc create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Madt.c create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Mcfg.aslc create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc create mode 100644 Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Spcr.aslc diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 05433d44..ce909982 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -121,7 +121,6 @@ DEFINE DO_CAPSULE = FALSE # Styx specific libraries # AmdSataInit|Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf - AmdStyxAcpiLib|Silicon/AMD/Styx/AcpiTables/AcpiTables.inf ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf RealTimeClockLib|Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf index 96df83e0..c7e27e20 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -454,6 +454,7 @@ CAPSULE_HEADER_INIT_VERSION = 0x1 PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional RAW ASL Optional |.aml + RAW ACPI Optional |.acpi } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 057bf0eb..29e74069 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -118,7 +118,6 @@ DEFINE DO_FLASHER = FALSE # Styx specific libraries # AmdSataInit|Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf - AmdStyxAcpiLib|Silicon/AMD/Styx/AcpiTables/AcpiTables.inf ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf RealTimeClockLib|Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.fdf b/Platform/LeMaker/CelloBoard/CelloBoard.fdf index fc977f14..6362257d 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.fdf +++ b/Platform/LeMaker/CelloBoard/CelloBoard.fdf @@ -365,6 +365,7 @@ READ_LOCK_STATUS = TRUE PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional RAW ASL Optional |.aml + RAW ACPI Optional |.acpi } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 985ba225..f342cf82 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -117,7 +117,6 @@ DEFINE DO_FLASHER = FALSE # Styx specific libraries # AmdSataInit|Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf - AmdStyxAcpiLib|Silicon/AMD/Styx/AcpiTables/AcpiTables.inf ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf RealTimeClockLib|Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf index 8fc9a979..9ba98dd8 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf @@ -367,6 +367,7 @@ READ_LOCK_STATUS = TRUE PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional RAW ASL Optional |.aml + RAW ACPI Optional |.acpi } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf deleted file mode 100644 index 0bc5b1e9..00000000 --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf +++ /dev/null @@ -1,85 +0,0 @@ -#/** @file -# Sample ACPI Platform Driver -# -# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
-# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#**/ -#/** -# -# Derived from: -# MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = AmdStyxAcpiLib - FILE_GUID = 74850e9e-371c-43af-b1fe-794d61505ad0 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = AmdStyxAcpiLib - -[Sources] - Gtdt.c - Fadt.c - Dbg2.c - Spcr.c - Madt.c - Mcfg.c - Csrt.c - Iort.c - Pptt.c - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec - Silicon/AMD/Styx/AmdStyx.dec - -[LibraryClasses] - PcdLib - DebugLib - UefiBootServicesTableLib - -[Protocols] - gAmdMpCoreInfoProtocolGuid ## CONSUMED - -[Pcd] - gAmdStyxTokenSpaceGuid.PcdSocCoreCount - gAmdStyxTokenSpaceGuid.PcdSocCpuId - -[FixedPcd] - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - gArmTokenSpaceGuid.PcdGicDistributorBase - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase - gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase - gAmdStyxTokenSpaceGuid.PcdGicVersion - gAmdStyxTokenSpaceGuid.PcdGicHypervisorInterruptInterfaceBase - gAmdStyxTokenSpaceGuid.PcdGicVirtualInterruptInterfaceBase - gAmdStyxTokenSpaceGuid.PcdGicVirtualMaintenanceInterrupt - gAmdStyxTokenSpaceGuid.PcdGicVirtualRegisterInterfaceBase - gAmdStyxTokenSpaceGuid.PcdGicMSIFrameBase - gAmdStyxTokenSpaceGuid.PcdCntControlBase - gAmdStyxTokenSpaceGuid.PcdCntReadBase - gAmdStyxTokenSpaceGuid.PcdCntCTLBase - gAmdStyxTokenSpaceGuid.PcdCntBase0 - gAmdStyxTokenSpaceGuid.PcdCntEL0Base0 - gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogRefreshBase - gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogControlBase - gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV - gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV - gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster - gAmdStyxTokenSpaceGuid.PcdSata1PortCount - -[Depex] - gAmdMpCoreInfoProtocolGuid diff --git a/Silicon/AMD/Styx/AcpiTables/Csrt.c b/Silicon/AMD/Styx/AcpiTables/Csrt.c deleted file mode 100644 index f25f90da..00000000 --- a/Silicon/AMD/Styx/AcpiTables/Csrt.c +++ /dev/null @@ -1,107 +0,0 @@ -/** @file - - ACPI Memory mapped configuration space base address Description Table (MCFG). - Implementation based on PCI Firmware Specification Revision 3.0 final draft, - downloadable at http://www.pcisig.com/home - - Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. - - This program and the accompanying materials are licensed and - made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the - license may be found at http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include - -// -// CSRT for ARM_CCN504 (L3 CACHE) -// -#define AMD_ACPI_ARM_CCN504_CSRT_REVISION 0 -#define AMD_ACPI_ARM_CCN504_VENDOR_ID SIGNATURE_32('A','R','M','H') -#define AMD_ACPI_ARM_CCN504_DEVICE_ID 0x510 -#define AMD_ACPI_ARM_CCN504_RESOURCE_TYPE 0x04 -#define AMD_ACPI_ARM_CCN504_DESC_VERSION 1 -#define AMD_ACPI_ARM_CCN504_HNF_COUNT 8 -#define AMD_ACPI_ARM_CCN504_BASE_ADDR 0xE8000000ULL -#define AMD_ACPI_ARM_CCN504_CACHE_SIZE 0x00800000ULL - -// -// Ensure proper (byte-packed) structure formats -// -#pragma pack(push, 1) - -typedef struct { - UINT32 Version; - UINT8 HnfRegionCount; - UINT8 Reserved[3]; - UINT64 BaseAddress; - UINT64 CacheSize; -} AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR; - -typedef struct { - UINT32 Length; - UINT16 ResourceType; - UINT16 ResourceSubtype; - UINT32 UID; - AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR Ccn504Desc; -} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR; - -typedef struct { - UINT32 Length; - UINT32 VendorId; - UINT32 SubvendorId; - UINT16 DeviceId; - UINT16 SubdeviceId; - UINT16 Revision; - UINT8 Reserved[2]; - UINT32 SharedInfoLength; - AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR RsrcDesc; -} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP; - -typedef struct { - EFI_ACPI_DESCRIPTION_HEADER Header; - AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP RsrcGroup; -} AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE; - - -AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE AcpiCsrt = { - AMD_ACPI_HEADER (EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE, - AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE, - AMD_ACPI_ARM_CCN504_CSRT_REVISION), - { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP), // UINT32 RsrcGroup.Length - AMD_ACPI_ARM_CCN504_VENDOR_ID, // UINT32 RsrcGroup.VendorId - 0, // UINT32 RsrcGroup.SubvendorId - AMD_ACPI_ARM_CCN504_DEVICE_ID, // UINT16 RsrcGroup.DeviceId - 0, // UINT16 RsrcGroup.SubdeviceId - 0, // UINT16 RsrcGroup.Revision - { 0 }, // UINT8 RsrcGroup.Reserved[] - 0, // UINT32 RsrcGroup.SharedInfoLength - { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR), // UINT32 RsrcDesc.Length - AMD_ACPI_ARM_CCN504_RESOURCE_TYPE, // UINT16 RsrcDesc.ResourceType - 0, // UINT16 RsrcDesc.ResourceSubtype - 0, // UINT32 RsrcDesc.UID - { AMD_ACPI_ARM_CCN504_DESC_VERSION, // UINT32 Ccn504Desc.Version - AMD_ACPI_ARM_CCN504_HNF_COUNT, // UINT8 Ccn504Desc.HnfRegionCount - { 0 }, // UINT8 Ccn504Desc.Reserved[] - AMD_ACPI_ARM_CCN504_BASE_ADDR, // UINT64 Ccn504Desc.BaseAddress - AMD_ACPI_ARM_CCN504_CACHE_SIZE, // UINT64 Ccn504Desc.CacheSize - }, - }, - }, -}; - -#pragma pack(pop) - - -EFI_ACPI_DESCRIPTION_HEADER * -CsrtHeader ( - VOID - ) -{ - return &AcpiCsrt.Header; -} diff --git a/Silicon/AMD/Styx/AcpiTables/Dbg2.c b/Silicon/AMD/Styx/AcpiTables/Dbg2.c deleted file mode 100644 index 5d6cf82d..00000000 --- a/Silicon/AMD/Styx/AcpiTables/Dbg2.c +++ /dev/null @@ -1,114 +0,0 @@ -/** @file - - Microsoft Debug Port Table 2 (DBG2) - © 2012 Microsoft. All rights reserved.
- http://go.microsoft.com/fwlink/p/?linkid=403551 - - Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include - -#pragma pack(push, 1) - -#define EFI_ACPI_DBG2_REVISION 0 -#define DBG2_NUM_DEBUG_PORTS 1 -#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1 -#define DBG2_NAMESPACESTRING_FIELD_SIZE 8 -#define DBG2_OEM_DATA_FIELD_SIZE 0 -#define DBG2_OEM_DATA_FIELD_OFFSET 0 - -#define DBG2_DEBUG_PORT_SUBTYPE_PL011 0x0003 // Sub type for Pl011 -#define DBG2_DEBUG_PORT_SUBTYPE_UEFI 0x0007 // Sub type for UEFI Debug Port -#define PL011_UART_LENGTH 0x1000 - -#define NAME_STR_UART1 {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'} -#define NAME_STR_UEFI {'U', 'E', 'F', 'I', '\0', '\0', '\0', '\0'} - - -typedef struct { - EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; - EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; - UINT32 AddressSize; - UINT8 NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE]; -} DBG2_DEBUG_DEVICE_INFORMATION; - -typedef struct { - EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; - DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS]; -} DBG2_TABLE; - - -#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \ - { \ - EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision; */ \ - sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length; */ \ - NumReg, /* UINT8 NumberofGenericAddressRegisters; */ \ - DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength; */ \ - OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset; */ \ - DBG2_OEM_DATA_FIELD_SIZE, /* UINT16 OemDataLength; */ \ - DBG2_OEM_DATA_FIELD_OFFSET, /* UINT16 OemDataOffset; */ \ - EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type; */ \ - SubType, /* UINT16 Port Subtype; */ \ - {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2]; */ \ - OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset; */ \ - OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset; */ \ - }, \ - AMD_GASN (UartBase), /* EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \ - UartAddrLen, /* UINT32 AddressSize */ \ - UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \ - } - - -STATIC DBG2_TABLE AcpiDbg2 = { - { - AMD_ACPI_HEADER (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE, - DBG2_TABLE, - EFI_ACPI_DBG2_REVISION), - OFFSET_OF(DBG2_TABLE, Dbg2DeviceInfo), - DBG2_NUM_DEBUG_PORTS // UINT32 NumberDbgDeviceInfo - }, - { - /* - * Kernel Debug Port - */ -#if (DBG2_NUM_DEBUG_PORTS > 0) - DBG2_DEBUG_PORT_DDI(DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS, - DBG2_DEBUG_PORT_SUBTYPE_PL011, - FixedPcdGet64(PcdSerialDbgRegisterBase), - PL011_UART_LENGTH, - NAME_STR_UART1), -#endif - /* - * UEFI Debug Port - */ -#if (DBG2_NUM_DEBUG_PORTS > 1) - DBG2_DEBUG_PORT_DDI(0, - DBG2_DEBUG_PORT_SUBTYPE_UEFI, - 0, - 0, - NAME_STR_UEFI), -#endif - } -}; - -#pragma pack(pop) - -EFI_ACPI_DESCRIPTION_HEADER * -Dbg2Header ( - VOID - ) -{ - return &AcpiDbg2.Description.Header; -} - diff --git a/Silicon/AMD/Styx/AcpiTables/Fadt.c b/Silicon/AMD/Styx/AcpiTables/Fadt.c deleted file mode 100644 index bdf88a9c..00000000 --- a/Silicon/AMD/Styx/AcpiTables/Fadt.c +++ /dev/null @@ -1,101 +0,0 @@ -/** @file - - Fixed ACPI Description Table (FADT) - - Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ -/** - - Derived from: - ArmPlatformPkg/ArmJunoPkg/AcpiTables/Fadt.aslc - -**/ - -#include - -#define FADT_FLAGS ( EFI_ACPI_5_1_HW_REDUCED_ACPI | \ - EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE | \ - EFI_ACPI_5_1_HEADLESS ) - -#pragma pack(push, 1) - -STATIC EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = { - AMD_ACPI_HEADER (EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION), - 0, // UINT32 FirmwareCtrl - 0, // UINT32 Dsdt - EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile - 0, // UINT16 SciInt - 0, // UINT32 SmiCmd - 0, // UINT8 AcpiEnable - 0, // UINT8 AcpiDisable - 0, // UINT8 S4BiosReq - 0, // UINT8 PstateCnt - 0, // UINT32 Pm1aEvtBlk - 0, // UINT32 Pm1bEvtBlk - 0, // UINT32 Pm1aCntBlk - 0, // UINT32 Pm1bCntBlk - 0, // UINT32 Pm2CntBlk - 0, // UINT32 PmTmrBlk - 0, // UINT32 Gpe0Blk - 0, // UINT32 Gpe1Blk - 0, // UINT8 Pm1EvtLen - 0, // UINT8 Pm1CntLen - 0, // UINT8 Pm2CntLen - 0, // UINT8 PmTmrLen - 0, // UINT8 Gpe0BlkLen - 0, // UINT8 Gpe1BlkLen - 0, // UINT8 Gpe1Base - 0, // UINT8 CstCnt - 0, // UINT16 PLvl2Lat - 0, // UINT16 PLvl3Lat - 0, // UINT16 FlushSize - 0, // UINT16 FlushStride - 0, // UINT8 DutyOffset - 0, // UINT8 DutyWidth - 0, // UINT8 DayAlrm - 0, // UINT8 MonAlrm - 0, // UINT8 Century - 0, // UINT16 IaPcBootArch - 0, // UINT8 Reserved1 - FADT_FLAGS, // UINT32 Flags - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg - 0, // UINT8 ResetValue - EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch - 1, // UINT8 MinorVersion - 0, // UINT64 XFirmwareCtrl - 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg -}; - -#pragma pack(pop) - -EFI_ACPI_DESCRIPTION_HEADER * -FadtTable ( - VOID - ) -{ - return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiFadt; -} - diff --git a/Silicon/AMD/Styx/AcpiTables/Gtdt.c b/Silicon/AMD/Styx/AcpiTables/Gtdt.c deleted file mode 100644 index 139c9ae0..00000000 --- a/Silicon/AMD/Styx/AcpiTables/Gtdt.c +++ /dev/null @@ -1,189 +0,0 @@ -/** @file - - Generic Timer Description Table (GTDT) - - Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ -/** - - Derived from: - ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc - -**/ - -#include - -#pragma pack(push, 1) - -#define CNT_CONTROL_BASE_ADDRESS FixedPcdGet64(PcdCntControlBase) -#define CNT_READ_BASE_ADDRESS FixedPcdGet64(PcdCntReadBase) -#define CNT_CTL_BASE_ADDRESS FixedPcdGet64(PcdCntCTLBase) -#define CNT_BASE0_ADDRESS FixedPcdGet64(PcdCntBase0) -#define CNT_EL0_BASE0_ADDRESS FixedPcdGet64(PcdCntEL0Base0) -#define SBSA_WATCHDOG_REFRESH_BASE FixedPcdGet64(PcdSbsaWatchDogRefreshBase) -#define SBSA_WATCHDOG_CONTROL_BASE FixedPcdGet64(PcdSbsaWatchDogControlBase) -#define SBSA_WAKEUP_GSIV FixedPcdGet64(PcdSbsaWakeUpGSIV) -#define SBSA_WATCHDOG_GSIV FixedPcdGet64(PcdSbsaWatchDogGSIV) - - -/* - * Section 8.2.3 of Cortex-A15 r2p1 TRM - */ -#define CP15_TIMER_SEC_INTR 29 -#define CP15_TIMER_NS_INTR 30 -#define CP15_TIMER_VIRT_INTR 27 -#define CP15_TIMER_NSHYP_INTR 26 - -/* SBSA Timers */ - #define PLATFORM_TIMER_COUNT 2 - #define PLATFORM_TIMER_OFFSET sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) - -/* -// GTDT Table timer flags. - -Bit 0: Timer interrupt Mode - This bit indicates the mode of the timer interrupt - 1: Interrupt is Edge triggered - 0: Interrupt is Level triggered -Timer Interrupt polarity - This bit indicates the polarity of the timer interrupt - 1: Interrupt is Active low - 0: Interrupt is Active high -Reserved 2 30 Reserved, must be zero. - -From A15 TRM: - 9.2 Generic Timer functional description - ... - Each timer provides an active-LOW interrupt output that is an external pin to the SoC and is - sent to the GIC as a Private Peripheral Interrupt (PPI). See Interrupt sources on page 8-4 for - the ID and PPI allocation of the Timer interrupts. - PPI6 Virtual Maintenance Interrupt. - PPI5 Hypervisor timer event. - PPI4 Virtual timer event. - PPI3 nIRQ. - PPI2 Non-secure physical timer event. - PPI1 Secure physical timer event. - PPI0-5 Active-LOW level-sensitive. - PPI6 Active-HIGH level-sensitive.*/ - -#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE -#define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY -#define GTDT_TIMER_ACTIVE_HIGH 0 -#define GTDT_TIMER_SECURE EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY -#define GTDT_TIMER_NON_SECURE 0 -#define GTDT_GTIMER_FLAGS (GTDT_TIMER_NON_SECURE | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_LEVEL_TRIGGERED) - -#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE -#define GTX_TIMER_LEVEL_TRIGGERED 0 -#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY -#define GTX_TIMER_ACTIVE_HIGH 0 -#define GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED) - -#define GTX_TIMER_SECURE EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER -#define GTX_TIMER_NON_SECURE 0 -#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY -#define GTX_TIMER_LOSE_CONTEXT 0 -#define GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE) - -#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE -#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 -#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY -#define SBSA_WATCHDOG_ACTIVE_HIGH 0 -#define SBSA_WATCHDOG_SECURE EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER -#define SBSA_WATCHDOG_NON_SECURE 0 -#define SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED) - - -#define AMD_SBSA_GTX { \ - EFI_ACPI_5_1_GTDT_GT_BLOCK, /* UINT8 Type */ \ - sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) + \ - sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), /* UINT16 Length */ \ - EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \ - CNT_CTL_BASE_ADDRESS, /* UINT64 CntCtlBase */ \ - 1, /* UINT32 GTBlockTimerCount */ \ - sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) /* UINT32 GTBlockTimerOffset */ \ - } - -#define AMD_SBSA_GTX_TIMER { \ - 0, /* UINT8 GTFrameNumber */ \ - {0, 0, 0}, /* UINT8 Reserved[3] */ \ - CNT_BASE0_ADDRESS, /* UINT64 CntBaseX */ \ - CNT_EL0_BASE0_ADDRESS, /* UINT64 CntEL0BaseX */ \ - SBSA_WAKEUP_GSIV, /* UINT32 GTxPhysicalTimerGSIV */ \ - GTX_TIMER_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \ - 0, /* UINT32 GTxVirtualTimerGSIV */ \ - GTX_TIMER_FLAGS, /* UINT32 GTxVirtualTimerFlags */ \ - GTX_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \ - } - -#define AMD_SBSA_WATCHDOG { \ - EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG, /* UINT8 Type */ \ - sizeof (EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), /* UINT16 Length */ \ - EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \ - SBSA_WATCHDOG_REFRESH_BASE, /* UINT64 RefreshFramePhysicalAddress */ \ - SBSA_WATCHDOG_CONTROL_BASE, /* UINT64 WatchdogControlFramePhysicalAddress */ \ - SBSA_WATCHDOG_GSIV, /* UINT32 WatchdogTimerGSIV */ \ - SBSA_WATCHDOG_FLAGS /* UINT32 WatchdogTimerFlags */ \ - } - -typedef struct { - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE GTxBlock; - EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE GTxTimer; - EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE WatchDog; -} AMD_ACPI_5_1_ARM_GTDT_STRUCTURE; - -STATIC AMD_ACPI_5_1_ARM_GTDT_STRUCTURE AcpiGtdt = { - { - AMD_ACPI_HEADER(EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - AMD_ACPI_5_1_ARM_GTDT_STRUCTURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION), - CNT_CONTROL_BASE_ADDRESS, // UINT64 PhysicalAddress - 0, // UINT32 Reserved - CP15_TIMER_SEC_INTR, // UINT32 SecureEL1TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 SecureEL1TimerFlags - CP15_TIMER_NS_INTR, // UINT32 NonSecureEL1TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL1TimerFlags - CP15_TIMER_VIRT_INTR, // UINT32 VirtualTimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags - CP15_TIMER_NSHYP_INTR, // UINT32 NonSecureEL2TimerGSIV - GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL2TimerFlags - CNT_READ_BASE_ADDRESS, // UINT64 CntReadBaseAddress - PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount - PLATFORM_TIMER_OFFSET // UINT32 PlatformTimerOffset - }, - AMD_SBSA_GTX, - AMD_SBSA_GTX_TIMER, - AMD_SBSA_WATCHDOG, -}; - -#pragma pack(pop) - - -EFI_ACPI_DESCRIPTION_HEADER * -GtdtHeader ( - VOID - ) -{ - UINT32 CpuId = PcdGet32 (PcdSocCpuId); - - // Check BaseModel and Stepping: Styx-B0 or prior? - if (((CpuId & 0xFF0) == 0) || ((CpuId & 0x00F) == 0)) { - AcpiGtdt.Gtdt.Header.Length = sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE); - AcpiGtdt.Gtdt.PlatformTimerCount = 0; - AcpiGtdt.Gtdt.PlatformTimerOffset = 0; - } - - return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiGtdt.Gtdt.Header; -} diff --git a/Silicon/AMD/Styx/AcpiTables/Iort.c b/Silicon/AMD/Styx/AcpiTables/Iort.c deleted file mode 100644 index 9c232379..00000000 --- a/Silicon/AMD/Styx/AcpiTables/Iort.c +++ /dev/null @@ -1,371 +0,0 @@ -/** @file - - Copyright (c) 2017, Linaro, Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include -#include - -#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) - -#define STYX_PCIE_SMMU_BASE 0xE0A00000 -#define STYX_PCIE_SMMU_SIZE 0x10000 -#define STYX_PCIE_SMMU_INTERRUPT 0x16d - -#define STYX_ETH0_SMMU_BASE 0xE0600000 -#define STYX_ETH0_SMMU_SIZE 0x10000 -#define STYX_ETH0_SMMU_INTERRUPT 0x170 - -#define STYX_ETH1_SMMU_BASE 0xE0800000 -#define STYX_ETH1_SMMU_SIZE 0x10000 -#define STYX_ETH1_SMMU_INTERRUPT 0x16f - -#define STYX_SATA0_SMMU_BASE 0xE0200000 -#define STYX_SATA0_SMMU_SIZE 0x10000 -#define STYX_SATA0_SMMU_INTERRUPT 0x16c - -#define STYX_SATA1_SMMU_BASE 0xE0C00000 -#define STYX_SATA1_SMMU_SIZE 0x10000 -#define STYX_SATA1_SMMU_INTERRUPT 0x16b - -#pragma pack(1) -typedef struct { - EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; - EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[1]; -} STYX_SMMU_NODE; - -typedef struct { - EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; - EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1]; -} STYX_RC_NODE; - -typedef struct { - EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; - CONST CHAR8 Name[11]; - EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[32]; -} STYX_NC_NODE; - -typedef struct { - EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; - STYX_SMMU_NODE PciSmmuNode; - STYX_RC_NODE PciRcNode; - -#if DO_XGBE - STYX_SMMU_NODE Eth0SmmuNode; - STYX_NC_NODE Eth0NamedNode; - STYX_SMMU_NODE Eth1SmmuNode; - STYX_NC_NODE Eth1NamedNode; -#endif - - STYX_SMMU_NODE Sata0SmmuNode; - STYX_NC_NODE Sata0NamedNode; - STYX_SMMU_NODE Sata1SmmuNode; - STYX_NC_NODE Sata1NamedNode; -} STYX_IO_REMAPPING_STRUCTURE; - -#define __STYX_SMMU_NODE(Base, Size, Irq) \ - { \ - { \ - EFI_ACPI_IORT_TYPE_SMMUv1v2, \ - sizeof(STYX_SMMU_NODE), \ - 0x0, \ - 0x0, \ - 0x0, \ - 0x0, \ - }, \ - Base, \ - Size, \ - EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401, \ - EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \ - FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \ - SMMU_NSgIrpt), \ - 0x1, \ - sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \ - 0x0, \ - 0x0, \ - Irq, \ - EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ - 0x0, \ - 0x0, \ - }, { \ - { \ - Irq, \ - EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ - }, \ - } - -#define __STYX_ID_MAPPING(In, Num, Out, Ref, Flags) \ - { \ - In, \ - Num, \ - Out, \ - FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \ - Flags \ - } - -#define __STYX_ID_MAPPING_SINGLE(Out, Ref) \ - { \ - 0x0, \ - 0x0, \ - Out, \ - FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \ - EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE \ - } - -#define __STYX_NAMED_COMPONENT_NODE(Name) \ - { \ - { \ - EFI_ACPI_IORT_TYPE_NAMED_COMP, \ - sizeof(STYX_NC_NODE), \ - 0x0, \ - 0x0, \ - 0x20, \ - FIELD_OFFSET(STYX_NC_NODE, RcIdMapping), \ - }, \ - 0x0, \ - EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, \ - 0x0, \ - 0x0, \ - EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | \ - EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, \ - 40, \ - }, \ - Name - -STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = { - { - AMD_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, - STYX_IO_REMAPPING_STRUCTURE, - EFI_ACPI_IO_REMAPPING_TABLE_REVISION), -#if DO_XGBE - 10, // NumNodes -#else - 6, // NumNodes -#endif - sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset - 0 // Reserved - }, { - // PciSmmuNode - __STYX_SMMU_NODE(STYX_PCIE_SMMU_BASE, - STYX_PCIE_SMMU_SIZE, - STYX_PCIE_SMMU_INTERRUPT) - }, { - // PciRcNode - { - { - EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type - sizeof(STYX_RC_NODE), // Length - 0x0, // Revision - 0x0, // Reserved - 0x1, // NumIdMappings - FIELD_OFFSET(STYX_RC_NODE, RcIdMapping), // IdReference - }, - EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent - 0x0, // AllocationHints - 0x0, // Reserved - EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | - EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags - EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute - 0x0, // PciSegmentNumber - }, { - __STYX_ID_MAPPING(0x0, 0xffff, 0x0, PciSmmuNode, 0x0), - } -#if DO_XGBE - }, { - // Eth0SmmuNode - __STYX_SMMU_NODE(STYX_ETH0_SMMU_BASE, - STYX_ETH0_SMMU_SIZE, - STYX_ETH0_SMMU_INTERRUPT) - }, { - // Eth0NamedNode - __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH0"), - { - __STYX_ID_MAPPING_SINGLE(0x00, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x01, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x02, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x03, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x04, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x05, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x06, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x07, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x08, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x09, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0A, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0B, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0C, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0D, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0E, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0F, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x10, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x11, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x12, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x13, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x14, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x15, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x16, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x17, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x18, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x19, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1A, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1B, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1C, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1D, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1E, Eth0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1F, Eth0SmmuNode), - } - }, { - // Eth1SmmuNode - __STYX_SMMU_NODE(STYX_ETH1_SMMU_BASE, - STYX_ETH1_SMMU_SIZE, - STYX_ETH1_SMMU_INTERRUPT) - }, { - // Eth1NamedNode - __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH1"), - { - __STYX_ID_MAPPING_SINGLE(0x00, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x01, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x02, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x03, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x04, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x05, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x06, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x07, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x08, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x09, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0A, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0B, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0C, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0D, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0E, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0F, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x10, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x11, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x12, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x13, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x14, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x15, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x16, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x17, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x18, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x19, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1A, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1B, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1C, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1D, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1E, Eth1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1F, Eth1SmmuNode), - } -#endif - }, { - // Sata0SmmuNode - __STYX_SMMU_NODE(STYX_SATA0_SMMU_BASE, - STYX_SATA0_SMMU_SIZE, - STYX_SATA0_SMMU_INTERRUPT) - }, { - // Sata0NamedNode - __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC0"), - { - __STYX_ID_MAPPING_SINGLE(0x00, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x01, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x02, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x03, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x04, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x05, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x06, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x07, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x08, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x09, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0A, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0B, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0C, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0D, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0E, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0F, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x10, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x11, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x12, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x13, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x14, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x15, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x16, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x17, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x18, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x19, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1A, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1B, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1C, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1D, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1E, Sata0SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1F, Sata0SmmuNode), - } - }, { - // Sata1SmmuNode - __STYX_SMMU_NODE(STYX_SATA1_SMMU_BASE, - STYX_SATA1_SMMU_SIZE, - STYX_SATA1_SMMU_INTERRUPT) - }, { - // Sata1NamedNode - __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC1"), - { - __STYX_ID_MAPPING_SINGLE(0x00, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x01, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x02, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x03, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x04, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x05, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x06, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x07, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x08, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x09, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0A, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0B, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0C, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0D, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0E, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x0F, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x10, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x11, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x12, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x13, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x14, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x15, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x16, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x17, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x18, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x19, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1A, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1B, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1C, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1D, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1E, Sata1SmmuNode), - __STYX_ID_MAPPING_SINGLE(0x1F, Sata1SmmuNode), - } - } -}; - -#pragma pack() - -EFI_ACPI_DESCRIPTION_HEADER * -IortHeader ( - VOID - ) -{ - if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) { - // - // Silicon revisions prior to B1 have only one SATA port, - // so omit the nodes of the second port in this case. - // - AcpiIort.Iort.NumNodes -= 2; - } - return (EFI_ACPI_DESCRIPTION_HEADER *)&AcpiIort.Iort.Header; -} diff --git a/Silicon/AMD/Styx/AcpiTables/Madt.c b/Silicon/AMD/Styx/AcpiTables/Madt.c deleted file mode 100644 index 43d415c8..00000000 --- a/Silicon/AMD/Styx/AcpiTables/Madt.c +++ /dev/null @@ -1,318 +0,0 @@ -/** @file - - Multiple APIC Description Table (MADT) - - Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
- Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ -/** - - Derived from: - ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc - -**/ - -#include -#include -#include -#include -#include - -#include -#include - -AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL; - - -// ARM PL390 General Interrupt Controller -#define GIC_BASE (FixedPcdGet64 (PcdGicInterruptInterfaceBase)) -#define GICD_BASE (FixedPcdGet64 (PcdGicDistributorBase)) -#define GICV_BASE (FixedPcdGet64 (PcdGicVirtualInterruptInterfaceBase)) -#define GICH_BASE (FixedPcdGet64 (PcdGicHypervisorInterruptInterfaceBase)) -#define VGIC_MAINT_INT (FixedPcdGet32 (PcdGicVirtualMaintenanceInterrupt)) -#define GICVR_BASE (FixedPcdGet64 (PcdGicVirtualRegisterInterfaceBase)) -#define GIC_MSI_FRAME (FixedPcdGet64 (PcdGicMSIFrameBase)) -#define GIC_VERSION (FixedPcdGet8 (PcdGicVersion)) - -#define GICD_ID ( 0 ) -#define GICD_VECTOR ( 0 ) - -#define GICM_ID ( 0 ) -#define GICM_SPI_COUNT ( 0x100 ) -#define GICM_SPI_BASE ( 0x40 ) -#define GSIV_SPI_OFFSET ( 32 ) - -#if STYX_A0 - #define MSI_TYPER_FLAG ( 1 ) // Ignore TYPER register and use Count/Base fields -#else - #define MSI_TYPER_FLAG ( 0 ) // Use TYPER register and ignore Count/Base fields -#endif - -#define CORES_PER_CLUSTER (FixedPcdGet32 (PcdSocCoresPerCluster)) - - -/* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */ -#define AMD_GIC(CpuNum, ClusterId, CoreId, PerfInt) { \ - EFI_ACPI_5_1_GIC, /* UINT8 Type */ \ - sizeof (EFI_ACPI_5_1_GIC_STRUCTURE), /* UINT8 Length */ \ - EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved */ \ - CpuNum, /* UINT32 CPUInterfaceNumber */ \ - (ClusterId << 8) | CoreId, /* UINT32 AcpiProcessorUid */ \ - EFI_ACPI_5_1_GIC_ENABLED, /* UINT32 Flags */ \ - 0, /* UINT32 ParkingProtocolVersion */ \ - PerfInt, /* UINT32 PerformanceInterruptGsiv */ \ - 0, /* UINT64 ParkedAddress */ \ - GIC_BASE, /* UINT64 PhysicalBaseAddress */ \ - GICV_BASE, /* UINT64 GICV */ \ - GICH_BASE, /* UINT64 GICH */ \ - VGIC_MAINT_INT, /* UINT32 VGICMaintenanceInterrupt */ \ - GICVR_BASE, /* UINT64 GICRBaseAddress */ \ - (ClusterId << 8) | CoreId /* UINT64 MPIDR */ \ - } - -/* Macro to initialise EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE */ -#define AMD_GICD(Id, Vec) { \ - EFI_ACPI_5_1_GICD, /* UINT8 Type */ \ - sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE), /* UINT8 Length */ \ - EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \ - Id, /* UINT32 GicId */ \ - GICD_BASE, /* UINT64 PhysicalBaseAddress */ \ - Vec, /* UINT32 SystemVectorBase */ \ - EFI_ACPI_RESERVED_DWORD /* UINT32 Reserved2 */ \ - } - -/* Macro to initialise EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE */ -#define AMD_GICM(Id, SpiCount, SpiBase) { \ - EFI_ACPI_5_1_GIC_MSI_FRAME, /* UINT8 Type */ \ - sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE), /* UINT8 Length */ \ - EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \ - Id, /* UINT32 GicMsiFrameId */ \ - GIC_MSI_FRAME, /* UINT64 PhysicalBaseAddress */ \ - MSI_TYPER_FLAG, /* UINT32 Flags */ \ - SpiCount, /* UINT16 SPICount */ \ - SpiBase /* UINT16 SPIBase */ \ - } - - -// -// NOTE: NUM_CORES is a pre-processor macro passed in with -D option -// -#pragma pack(push, 1) -typedef struct { - EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_5_1_GIC_STRUCTURE GicC[NUM_CORES]; - EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE GicD; - EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE GicM; -} EFI_ACPI_5_1_ARM_MADT_STRUCTURE; -#pragma pack(pop) - - -STATIC EFI_ACPI_5_1_ARM_MADT_STRUCTURE AcpiMadt = { - { - AMD_ACPI_HEADER (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_ARM_MADT_STRUCTURE, - EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), - GIC_BASE, // UINT32 LocalApicAddress - 0 // UINT32 Flags - }, - { - /* - * GIC Interface for Cluster 0 CPU 0 - */ - AMD_GIC(0, 0, 0, 39), // EFI_ACPI_5_1_GIC_STRUCTURE -#if (NUM_CORES > 1) - /* - * GIC Interface for Cluster 0 CPU 1 - */ - AMD_GIC(1, 0, 1, 40), // EFI_ACPI_5_1_GIC_STRUCTURE -#endif -#if (NUM_CORES > 2) - /* - * GIC Interface for Cluster 1 CPU 0 - */ - AMD_GIC(2, 1, 0, 41), // EFI_ACPI_5_1_GIC_STRUCTURE -#endif -#if (NUM_CORES > 3) - /* - * GIC Interface for Cluster 1 CPU 1 - */ - AMD_GIC(3, 1, 1, 42), // EFI_ACPI_5_1_GIC_STRUCTURE -#endif -#if (NUM_CORES > 4) - /* - * GIC Interface for Cluster 2 CPU 0 - */ - AMD_GIC(4, 2, 0, 43), // EFI_ACPI_5_1_GIC_STRUCTURE -#endif -#if (NUM_CORES > 5) - /* - * GIC Interface for Cluster 2 CPU 1 - */ - AMD_GIC(5, 2, 1, 44), // EFI_ACPI_5_1_GIC_STRUCTURE -#endif -#if (NUM_CORES > 6) - /* - * GIC Interface for Cluster 3 CPU 0 - */ - AMD_GIC(6, 3, 0, 45), // EFI_ACPI_5_1_GIC_STRUCTURE -#endif -#if (NUM_CORES > 7) - /* - * GIC Interface for Cluster 3 CPU 1 - */ - AMD_GIC(7, 3, 1, 46), // EFI_ACPI_5_1_GIC_STRUCTURE -#endif - }, - /* - * GIC Distributor - */ - AMD_GICD(GICD_ID, GICD_VECTOR), // EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE - /* - * GIC MSI Frame - */ - AMD_GICM(GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE), -}; - - -STATIC -EFI_STATUS -BuildGicC ( - EFI_ACPI_5_1_GIC_STRUCTURE *GicC, - UINT32 CpuNum, - UINT32 ClusterId, - UINT32 CoreId - ) -{ - UINT32 MpId, PmuSpi; - EFI_STATUS Status; - - MpId = (UINT32) GET_MPID (ClusterId, CoreId); - Status = mAmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuSpi); - if (EFI_ERROR (Status)) - return Status; - - GicC->Type = EFI_ACPI_5_1_GIC; - GicC->Length = sizeof (EFI_ACPI_5_1_GIC_STRUCTURE); - GicC->Reserved = EFI_ACPI_RESERVED_WORD; - GicC->CPUInterfaceNumber = CpuNum; - GicC->AcpiProcessorUid = MpId; - GicC->Flags = EFI_ACPI_5_1_GIC_ENABLED; - GicC->PhysicalBaseAddress = GIC_BASE; - GicC->GICV = GICV_BASE; - GicC->GICH = GICH_BASE; - GicC->VGICMaintenanceInterrupt = VGIC_MAINT_INT; - GicC->GICRBaseAddress = GICVR_BASE; - GicC->PerformanceInterruptGsiv = PmuSpi + GSIV_SPI_OFFSET; - GicC->MPIDR = MpId; - - return EFI_SUCCESS; -} - -STATIC -VOID -BuildGicD ( - EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD, - UINT32 GicId, - UINT32 SystemVectorBase - ) -{ - GicD->Type = EFI_ACPI_5_1_GICD; - GicD->Length = sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE); - GicD->Reserved1 = EFI_ACPI_RESERVED_WORD; - GicD->GicId = GicId; - GicD->PhysicalBaseAddress = GICD_BASE; - GicD->SystemVectorBase = SystemVectorBase; -#if 0 - GicD->Reserved2 = EFI_ACPI_RESERVED_DWORD; -#else - GicD->GicVersion = EFI_ACPI_RESERVED_BYTE; - GicD->Reserved2[0] = EFI_ACPI_RESERVED_BYTE; - GicD->Reserved2[1] = EFI_ACPI_RESERVED_BYTE; - GicD->Reserved2[2] = EFI_ACPI_RESERVED_BYTE; -#endif -} - - -STATIC -VOID -BuildGicM ( - EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM, - UINT32 MsiFrameId, - UINT16 SpiCount, - UINT16 SpiBase - ) -{ - GicM->Type = EFI_ACPI_5_1_GIC_MSI_FRAME; - GicM->Length = sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE); - GicM->Reserved1 = EFI_ACPI_RESERVED_WORD; - GicM->GicMsiFrameId = MsiFrameId; - GicM->PhysicalBaseAddress = GIC_MSI_FRAME; - GicM->Flags = MSI_TYPER_FLAG; - GicM->SPICount = SpiCount; - GicM->SPIBase = SpiBase; -} - - -EFI_ACPI_DESCRIPTION_HEADER * -MadtHeader ( - VOID - ) -{ - EFI_ACPI_5_1_GIC_STRUCTURE *GicC; - EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD; - EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM; - ARM_CORE_INFO *ArmCoreInfoTable; - UINTN CoreCount, CpuNum; - EFI_STATUS Status; - - Status = gBS->LocateProtocol ( - &gAmdMpCoreInfoProtocolGuid, - NULL, - (VOID **)&mAmdMpCoreInfoProtocol - ); - ASSERT_EFI_ERROR (Status); - - // Get pointer to ARM core info table - ArmCoreInfoTable = mAmdMpCoreInfoProtocol->GetArmCoreInfoTable (&CoreCount); - ASSERT (ArmCoreInfoTable != NULL); - - // Make sure SoC's core count does not exceed what we want to build - ASSERT (CoreCount <= NUM_CORES); - ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount)); - - GicC = (EFI_ACPI_5_1_GIC_STRUCTURE *)&AcpiMadt.GicC[0]; - AcpiMadt.Header.Header.Length = sizeof (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); - - for (CpuNum = 0; CpuNum < CoreCount; ++CpuNum, ++GicC) { - DEBUG ((EFI_D_ERROR, "MADT: Core[%d]: ClusterId = %d CoreId = %d\n", - CpuNum, ArmCoreInfoTable[CpuNum].ClusterId, ArmCoreInfoTable[CpuNum].CoreId)); - - Status = BuildGicC (GicC, CpuNum, - ArmCoreInfoTable[CpuNum].ClusterId, - ArmCoreInfoTable[CpuNum].CoreId - ); - ASSERT_EFI_ERROR (Status); - - AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_STRUCTURE); - } - - GicD = (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length); - BuildGicD (GicD, GICD_ID, GICD_VECTOR); - AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE); - - GicM = (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length); - BuildGicM (GicM, GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE); - AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE); - - return &AcpiMadt.Header.Header; -} - diff --git a/Silicon/AMD/Styx/AcpiTables/Mcfg.c b/Silicon/AMD/Styx/AcpiTables/Mcfg.c deleted file mode 100644 index 4fc18e8e..00000000 --- a/Silicon/AMD/Styx/AcpiTables/Mcfg.c +++ /dev/null @@ -1,51 +0,0 @@ -/** @file - - ACPI Memory mapped configuration space base address Description Table (MCFG). - Implementation based on PCI Firmware Specification Revision 3.0 final draft, - downloadable at http://www.pcisig.com/home - - Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. - - This program and the accompanying materials are licensed and - made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the - license may be found at http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include - -#if STYX_A0 -#define END_PCI_BUS_NUMBER 15 -#else -#define END_PCI_BUS_NUMBER 255 -#endif - -#pragma pack(push, 1) - -typedef struct { - EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; - EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure; -} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; - -EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE AcpiMcfg = { - { AMD_ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, - EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), - EFI_ACPI_RESERVED_QWORD }, - { 0xF0000000ULL, 0, 0, END_PCI_BUS_NUMBER, EFI_ACPI_RESERVED_DWORD } -}; - -#pragma pack(pop) - -EFI_ACPI_DESCRIPTION_HEADER * -McfgHeader ( - VOID - ) -{ - return &AcpiMcfg.Header.Header; -} diff --git a/Silicon/AMD/Styx/AcpiTables/Pptt.c b/Silicon/AMD/Styx/AcpiTables/Pptt.c deleted file mode 100644 index 1746bbe8..00000000 --- a/Silicon/AMD/Styx/AcpiTables/Pptt.c +++ /dev/null @@ -1,225 +0,0 @@ -/** @file - - Copyright (c) 2018, Linaro Ltd. All rights reserved.
- - This program and the accompanying materials are licensed and made available - under the terms and conditions of the BSD License which accompanies this - distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include - -#include - -#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) - -#pragma pack(1) -typedef struct { - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; - UINT32 Offset[2]; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; -} STYX_PPTT_CORE; - -typedef struct { - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; - UINT32 Offset[1]; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; - STYX_PPTT_CORE Cores[2]; -} STYX_PPTT_CLUSTER; - -typedef struct { - EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; - UINT32 Offset[1]; - EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; - STYX_PPTT_CLUSTER Clusters[NUM_CORES / 2]; -} STYX_PPTT_PACKAGE; - -typedef struct { - EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; - STYX_PPTT_PACKAGE Packages[1]; -} STYX_PPTT_TABLE; -#pragma pack() - -#define PPTT_CORE(pid, cid, id) { \ - { \ - EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ - FIELD_OFFSET (STYX_PPTT_CORE, DCache), \ - {}, \ - { \ - 0, /* PhysicalPackage */ \ - EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ - }, \ - FIELD_OFFSET (STYX_PPTT_TABLE, \ - Packages[pid].Clusters[cid]), /* Parent */ \ - ((cid) << 8) + (id), /* AcpiProcessorId */ \ - 2, /* NumberOfPrivateResources */\ - }, { \ - FIELD_OFFSET (STYX_PPTT_TABLE, \ - Packages[pid].Clusters[cid].Cores[id].DCache), \ - FIELD_OFFSET (STYX_PPTT_TABLE, \ - Packages[pid].Clusters[cid].Cores[id].ICache), \ - }, { \ - EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ - {}, \ - { \ - 1, /* SizePropertyValid */ \ - 1, /* NumberOfSetsValid */ \ - 1, /* AssociativityValid */ \ - 0, /* AllocationTypeValid */ \ - 1, /* CacheTypeValid */ \ - 1, /* WritePolicyValid */ \ - 1, /* LineSizeValid */ \ - }, \ - 0, /* NextLevelOfCache */ \ - SIZE_32KB, /* Size */ \ - 256, /* NumberOfSets */ \ - 2, /* Associativity */ \ - { \ - 0, /* AllocationType */ \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ - }, \ - 64 /* LineSize */ \ - }, { \ - EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ - {}, \ - { \ - 1, /* SizePropertyValid */ \ - 1, /* NumberOfSetsValid */ \ - 1, /* AssociativityValid */ \ - 0, /* AllocationTypeValid */ \ - 1, /* CacheTypeValid */ \ - 1, /* WritePolicyValid */ \ - 1, /* LineSizeValid */ \ - }, \ - 0, /* NextLevelOfCache */ \ - 3 * SIZE_16KB,/* Size */ \ - 256, /* NumberOfSets */ \ - 3, /* Associativity */ \ - { \ - 0, /* AllocationType */ \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ - }, \ - 64 /* LineSize */ \ - } \ -} - -#define PPTT_CLUSTER(pid, cid) { \ - { \ - EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ - FIELD_OFFSET (STYX_PPTT_CLUSTER, L2Cache), \ - {}, \ - { \ - 0, /* PhysicalPackage */ \ - EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ - }, \ - FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid]), /* Parent */ \ - 0, /* AcpiProcessorId */ \ - 1, /* NumberOfPrivateResources */ \ - }, { \ - FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \ - }, { \ - EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ - {}, \ - { \ - 1, /* SizePropertyValid */ \ - 1, /* NumberOfSetsValid */ \ - 1, /* AssociativityValid */ \ - 0, /* AllocationTypeValid */ \ - 1, /* CacheTypeValid */ \ - 1, /* WritePolicyValid */ \ - 1, /* LineSizeValid */ \ - }, \ - 0, /* NextLevelOfCache */ \ - SIZE_1MB, /* Size */ \ - 1024, /* NumberOfSets */ \ - 16, /* Associativity */ \ - { \ - 0, /* AllocationType */ \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ - }, \ - 64 /* LineSize */ \ - }, { \ - PPTT_CORE(pid, cid, 0), \ - PPTT_CORE(pid, cid, 1), \ - } \ -} - -STATIC STYX_PPTT_TABLE mStyxPpttTable = { - { - AMD_ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - STYX_PPTT_TABLE, - EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), - }, - { - { - { - EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, - FIELD_OFFSET (STYX_PPTT_PACKAGE, L3Cache), - {}, - { - 1, /* PhysicalPackage */ - EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ - }, - 0, /* Parent */ - 0, /* AcpiProcessorId */ - 1, /* NumberOfPrivateResources */ - }, { - FIELD_OFFSET (STYX_PPTT_TABLE, Packages[0].L3Cache), - }, { - EFI_ACPI_6_2_PPTT_TYPE_CACHE, - sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), - {}, - { - 1, /* SizePropertyValid */ - 1, /* NumberOfSetsValid */ - 1, /* AssociativityValid */ - 0, /* AllocationTypeValid */ - 1, /* CacheTypeValid */ - 1, /* WritePolicyValid */ - 1, /* LineSizeValid */ - }, - 0, /* NextLevelOfCache */ - SIZE_8MB, /* Size */ - 8192, /* NumberOfSets */ - 16, /* Associativity */ - { - 0, /* AllocationType */ - EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, - EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, - }, - 64 /* LineSize */ - }, { - PPTT_CLUSTER (0, 0), -#if NUM_CORES > 3 - PPTT_CLUSTER (0, 1), -#if NUM_CORES > 5 - PPTT_CLUSTER (0, 2), -#if NUM_CORES > 7 - PPTT_CLUSTER (0, 3), -#endif -#endif -#endif - } - } - } -}; - -EFI_ACPI_DESCRIPTION_HEADER * -PpttHeader ( - VOID - ) -{ - return (EFI_ACPI_DESCRIPTION_HEADER *)&mStyxPpttTable.Pptt.Header; -} diff --git a/Silicon/AMD/Styx/AcpiTables/Spcr.c b/Silicon/AMD/Styx/AcpiTables/Spcr.c deleted file mode 100644 index 719c276c..00000000 --- a/Silicon/AMD/Styx/AcpiTables/Spcr.c +++ /dev/null @@ -1,124 +0,0 @@ -/** @file - - Serial Port Console Redirection Table - © 2000 - 2014 Microsoft Corporation. All rights reserved. - http://go.microsoft.com/fwlink/?linkid=403368 - - Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. - - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include - -#pragma pack(push, 1) - -#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011 3 - -STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE AcpiSpcr = { - // - // Header - // - AMD_ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, - 2), /* New MS definition for PL011 support */ - // - // InterfaceType - // - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011, - // - // Reserved[3] - // - {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, - // - // BaseAddress - // - AMD_GASN(FixedPcdGet64(PcdSerialRegisterBase)), - // - // InterruptType - // - 0, - // - // Irq - // - 0, - // - // GlobalSystemInterrupt - // - 0x148, - // - // BaudRate - // - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, - // - // Parity - // - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, - // - // StopBits - // - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, - // - // FlowControl - // - 0, - // - // TerminalType - // - EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, - // - // Language - // - EFI_ACPI_RESERVED_BYTE, - // - // PciDeviceId - // - 0xFFFF, - // - // PciVendorId - // - 0xFFFF, - // - // PciBusNumber - // - 0x00, - // - // PciDeviceNumber - // - 0x00, - // - // PciFunctionNumber - // - 0x00, - // - // PciFlags - // - 0, - // - // PciSegment - // - 0, - // - // Reserved2 - // - EFI_ACPI_RESERVED_DWORD -}; - -#pragma pack(pop) - -EFI_ACPI_DESCRIPTION_HEADER * -SpcrHeader ( - VOID - ) -{ - return &AcpiSpcr.Header; -} - diff --git a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h deleted file mode 100644 index 0dfd7635..00000000 --- a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @file - This library provides support for various platform-specific DXE drivers. - - Copyright (c) 2014 - 2015, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _AMDSTYX_ACPI_LIB_H_ -#define _AMDSTYX_ACPI_LIB_H_ - -#include - -EFI_ACPI_DESCRIPTION_HEADER *FadtTable (void); -EFI_ACPI_DESCRIPTION_HEADER *FacsTable (void); -EFI_ACPI_DESCRIPTION_HEADER *MadtHeader (void); -EFI_ACPI_DESCRIPTION_HEADER *GtdtHeader (void); -EFI_ACPI_DESCRIPTION_HEADER *McfgHeader (void); -EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); -EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); -EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void); -EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void); -EFI_ACPI_DESCRIPTION_HEADER *PpttHeader (void); - -#define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} -#define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') -#define EFI_ACPI_AMD_OEM_REVISION 0 -#define EFI_ACPI_AMD_CREATOR_ID SIGNATURE_32('A','M','D',' ') -#define EFI_ACPI_AMD_CREATOR_REVISION 0 - -/** - * A macro to initialize the common header part of EFI ACPI tables - * as defined by EFI_ACPI_DESCRIPTION_HEADER structure. - **/ -#define AMD_ACPI_HEADER(sign, type, rev) { \ - sign, /* UINT32 Signature */ \ - sizeof (type), /* UINT32 Length */ \ - rev, /* UINT8 Revision */ \ - 0, /* UINT8 Checksum */ \ - EFI_ACPI_AMD_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \ - EFI_ACPI_AMD_OEM_TABLE_ID, /* UINT64 OemTableId */ \ - EFI_ACPI_AMD_OEM_REVISION, /* UINT32 OemRevision */ \ - EFI_ACPI_AMD_CREATOR_ID, /* UINT32 CreatorId */ \ - EFI_ACPI_AMD_CREATOR_REVISION /* UINT32 CreatorRevision */ \ - } - -#define NULL_GAS {EFI_ACPI_5_1_SYSTEM_MEMORY, 0, 0, EFI_ACPI_5_1_UNDEFINED, 0L} -#define AMD_GAS8(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 8, 0, EFI_ACPI_5_1_BYTE, address} -#define AMD_GAS16(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 16, 0, EFI_ACPI_5_1_WORD, address} -#define AMD_GAS32(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_1_DWORD, address} -#define AMD_GAS64(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 64, 0, EFI_ACPI_5_1_QWORD, address} -#define AMD_GASN(address) AMD_GAS32(address) - -#endif // _AMDSTYX_ACPI_LIB_H_ - diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index a00bd3bd..ff132698 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -19,7 +19,6 @@ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatform.c **/ -#include #include #include @@ -31,12 +30,11 @@ #include #include +#include #include -#define MAX_ACPI_TABLES 16 - -EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES]; +#include "AcpiPlatform.h" STATIC EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol; @@ -97,16 +95,20 @@ InstallSystemDescriptionTables ( VOID ) { - EFI_ACPI_DESCRIPTION_HEADER *Table; - EFI_STATUS Status; - UINT32 CpuId; - UINTN Index; - UINTN TableSize; - UINTN TableHandle; + EFI_ACPI_DESCRIPTION_HEADER *Table; + EFI_STATUS Status; + UINT32 CpuId; + UINTN Index; + UINTN TableSize; + UINTN TableHandle; + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE *Gtdt; + EFI_ACPI_6_0_IO_REMAPPING_TABLE *Iort; #if DO_XGBE UINT8 MacPackage[sizeof(mDefaultMacPackageA)]; #endif + CpuId = PcdGet32 (PcdSocCpuId); + Status = EFI_SUCCESS; for (Index = 0; !EFI_ERROR (Status); Index++) { Status = GetSectionFromFv (&gEfiCallerIdGuid, EFI_SECTION_RAW, Index, @@ -117,7 +119,6 @@ InstallSystemDescriptionTables ( switch (Table->OemTableId) { case SIGNATURE_64 ('S', 't', 'y', 'x', 'B', '1', ' ', ' '): - CpuId = PcdGet32 (PcdSocCpuId); if ((CpuId & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) { continue; } @@ -141,11 +142,39 @@ InstallSystemDescriptionTables ( break; #endif continue; + + default: + switch (Table->Signature) { + case EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE: + if (!PcdGetBool (PcdEnableSmmus)) { + continue; + } + if ((CpuId & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) { + Iort = (EFI_ACPI_6_0_IO_REMAPPING_TABLE *)Table; + Iort->NumNodes -= 2; + } + break; + + case EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE: + if ((CpuId & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) { + Gtdt = (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE *)Table; + Gtdt->Header.Length = sizeof (*Gtdt); + Gtdt->PlatformTimerCount = 0; + Gtdt->PlatformTimerOffset = 0; + } + break; + } } Status = mAcpiTableProtocol->InstallAcpiTable (mAcpiTableProtocol, Table, - TableSize, &TableHandle); - ASSERT_EFI_ERROR (Status); + Table->Length, &TableHandle); + + DEBUG ((DEBUG_WARN, + "Installing %c%c%c%c Table (Revision %d, Length %d) ... %r\n", + ((UINT8 *)&Table->Signature)[0], ((UINT8 *)&Table->Signature)[1], + ((UINT8 *)&Table->Signature)[2], ((UINT8 *)&Table->Signature)[3], + Table->Revision, Table->Length, Status)); + FreePool (Table); } } @@ -168,67 +197,23 @@ AcpiPlatformEntryPoint ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; - UINTN TableHandle; - UINTN TableIndex; - - ZeroMem(AcpiTableList, sizeof(AcpiTableList)); - - TableIndex = 0; - AcpiTableList[TableIndex++] = FadtTable(); - AcpiTableList[TableIndex++] = MadtHeader(); - AcpiTableList[TableIndex++] = GtdtHeader(); - AcpiTableList[TableIndex++] = Dbg2Header(); - AcpiTableList[TableIndex++] = SpcrHeader(); - AcpiTableList[TableIndex++] = McfgHeader(); - AcpiTableList[TableIndex++] = CsrtHeader(); - if (PcdGetBool (PcdEnableSmmus)) { - AcpiTableList[TableIndex++] = IortHeader(); - } - AcpiTableList[TableIndex++] = PpttHeader(); - AcpiTableList[TableIndex++] = NULL; - - DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__)); + EFI_STATUS Status; + UINTN TableHandle; + EFI_ACPI_DESCRIPTION_HEADER *Header; // // Find the AcpiTable protocol // Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&mAcpiTableProtocol); - if (EFI_ERROR (Status)) { - DEBUG((EFI_D_ERROR, "Failed to locate AcpiTable protocol. Status = %r\n", Status)); - ASSERT_EFI_ERROR(Status); - } + ASSERT_EFI_ERROR (Status); - TableIndex = 0; - while (AcpiTableList[TableIndex] != NULL) { - // - // Install ACPI table - // - DEBUG ((EFI_D_ERROR, "Installing %c%c%c%c Table (Revision %d, Length %d) ...\n", - *((UINT8*)&AcpiTableList[TableIndex]->Signature), - *((UINT8*)&AcpiTableList[TableIndex]->Signature + 1), - *((UINT8*)&AcpiTableList[TableIndex]->Signature + 2), - *((UINT8*)&AcpiTableList[TableIndex]->Signature + 3), - AcpiTableList[TableIndex]->Revision, - AcpiTableList[TableIndex]->Length)); - - Status = mAcpiTableProtocol->InstallAcpiTable ( - mAcpiTableProtocol, - AcpiTableList[TableIndex], - (AcpiTableList[TableIndex])->Length, - &TableHandle - ); - if (EFI_ERROR (Status)) { - DEBUG((DEBUG_ERROR,"Error adding ACPI Table. Status = %r\n", Status)); - ASSERT_EFI_ERROR(Status); - } - TableIndex++; - ASSERT( TableIndex < MAX_ACPI_TABLES ); - } + Header = MadtHeader (); + Status = mAcpiTableProtocol->InstallAcpiTable (mAcpiTableProtocol, Header, + Header->Length, &TableHandle); + ASSERT_EFI_ERROR (Status); InstallSystemDescriptionTables (); - return EFI_SUCCESS; + return EFI_REQUEST_UNLOAD_IMAGE; } - diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.h b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.h new file mode 100644 index 00000000..b1864131 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.h @@ -0,0 +1,53 @@ +/** @file + This library provides support for various platform-specific DXE drivers. + + Copyright (c) 2014 - 2015, AMD Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _AMDSTYX_ACPI_LIB_H_ +#define _AMDSTYX_ACPI_LIB_H_ + +#include + +EFI_ACPI_DESCRIPTION_HEADER *MadtHeader (void); + +#define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} +#define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') +#define EFI_ACPI_AMD_OEM_REVISION 0 +#define EFI_ACPI_AMD_CREATOR_ID SIGNATURE_32('A','M','D',' ') +#define EFI_ACPI_AMD_CREATOR_REVISION 0 + +/** + * A macro to initialize the common header part of EFI ACPI tables + * as defined by EFI_ACPI_DESCRIPTION_HEADER structure. + **/ +#define AMD_ACPI_HEADER(sign, type, rev) { \ + sign, /* UINT32 Signature */ \ + sizeof (type), /* UINT32 Length */ \ + rev, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + EFI_ACPI_AMD_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \ + EFI_ACPI_AMD_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_AMD_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_AMD_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_AMD_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#define NULL_GAS {EFI_ACPI_5_1_SYSTEM_MEMORY, 0, 0, EFI_ACPI_5_1_UNDEFINED, 0L} +#define AMD_GAS8(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 8, 0, EFI_ACPI_5_1_BYTE, address} +#define AMD_GAS16(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 16, 0, EFI_ACPI_5_1_WORD, address} +#define AMD_GAS32(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_1_DWORD, address} +#define AMD_GAS64(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 64, 0, EFI_ACPI_5_1_QWORD, address} +#define AMD_GASN(address) AMD_GAS32(address) + +#endif // _AMDSTYX_ACPI_LIB_H_ + diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 92f185fa..95745db0 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -28,7 +28,16 @@ [Sources] AcpiPlatform.c + Csrt.aslc + Dbg2.aslc Dsdt.asl + Fadt.aslc + Gtdt.aslc + Iort.aslc + Madt.c + Mcfg.aslc + Pptt.aslc + Spcr.aslc SsdtB1.asl SsdtXgbe.asl @@ -40,7 +49,6 @@ Silicon/AMD/Styx/AmdStyx.dec [LibraryClasses] - AmdStyxAcpiLib BaseLib BaseMemoryLib DebugLib @@ -54,12 +62,33 @@ gAmdStyxTokenSpaceGuid.PcdEthMacA gAmdStyxTokenSpaceGuid.PcdEthMacB gAmdStyxTokenSpaceGuid.PcdEnableSmmus + gAmdStyxTokenSpaceGuid.PcdSocCoreCount gAmdStyxTokenSpaceGuid.PcdSocCpuId [FixedPcd] + gAmdStyxTokenSpaceGuid.PcdCntControlBase + gAmdStyxTokenSpaceGuid.PcdCntReadBase + gAmdStyxTokenSpaceGuid.PcdCntCTLBase + gAmdStyxTokenSpaceGuid.PcdCntBase0 + gAmdStyxTokenSpaceGuid.PcdCntEL0Base0 + gAmdStyxTokenSpaceGuid.PcdGicVersion + gAmdStyxTokenSpaceGuid.PcdGicHypervisorInterruptInterfaceBase + gAmdStyxTokenSpaceGuid.PcdGicVirtualInterruptInterfaceBase + gAmdStyxTokenSpaceGuid.PcdGicVirtualMaintenanceInterrupt + gAmdStyxTokenSpaceGuid.PcdGicVirtualRegisterInterfaceBase + gAmdStyxTokenSpaceGuid.PcdGicMSIFrameBase gAmdStyxTokenSpaceGuid.PcdSata1PortCount + gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogRefreshBase + gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogControlBase + gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV + gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV + gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase [Protocols] + gAmdMpCoreInfoProtocolGuid ## CONSUMED gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED [Depex] diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Csrt.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Csrt.aslc new file mode 100644 index 00000000..4aca9320 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Csrt.aslc @@ -0,0 +1,100 @@ +/** @file + + ACPI Memory mapped configuration space base address Description Table (MCFG). + Implementation based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. + + This program and the accompanying materials are licensed and + made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the + license may be found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "AcpiPlatform.h" + +// +// CSRT for ARM_CCN504 (L3 CACHE) +// +#define AMD_ACPI_ARM_CCN504_CSRT_REVISION 0 +#define AMD_ACPI_ARM_CCN504_VENDOR_ID SIGNATURE_32('A','R','M','H') +#define AMD_ACPI_ARM_CCN504_DEVICE_ID 0x510 +#define AMD_ACPI_ARM_CCN504_RESOURCE_TYPE 0x04 +#define AMD_ACPI_ARM_CCN504_DESC_VERSION 1 +#define AMD_ACPI_ARM_CCN504_HNF_COUNT 8 +#define AMD_ACPI_ARM_CCN504_BASE_ADDR 0xE8000000ULL +#define AMD_ACPI_ARM_CCN504_CACHE_SIZE 0x00800000ULL + +// +// Ensure proper (byte-packed) structure formats +// +#pragma pack(push, 1) + +typedef struct { + UINT32 Version; + UINT8 HnfRegionCount; + UINT8 Reserved[3]; + UINT64 BaseAddress; + UINT64 CacheSize; +} AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR; + +typedef struct { + UINT32 Length; + UINT16 ResourceType; + UINT16 ResourceSubtype; + UINT32 UID; + AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR Ccn504Desc; +} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR; + +typedef struct { + UINT32 Length; + UINT32 VendorId; + UINT32 SubvendorId; + UINT16 DeviceId; + UINT16 SubdeviceId; + UINT16 Revision; + UINT8 Reserved[2]; + UINT32 SharedInfoLength; + AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR RsrcDesc; +} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP; + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP RsrcGroup; +} AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE; + + +STATIC AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE AcpiCsrt = { + AMD_ACPI_HEADER (EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE, + AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE, + AMD_ACPI_ARM_CCN504_CSRT_REVISION), + { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP), // UINT32 RsrcGroup.Length + AMD_ACPI_ARM_CCN504_VENDOR_ID, // UINT32 RsrcGroup.VendorId + 0, // UINT32 RsrcGroup.SubvendorId + AMD_ACPI_ARM_CCN504_DEVICE_ID, // UINT16 RsrcGroup.DeviceId + 0, // UINT16 RsrcGroup.SubdeviceId + 0, // UINT16 RsrcGroup.Revision + { 0 }, // UINT8 RsrcGroup.Reserved[] + 0, // UINT32 RsrcGroup.SharedInfoLength + { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR), // UINT32 RsrcDesc.Length + AMD_ACPI_ARM_CCN504_RESOURCE_TYPE, // UINT16 RsrcDesc.ResourceType + 0, // UINT16 RsrcDesc.ResourceSubtype + 0, // UINT32 RsrcDesc.UID + { AMD_ACPI_ARM_CCN504_DESC_VERSION, // UINT32 Ccn504Desc.Version + AMD_ACPI_ARM_CCN504_HNF_COUNT, // UINT8 Ccn504Desc.HnfRegionCount + { 0 }, // UINT8 Ccn504Desc.Reserved[] + AMD_ACPI_ARM_CCN504_BASE_ADDR, // UINT64 Ccn504Desc.BaseAddress + AMD_ACPI_ARM_CCN504_CACHE_SIZE, // UINT64 Ccn504Desc.CacheSize + }, + }, + }, +}; + +#pragma pack(pop) + +VOID* CONST ReferenceAcpiTable = &AcpiCsrt; diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dbg2.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dbg2.aslc new file mode 100644 index 00000000..07635aa9 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dbg2.aslc @@ -0,0 +1,108 @@ +/** @file + + Microsoft Debug Port Table 2 (DBG2) + © 2012 Microsoft. All rights reserved.
+ http://go.microsoft.com/fwlink/p/?linkid=403551 + + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include "AcpiPlatform.h" + +#pragma pack(push, 1) + +#define EFI_ACPI_DBG2_REVISION 0 +#define DBG2_NUM_DEBUG_PORTS 1 +#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1 +#define DBG2_NAMESPACESTRING_FIELD_SIZE 8 +#define DBG2_OEM_DATA_FIELD_SIZE 0 +#define DBG2_OEM_DATA_FIELD_OFFSET 0 + +#define DBG2_DEBUG_PORT_SUBTYPE_PL011 0x0003 // Sub type for Pl011 +#define DBG2_DEBUG_PORT_SUBTYPE_UEFI 0x0007 // Sub type for UEFI Debug Port +#define PL011_UART_LENGTH 0x1000 + +#define NAME_STR_UART1 {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'} +#define NAME_STR_UEFI {'U', 'E', 'F', 'I', '\0', '\0', '\0', '\0'} + + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS]; +} DBG2_TABLE; + + +#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \ + { \ + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision; */ \ + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length; */ \ + NumReg, /* UINT8 NumberofGenericAddressRegisters; */ \ + DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength; */ \ + OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset; */ \ + DBG2_OEM_DATA_FIELD_SIZE, /* UINT16 OemDataLength; */ \ + DBG2_OEM_DATA_FIELD_OFFSET, /* UINT16 OemDataOffset; */ \ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type; */ \ + SubType, /* UINT16 Port Subtype; */ \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2]; */ \ + OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset; */ \ + OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset; */ \ + }, \ + AMD_GASN (UartBase), /* EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \ + UartAddrLen, /* UINT32 AddressSize */ \ + UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \ + } + + +STATIC DBG2_TABLE AcpiDbg2 = { + { + AMD_ACPI_HEADER (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_REVISION), + OFFSET_OF(DBG2_TABLE, Dbg2DeviceInfo), + DBG2_NUM_DEBUG_PORTS // UINT32 NumberDbgDeviceInfo + }, + { + /* + * Kernel Debug Port + */ +#if (DBG2_NUM_DEBUG_PORTS > 0) + DBG2_DEBUG_PORT_DDI(DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS, + DBG2_DEBUG_PORT_SUBTYPE_PL011, + FixedPcdGet64(PcdSerialDbgRegisterBase), + PL011_UART_LENGTH, + NAME_STR_UART1), +#endif + /* + * UEFI Debug Port + */ +#if (DBG2_NUM_DEBUG_PORTS > 1) + DBG2_DEBUG_PORT_DDI(0, + DBG2_DEBUG_PORT_SUBTYPE_UEFI, + 0, + 0, + NAME_STR_UEFI), +#endif + } +}; + +#pragma pack(pop) + +VOID* CONST ReferenceAcpiTable = &AcpiDbg2; diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Fadt.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Fadt.aslc new file mode 100644 index 00000000..35d190bd --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Fadt.aslc @@ -0,0 +1,94 @@ +/** @file + + Fixed ACPI Description Table (FADT) + + Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +/** + + Derived from: + ArmPlatformPkg/ArmJunoPkg/AcpiTables/Fadt.aslc + +**/ + +#include "AcpiPlatform.h" + +#define FADT_FLAGS ( EFI_ACPI_5_1_HW_REDUCED_ACPI | \ + EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE | \ + EFI_ACPI_5_1_HEADLESS ) + +#pragma pack(push, 1) + +STATIC EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = { + AMD_ACPI_HEADER (EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + FADT_FLAGS, // UINT32 Flags + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch + 1, // UINT8 MinorVersion + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg +}; + +#pragma pack(pop) + +VOID* CONST ReferenceAcpiTable = &AcpiFadt; diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Gtdt.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Gtdt.aslc new file mode 100644 index 00000000..34f92f2e --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Gtdt.aslc @@ -0,0 +1,173 @@ +/** @file + + Generic Timer Description Table (GTDT) + + Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +/** + + Derived from: + ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc + +**/ + +#include "AcpiPlatform.h" + +#pragma pack(push, 1) + +#define CNT_CONTROL_BASE_ADDRESS FixedPcdGet64(PcdCntControlBase) +#define CNT_READ_BASE_ADDRESS FixedPcdGet64(PcdCntReadBase) +#define CNT_CTL_BASE_ADDRESS FixedPcdGet64(PcdCntCTLBase) +#define CNT_BASE0_ADDRESS FixedPcdGet64(PcdCntBase0) +#define CNT_EL0_BASE0_ADDRESS FixedPcdGet64(PcdCntEL0Base0) +#define SBSA_WATCHDOG_REFRESH_BASE FixedPcdGet64(PcdSbsaWatchDogRefreshBase) +#define SBSA_WATCHDOG_CONTROL_BASE FixedPcdGet64(PcdSbsaWatchDogControlBase) +#define SBSA_WAKEUP_GSIV FixedPcdGet64(PcdSbsaWakeUpGSIV) +#define SBSA_WATCHDOG_GSIV FixedPcdGet64(PcdSbsaWatchDogGSIV) + + +/* + * Section 8.2.3 of Cortex-A15 r2p1 TRM + */ +#define CP15_TIMER_SEC_INTR 29 +#define CP15_TIMER_NS_INTR 30 +#define CP15_TIMER_VIRT_INTR 27 +#define CP15_TIMER_NSHYP_INTR 26 + +/* SBSA Timers */ + #define PLATFORM_TIMER_COUNT 2 + #define PLATFORM_TIMER_OFFSET sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) + +/* +// GTDT Table timer flags. + +Bit 0: Timer interrupt Mode + This bit indicates the mode of the timer interrupt + 1: Interrupt is Edge triggered + 0: Interrupt is Level triggered +Timer Interrupt polarity + This bit indicates the polarity of the timer interrupt + 1: Interrupt is Active low + 0: Interrupt is Active high +Reserved 2 30 Reserved, must be zero. + +From A15 TRM: + 9.2 Generic Timer functional description + ... + Each timer provides an active-LOW interrupt output that is an external pin to the SoC and is + sent to the GIC as a Private Peripheral Interrupt (PPI). See Interrupt sources on page 8-4 for + the ID and PPI allocation of the Timer interrupts. + PPI6 Virtual Maintenance Interrupt. + PPI5 Hypervisor timer event. + PPI4 Virtual timer event. + PPI3 nIRQ. + PPI2 Non-secure physical timer event. + PPI1 Secure physical timer event. + PPI0-5 Active-LOW level-sensitive. + PPI6 Active-HIGH level-sensitive.*/ + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_SECURE EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY +#define GTDT_TIMER_NON_SECURE 0 +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_NON_SECURE | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTX_TIMER_LEVEL_TRIGGERED 0 +#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTX_TIMER_ACTIVE_HIGH 0 +#define GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_SECURE EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_LOSE_CONTEXT 0 +#define GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE) + +#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE +#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 +#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY +#define SBSA_WATCHDOG_ACTIVE_HIGH 0 +#define SBSA_WATCHDOG_SECURE EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER +#define SBSA_WATCHDOG_NON_SECURE 0 +#define SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED) + + +#define AMD_SBSA_GTX { \ + EFI_ACPI_5_1_GTDT_GT_BLOCK, /* UINT8 Type */ \ + sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) + \ + sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), /* UINT16 Length */ \ + EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \ + CNT_CTL_BASE_ADDRESS, /* UINT64 CntCtlBase */ \ + 1, /* UINT32 GTBlockTimerCount */ \ + sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) /* UINT32 GTBlockTimerOffset */ \ + } + +#define AMD_SBSA_GTX_TIMER { \ + 0, /* UINT8 GTFrameNumber */ \ + {0, 0, 0}, /* UINT8 Reserved[3] */ \ + CNT_BASE0_ADDRESS, /* UINT64 CntBaseX */ \ + CNT_EL0_BASE0_ADDRESS, /* UINT64 CntEL0BaseX */ \ + SBSA_WAKEUP_GSIV, /* UINT32 GTxPhysicalTimerGSIV */ \ + GTX_TIMER_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \ + 0, /* UINT32 GTxVirtualTimerGSIV */ \ + GTX_TIMER_FLAGS, /* UINT32 GTxVirtualTimerFlags */ \ + GTX_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \ + } + +#define AMD_SBSA_WATCHDOG { \ + EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG, /* UINT8 Type */ \ + sizeof (EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), /* UINT16 Length */ \ + EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \ + SBSA_WATCHDOG_REFRESH_BASE, /* UINT64 RefreshFramePhysicalAddress */ \ + SBSA_WATCHDOG_CONTROL_BASE, /* UINT64 WatchdogControlFramePhysicalAddress */ \ + SBSA_WATCHDOG_GSIV, /* UINT32 WatchdogTimerGSIV */ \ + SBSA_WATCHDOG_FLAGS /* UINT32 WatchdogTimerFlags */ \ + } + +typedef struct { + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE GTxBlock; + EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE GTxTimer; + EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE WatchDog; +} AMD_ACPI_5_1_ARM_GTDT_STRUCTURE; + +STATIC AMD_ACPI_5_1_ARM_GTDT_STRUCTURE AcpiGtdt = { + { + AMD_ACPI_HEADER(EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + AMD_ACPI_5_1_ARM_GTDT_STRUCTURE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION), + CNT_CONTROL_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + CP15_TIMER_SEC_INTR, // UINT32 SecureEL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecureEL1TimerFlags + CP15_TIMER_NS_INTR, // UINT32 NonSecureEL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL1TimerFlags + CP15_TIMER_VIRT_INTR, // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + CP15_TIMER_NSHYP_INTR, // UINT32 NonSecureEL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL2TimerFlags + CNT_READ_BASE_ADDRESS, // UINT64 CntReadBaseAddress + PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount + PLATFORM_TIMER_OFFSET // UINT32 PlatformTimerOffset + }, + AMD_SBSA_GTX, + AMD_SBSA_GTX_TIMER, + AMD_SBSA_WATCHDOG, +}; + +#pragma pack(pop) + +VOID* CONST ReferenceAcpiTable = &AcpiGtdt; diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Iort.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Iort.aslc new file mode 100644 index 00000000..7723a4dd --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Iort.aslc @@ -0,0 +1,358 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include "AcpiPlatform.h" + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#define STYX_PCIE_SMMU_BASE 0xE0A00000 +#define STYX_PCIE_SMMU_SIZE 0x10000 +#define STYX_PCIE_SMMU_INTERRUPT 0x16d + +#define STYX_ETH0_SMMU_BASE 0xE0600000 +#define STYX_ETH0_SMMU_SIZE 0x10000 +#define STYX_ETH0_SMMU_INTERRUPT 0x170 + +#define STYX_ETH1_SMMU_BASE 0xE0800000 +#define STYX_ETH1_SMMU_SIZE 0x10000 +#define STYX_ETH1_SMMU_INTERRUPT 0x16f + +#define STYX_SATA0_SMMU_BASE 0xE0200000 +#define STYX_SATA0_SMMU_SIZE 0x10000 +#define STYX_SATA0_SMMU_INTERRUPT 0x16c + +#define STYX_SATA1_SMMU_BASE 0xE0C00000 +#define STYX_SATA1_SMMU_SIZE 0x10000 +#define STYX_SATA1_SMMU_INTERRUPT 0x16b + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[1]; +} STYX_SMMU_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1]; +} STYX_RC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; + CONST CHAR8 Name[11]; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[32]; +} STYX_NC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + STYX_SMMU_NODE PciSmmuNode; + STYX_RC_NODE PciRcNode; + +#if DO_XGBE + STYX_SMMU_NODE Eth0SmmuNode; + STYX_NC_NODE Eth0NamedNode; + STYX_SMMU_NODE Eth1SmmuNode; + STYX_NC_NODE Eth1NamedNode; +#endif + + STYX_SMMU_NODE Sata0SmmuNode; + STYX_NC_NODE Sata0NamedNode; + STYX_SMMU_NODE Sata1SmmuNode; + STYX_NC_NODE Sata1NamedNode; +} STYX_IO_REMAPPING_STRUCTURE; + +#define __STYX_SMMU_NODE(Base, Size, Irq) \ + { \ + { \ + EFI_ACPI_IORT_TYPE_SMMUv1v2, \ + sizeof(STYX_SMMU_NODE), \ + 0x0, \ + 0x0, \ + 0x0, \ + 0x0, \ + }, \ + Base, \ + Size, \ + EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401, \ + EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \ + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \ + SMMU_NSgIrpt), \ + 0x1, \ + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \ + 0x0, \ + 0x0, \ + Irq, \ + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ + 0x0, \ + 0x0, \ + }, { \ + { \ + Irq, \ + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \ + }, \ + } + +#define __STYX_ID_MAPPING(In, Num, Out, Ref, Flags) \ + { \ + In, \ + Num, \ + Out, \ + FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \ + Flags \ + } + +#define __STYX_ID_MAPPING_SINGLE(Out, Ref) \ + { \ + 0x0, \ + 0x0, \ + Out, \ + FIELD_OFFSET(STYX_IO_REMAPPING_STRUCTURE, Ref), \ + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE \ + } + +#define __STYX_NAMED_COMPONENT_NODE(Name) \ + { \ + { \ + EFI_ACPI_IORT_TYPE_NAMED_COMP, \ + sizeof(STYX_NC_NODE), \ + 0x0, \ + 0x0, \ + 0x20, \ + FIELD_OFFSET(STYX_NC_NODE, RcIdMapping), \ + }, \ + 0x0, \ + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, \ + 0x0, \ + 0x0, \ + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | \ + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, \ + 40, \ + }, \ + Name + +STATIC STYX_IO_REMAPPING_STRUCTURE AcpiIort = { + { + AMD_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + STYX_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), +#if DO_XGBE + 10, // NumNodes +#else + 6, // NumNodes +#endif + sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, { + // PciSmmuNode + __STYX_SMMU_NODE(STYX_PCIE_SMMU_BASE, + STYX_PCIE_SMMU_SIZE, + STYX_PCIE_SMMU_INTERRUPT) + }, { + // PciRcNode + { + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof(STYX_RC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x1, // NumIdMappings + FIELD_OFFSET(STYX_RC_NODE, RcIdMapping), // IdReference + }, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute + 0x0, // PciSegmentNumber + }, { + __STYX_ID_MAPPING(0x0, 0xffff, 0x0, PciSmmuNode, 0x0), + } +#if DO_XGBE + }, { + // Eth0SmmuNode + __STYX_SMMU_NODE(STYX_ETH0_SMMU_BASE, + STYX_ETH0_SMMU_SIZE, + STYX_ETH0_SMMU_INTERRUPT) + }, { + // Eth0NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH0"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Eth0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Eth0SmmuNode), + } + }, { + // Eth1SmmuNode + __STYX_SMMU_NODE(STYX_ETH1_SMMU_BASE, + STYX_ETH1_SMMU_SIZE, + STYX_ETH1_SMMU_INTERRUPT) + }, { + // Eth1NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.ETH1"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Eth1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Eth1SmmuNode), + } +#endif + }, { + // Sata0SmmuNode + __STYX_SMMU_NODE(STYX_SATA0_SMMU_BASE, + STYX_SATA0_SMMU_SIZE, + STYX_SATA0_SMMU_INTERRUPT) + }, { + // Sata0NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC0"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Sata0SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Sata0SmmuNode), + } + }, { + // Sata1SmmuNode + __STYX_SMMU_NODE(STYX_SATA1_SMMU_BASE, + STYX_SATA1_SMMU_SIZE, + STYX_SATA1_SMMU_INTERRUPT) + }, { + // Sata1NamedNode + __STYX_NAMED_COMPONENT_NODE("\\_SB_.AHC1"), + { + __STYX_ID_MAPPING_SINGLE(0x00, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x01, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x02, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x03, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x04, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x05, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x06, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x07, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x08, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x09, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0A, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0B, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0C, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0D, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0E, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x0F, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x10, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x11, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x12, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x13, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x14, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x15, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x16, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x17, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x18, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x19, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1A, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1B, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1C, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1D, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1E, Sata1SmmuNode), + __STYX_ID_MAPPING_SINGLE(0x1F, Sata1SmmuNode), + } + } +}; + +#pragma pack() + +VOID* CONST ReferenceAcpiTable = &AcpiIort; diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Madt.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Madt.c new file mode 100644 index 00000000..b10ae7e1 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Madt.c @@ -0,0 +1,319 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +/** + + Derived from: + ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc + +**/ + +#include +#include +#include +#include +#include + +#include + +#include "AcpiPlatform.h" + +AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL; + + +// ARM PL390 General Interrupt Controller +#define GIC_BASE (FixedPcdGet64 (PcdGicInterruptInterfaceBase)) +#define GICD_BASE (FixedPcdGet64 (PcdGicDistributorBase)) +#define GICV_BASE (FixedPcdGet64 (PcdGicVirtualInterruptInterfaceBase)) +#define GICH_BASE (FixedPcdGet64 (PcdGicHypervisorInterruptInterfaceBase)) +#define VGIC_MAINT_INT (FixedPcdGet32 (PcdGicVirtualMaintenanceInterrupt)) +#define GICVR_BASE (FixedPcdGet64 (PcdGicVirtualRegisterInterfaceBase)) +#define GIC_MSI_FRAME (FixedPcdGet64 (PcdGicMSIFrameBase)) +#define GIC_VERSION (FixedPcdGet8 (PcdGicVersion)) + +#define GICD_ID ( 0 ) +#define GICD_VECTOR ( 0 ) + +#define GICM_ID ( 0 ) +#define GICM_SPI_COUNT ( 0x100 ) +#define GICM_SPI_BASE ( 0x40 ) +#define GSIV_SPI_OFFSET ( 32 ) + +#if STYX_A0 + #define MSI_TYPER_FLAG ( 1 ) // Ignore TYPER register and use Count/Base fields +#else + #define MSI_TYPER_FLAG ( 0 ) // Use TYPER register and ignore Count/Base fields +#endif + +#define CORES_PER_CLUSTER (FixedPcdGet32 (PcdSocCoresPerCluster)) + + +/* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */ +#define AMD_GIC(CpuNum, ClusterId, CoreId, PerfInt) { \ + EFI_ACPI_5_1_GIC, /* UINT8 Type */ \ + sizeof (EFI_ACPI_5_1_GIC_STRUCTURE), /* UINT8 Length */ \ + EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved */ \ + CpuNum, /* UINT32 CPUInterfaceNumber */ \ + (ClusterId << 8) | CoreId, /* UINT32 AcpiProcessorUid */ \ + EFI_ACPI_5_1_GIC_ENABLED, /* UINT32 Flags */ \ + 0, /* UINT32 ParkingProtocolVersion */ \ + PerfInt, /* UINT32 PerformanceInterruptGsiv */ \ + 0, /* UINT64 ParkedAddress */ \ + GIC_BASE, /* UINT64 PhysicalBaseAddress */ \ + GICV_BASE, /* UINT64 GICV */ \ + GICH_BASE, /* UINT64 GICH */ \ + VGIC_MAINT_INT, /* UINT32 VGICMaintenanceInterrupt */ \ + GICVR_BASE, /* UINT64 GICRBaseAddress */ \ + (ClusterId << 8) | CoreId /* UINT64 MPIDR */ \ + } + +/* Macro to initialise EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE */ +#define AMD_GICD(Id, Vec) { \ + EFI_ACPI_5_1_GICD, /* UINT8 Type */ \ + sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE), /* UINT8 Length */ \ + EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \ + Id, /* UINT32 GicId */ \ + GICD_BASE, /* UINT64 PhysicalBaseAddress */ \ + Vec, /* UINT32 SystemVectorBase */ \ + EFI_ACPI_RESERVED_DWORD /* UINT32 Reserved2 */ \ + } + +/* Macro to initialise EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE */ +#define AMD_GICM(Id, SpiCount, SpiBase) { \ + EFI_ACPI_5_1_GIC_MSI_FRAME, /* UINT8 Type */ \ + sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE), /* UINT8 Length */ \ + EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \ + Id, /* UINT32 GicMsiFrameId */ \ + GIC_MSI_FRAME, /* UINT64 PhysicalBaseAddress */ \ + MSI_TYPER_FLAG, /* UINT32 Flags */ \ + SpiCount, /* UINT16 SPICount */ \ + SpiBase /* UINT16 SPIBase */ \ + } + + +// +// NOTE: NUM_CORES is a pre-processor macro passed in with -D option +// +#pragma pack(push, 1) +typedef struct { + EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_5_1_GIC_STRUCTURE GicC[NUM_CORES]; + EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE GicD; + EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE GicM; +} EFI_ACPI_5_1_ARM_MADT_STRUCTURE; +#pragma pack(pop) + + +STATIC EFI_ACPI_5_1_ARM_MADT_STRUCTURE AcpiMadt = { + { + AMD_ACPI_HEADER (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_1_ARM_MADT_STRUCTURE, + EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), + GIC_BASE, // UINT32 LocalApicAddress + 0 // UINT32 Flags + }, + { + /* + * GIC Interface for Cluster 0 CPU 0 + */ + AMD_GIC(0, 0, 0, 39), // EFI_ACPI_5_1_GIC_STRUCTURE +#if (NUM_CORES > 1) + /* + * GIC Interface for Cluster 0 CPU 1 + */ + AMD_GIC(1, 0, 1, 40), // EFI_ACPI_5_1_GIC_STRUCTURE +#endif +#if (NUM_CORES > 2) + /* + * GIC Interface for Cluster 1 CPU 0 + */ + AMD_GIC(2, 1, 0, 41), // EFI_ACPI_5_1_GIC_STRUCTURE +#endif +#if (NUM_CORES > 3) + /* + * GIC Interface for Cluster 1 CPU 1 + */ + AMD_GIC(3, 1, 1, 42), // EFI_ACPI_5_1_GIC_STRUCTURE +#endif +#if (NUM_CORES > 4) + /* + * GIC Interface for Cluster 2 CPU 0 + */ + AMD_GIC(4, 2, 0, 43), // EFI_ACPI_5_1_GIC_STRUCTURE +#endif +#if (NUM_CORES > 5) + /* + * GIC Interface for Cluster 2 CPU 1 + */ + AMD_GIC(5, 2, 1, 44), // EFI_ACPI_5_1_GIC_STRUCTURE +#endif +#if (NUM_CORES > 6) + /* + * GIC Interface for Cluster 3 CPU 0 + */ + AMD_GIC(6, 3, 0, 45), // EFI_ACPI_5_1_GIC_STRUCTURE +#endif +#if (NUM_CORES > 7) + /* + * GIC Interface for Cluster 3 CPU 1 + */ + AMD_GIC(7, 3, 1, 46), // EFI_ACPI_5_1_GIC_STRUCTURE +#endif + }, + /* + * GIC Distributor + */ + AMD_GICD(GICD_ID, GICD_VECTOR), // EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE + /* + * GIC MSI Frame + */ + AMD_GICM(GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE), +}; + + +STATIC +EFI_STATUS +BuildGicC ( + EFI_ACPI_5_1_GIC_STRUCTURE *GicC, + UINT32 CpuNum, + UINT32 ClusterId, + UINT32 CoreId + ) +{ + UINT32 MpId, PmuSpi; + EFI_STATUS Status; + + MpId = (UINT32) GET_MPID (ClusterId, CoreId); + Status = mAmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuSpi); + if (EFI_ERROR (Status)) + return Status; + + GicC->Type = EFI_ACPI_5_1_GIC; + GicC->Length = sizeof (EFI_ACPI_5_1_GIC_STRUCTURE); + GicC->Reserved = EFI_ACPI_RESERVED_WORD; + GicC->CPUInterfaceNumber = CpuNum; + GicC->AcpiProcessorUid = MpId; + GicC->Flags = EFI_ACPI_5_1_GIC_ENABLED; + GicC->PhysicalBaseAddress = GIC_BASE; + GicC->GICV = GICV_BASE; + GicC->GICH = GICH_BASE; + GicC->VGICMaintenanceInterrupt = VGIC_MAINT_INT; + GicC->GICRBaseAddress = GICVR_BASE; + GicC->PerformanceInterruptGsiv = PmuSpi + GSIV_SPI_OFFSET; + GicC->MPIDR = MpId; + + return EFI_SUCCESS; +} + +STATIC +VOID +BuildGicD ( + EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD, + UINT32 GicId, + UINT32 SystemVectorBase + ) +{ + GicD->Type = EFI_ACPI_5_1_GICD; + GicD->Length = sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE); + GicD->Reserved1 = EFI_ACPI_RESERVED_WORD; + GicD->GicId = GicId; + GicD->PhysicalBaseAddress = GICD_BASE; + GicD->SystemVectorBase = SystemVectorBase; +#if 0 + GicD->Reserved2 = EFI_ACPI_RESERVED_DWORD; +#else + GicD->GicVersion = EFI_ACPI_RESERVED_BYTE; + GicD->Reserved2[0] = EFI_ACPI_RESERVED_BYTE; + GicD->Reserved2[1] = EFI_ACPI_RESERVED_BYTE; + GicD->Reserved2[2] = EFI_ACPI_RESERVED_BYTE; +#endif +} + + +STATIC +VOID +BuildGicM ( + EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM, + UINT32 MsiFrameId, + UINT16 SpiCount, + UINT16 SpiBase + ) +{ + GicM->Type = EFI_ACPI_5_1_GIC_MSI_FRAME; + GicM->Length = sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE); + GicM->Reserved1 = EFI_ACPI_RESERVED_WORD; + GicM->GicMsiFrameId = MsiFrameId; + GicM->PhysicalBaseAddress = GIC_MSI_FRAME; + GicM->Flags = MSI_TYPER_FLAG; + GicM->SPICount = SpiCount; + GicM->SPIBase = SpiBase; +} + + +EFI_ACPI_DESCRIPTION_HEADER * +MadtHeader ( + VOID + ) +{ + EFI_ACPI_5_1_GIC_STRUCTURE *GicC; + EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD; + EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM; + ARM_CORE_INFO *ArmCoreInfoTable; + UINTN CoreCount, CpuNum; + EFI_STATUS Status; + + Status = gBS->LocateProtocol ( + &gAmdMpCoreInfoProtocolGuid, + NULL, + (VOID **)&mAmdMpCoreInfoProtocol + ); + ASSERT_EFI_ERROR (Status); + + // Get pointer to ARM core info table + ArmCoreInfoTable = mAmdMpCoreInfoProtocol->GetArmCoreInfoTable (&CoreCount); + ASSERT (ArmCoreInfoTable != NULL); + + // Make sure SoC's core count does not exceed what we want to build + ASSERT (CoreCount <= NUM_CORES); + ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount)); + + GicC = (EFI_ACPI_5_1_GIC_STRUCTURE *)&AcpiMadt.GicC[0]; + AcpiMadt.Header.Header.Length = sizeof (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); + + for (CpuNum = 0; CpuNum < CoreCount; ++CpuNum, ++GicC) { + DEBUG ((EFI_D_ERROR, "MADT: Core[%d]: ClusterId = %d CoreId = %d\n", + CpuNum, ArmCoreInfoTable[CpuNum].ClusterId, ArmCoreInfoTable[CpuNum].CoreId)); + + Status = BuildGicC (GicC, CpuNum, + ArmCoreInfoTable[CpuNum].ClusterId, + ArmCoreInfoTable[CpuNum].CoreId + ); + ASSERT_EFI_ERROR (Status); + + AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_STRUCTURE); + } + + GicD = (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length); + BuildGicD (GicD, GICD_ID, GICD_VECTOR); + AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE); + + GicM = (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length); + BuildGicM (GicM, GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE); + AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE); + + return &AcpiMadt.Header.Header; +} + diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Mcfg.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Mcfg.aslc new file mode 100644 index 00000000..67fb0429 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Mcfg.aslc @@ -0,0 +1,46 @@ +/** @file + + ACPI Memory mapped configuration space base address Description Table (MCFG). + Implementation based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. + + This program and the accompanying materials are licensed and + made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the + license may be found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include "AcpiPlatform.h" + +#if STYX_A0 +#define END_PCI_BUS_NUMBER 15 +#else +#define END_PCI_BUS_NUMBER 255 +#endif + +#pragma pack(push, 1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; + +STATIC EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE AcpiMcfg = { + { AMD_ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), + EFI_ACPI_RESERVED_QWORD }, + { 0xF0000000ULL, 0, 0, END_PCI_BUS_NUMBER, EFI_ACPI_RESERVED_DWORD } +}; + +#pragma pack(pop) + +VOID* CONST ReferenceAcpiTable = &AcpiMcfg; diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc new file mode 100644 index 00000000..64a6cda7 --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc @@ -0,0 +1,219 @@ +/** @file + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include "AcpiPlatform.h" + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} STYX_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + STYX_PPTT_CORE Cores[2]; +} STYX_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + STYX_PPTT_CLUSTER Clusters[NUM_CORES / 2]; +} STYX_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + STYX_PPTT_PACKAGE Packages[1]; +} STYX_PPTT_TABLE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (STYX_PPTT_CORE, DCache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (STYX_PPTT_TABLE, \ + Packages[pid].Clusters[cid]), /* Parent */ \ + ((cid) << 8) + (id), /* AcpiProcessorId */ \ + 2, /* NumberOfPrivateResources */\ + }, { \ + FIELD_OFFSET (STYX_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].DCache), \ + FIELD_OFFSET (STYX_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].ICache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_32KB, /* Size */ \ + 256, /* NumberOfSets */ \ + 2, /* Associativity */ \ + { \ + 0, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + 3 * SIZE_16KB,/* Size */ \ + 256, /* NumberOfSets */ \ + 3, /* Associativity */ \ + { \ + 0, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + } \ +} + +#define PPTT_CLUSTER(pid, cid) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (STYX_PPTT_CLUSTER, L2Cache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid]), /* Parent */ \ + 0, /* AcpiProcessorId */ \ + 1, /* NumberOfPrivateResources */ \ + }, { \ + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_1MB, /* Size */ \ + 1024, /* NumberOfSets */ \ + 16, /* Associativity */ \ + { \ + 0, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + PPTT_CORE(pid, cid, 0), \ + PPTT_CORE(pid, cid, 1), \ + } \ +} + +STATIC STYX_PPTT_TABLE mStyxPpttTable = { + { + AMD_ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + STYX_PPTT_TABLE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), + }, + { + { + { + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, + FIELD_OFFSET (STYX_PPTT_PACKAGE, L3Cache), + {}, + { + 1, /* PhysicalPackage */ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ + }, + 0, /* Parent */ + 0, /* AcpiProcessorId */ + 1, /* NumberOfPrivateResources */ + }, { + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[0].L3Cache), + }, { + EFI_ACPI_6_2_PPTT_TYPE_CACHE, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), + {}, + { + 1, /* SizePropertyValid */ + 1, /* NumberOfSetsValid */ + 1, /* AssociativityValid */ + 0, /* AllocationTypeValid */ + 1, /* CacheTypeValid */ + 1, /* WritePolicyValid */ + 1, /* LineSizeValid */ + }, + 0, /* NextLevelOfCache */ + SIZE_8MB, /* Size */ + 8192, /* NumberOfSets */ + 16, /* Associativity */ + { + 0, /* AllocationType */ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, + }, + 64 /* LineSize */ + }, { + PPTT_CLUSTER (0, 0), +#if NUM_CORES > 3 + PPTT_CLUSTER (0, 1), +#if NUM_CORES > 5 + PPTT_CLUSTER (0, 2), +#if NUM_CORES > 7 + PPTT_CLUSTER (0, 3), +#endif +#endif +#endif + } + } + } +}; + +VOID* CONST ReferenceAcpiTable = &mStyxPpttTable; diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Spcr.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Spcr.aslc new file mode 100644 index 00000000..bd84a19c --- /dev/null +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Spcr.aslc @@ -0,0 +1,118 @@ +/** @file + + Serial Port Console Redirection Table + © 2000 - 2014 Microsoft Corporation. All rights reserved. + http://go.microsoft.com/fwlink/?linkid=403368 + + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include "AcpiPlatform.h" + +#pragma pack(push, 1) + +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011 3 + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE AcpiSpcr = { + // + // Header + // + AMD_ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + 2), /* New MS definition for PL011 support */ + // + // InterfaceType + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011, + // + // Reserved[3] + // + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + // + // BaseAddress + // + AMD_GASN(FixedPcdGet64(PcdSerialRegisterBase)), + // + // InterruptType + // + 0, + // + // Irq + // + 0, + // + // GlobalSystemInterrupt + // + 0x148, + // + // BaudRate + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + // + // Parity + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // + // StopBits + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // + // FlowControl + // + 0, + // + // TerminalType + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + // + // Language + // + EFI_ACPI_RESERVED_BYTE, + // + // PciDeviceId + // + 0xFFFF, + // + // PciVendorId + // + 0xFFFF, + // + // PciBusNumber + // + 0x00, + // + // PciDeviceNumber + // + 0x00, + // + // PciFunctionNumber + // + 0x00, + // + // PciFlags + // + 0, + // + // PciSegment + // + 0, + // + // Reserved2 + // + EFI_ACPI_RESERVED_DWORD +}; + +#pragma pack(pop) + +VOID* CONST ReferenceAcpiTable = &AcpiSpcr; -- cgit v1.2.3