diff options
| author | Mohit Aggarwal <maggarwa@codeaurora.org> | 2014-02-06 12:50:05 +0530 |
|---|---|---|
| committer | Mohit Aggarwal <maggarwa@codeaurora.org> | 2014-02-10 13:46:35 +0530 |
| commit | dc4250167e7aa055c2b4d739ffa80e948f417c8a (patch) | |
| tree | f4774f7a08fcdb2ab7512d7323bc41e7c26cc083 /drivers/rtc | |
| parent | cd74cbf9e678b7d2285f166af2658bde2a7a5259 (diff) | |
rtc: qpnp-rtc: Sets RTC time correctly
Currently RTC driver is not setting the RTC time
correctly. RTC H/w needs to be disabled before the
writes, and then re-enabled after the writes are completed.
Change-Id: I4f66a2ea5b8ba52a5e9dcf21da7a09c36b1c9074
CRs-Fixed: 610221
Signed-off-by: Mohit Aggarwal <maggarwa@codeaurora.org>
Diffstat (limited to 'drivers/rtc')
| -rw-r--r-- | drivers/rtc/qpnp-rtc.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/drivers/rtc/qpnp-rtc.c b/drivers/rtc/qpnp-rtc.c index 11a593cb9161..4d73cf1bedcb 100644 --- a/drivers/rtc/qpnp-rtc.c +++ b/drivers/rtc/qpnp-rtc.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -102,6 +102,7 @@ qpnp_rtc_set_time(struct device *dev, struct rtc_time *tm) int rc; unsigned long secs, irq_flags; u8 value[4], reg = 0, alarm_enabled = 0, ctrl_reg; + u8 rtc_disabled = 0, rtc_ctrl_reg; struct qpnp_rtc *rtc_dd = dev_get_drvdata(dev); rtc_tm_to_time(tm, &secs); @@ -152,6 +153,22 @@ qpnp_rtc_set_time(struct device *dev, struct rtc_time *tm) * write operation */ + /* Disable RTC H/w before writing on RTC register*/ + rtc_ctrl_reg = rtc_dd->rtc_ctrl_reg; + if (rtc_ctrl_reg & BIT_RTC_ENABLE) { + rtc_disabled = 1; + rtc_ctrl_reg &= ~BIT_RTC_ENABLE; + rc = qpnp_write_wrapper(rtc_dd, &rtc_ctrl_reg, + rtc_dd->rtc_base + REG_OFFSET_RTC_CTRL, 1); + if (rc) { + dev_err(dev, + "Disabling of RTC control reg failed" + " with error:%d\n", rc); + goto rtc_rw_fail; + } + rtc_dd->rtc_ctrl_reg = rtc_ctrl_reg; + } + /* Clear WDATA[0] */ reg = 0x0; rc = qpnp_write_wrapper(rtc_dd, ®, @@ -177,6 +194,20 @@ qpnp_rtc_set_time(struct device *dev, struct rtc_time *tm) goto rtc_rw_fail; } + /* Enable RTC H/w after writing on RTC register*/ + if (rtc_disabled) { + rtc_ctrl_reg |= BIT_RTC_ENABLE; + rc = qpnp_write_wrapper(rtc_dd, &rtc_ctrl_reg, + rtc_dd->rtc_base + REG_OFFSET_RTC_CTRL, 1); + if (rc) { + dev_err(dev, + "Enabling of RTC control reg failed" + " with error:%d\n", rc); + goto rtc_rw_fail; + } + rtc_dd->rtc_ctrl_reg = rtc_ctrl_reg; + } + if (alarm_enabled) { ctrl_reg |= BIT_RTC_ALARM_ENABLE; rc = qpnp_write_wrapper(rtc_dd, &ctrl_reg, |