From f1d0aef06ae7fe09793d46589bd94fa36c45bbc0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Apr 2015 15:52:42 -0500 Subject: pxa1928-helium: Enable console on both UART1 and UART3 UART3 is on the debug header. UART1 is on the expansion header. Enable both as different users may have different serial cables. Signed-off-by: Rob Herring --- arch/arm/include/asm/arch-pxa1928/mfp.h | 5 +++++ board/Marvell/pxa1928_helium/pxa1928_helium.c | 5 +++++ include/configs/pxa1928_helium.h | 14 ++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/arch/arm/include/asm/arch-pxa1928/mfp.h b/arch/arm/include/asm/arch-pxa1928/mfp.h index 8276ecfa40..47d0d576f1 100644 --- a/arch/arm/include/asm/arch-pxa1928/mfp.h +++ b/arch/arm/include/asm/arch-pxa1928/mfp.h @@ -90,6 +90,11 @@ #define GPIO9_IN_MFP9 (MFP_REG(0x134) | MFP_AF0 | MFP_PULL_HIGH) #define GPIO17_OUT_MFP17 (MFP_REG(0x15C) | MFP_AF0 | MFP_DRIVE_SLOW) +#define UART1_RXD_GPIO51_MFP51 (MFP_REG(0x1BC) | MFP_AF1 | MFP_DRIVE_SLOW) +#define UART1_TXD_GPIO52_MFP52 (MFP_REG(0x1C0) | MFP_AF1 | MFP_DRIVE_SLOW) +#define UART1_CTS_GPIO53_MFP53 (MFP_REG(0x1C4) | MFP_AF1 | MFP_DRIVE_SLOW) +#define UART1_RTS_GPIO54_MFP54 (MFP_REG(0x1C8) | MFP_AF1 | MFP_DRIVE_SLOW) + #define BOOST_5V_EN_MFP10 (MFP_REG(0x138) | MFP_AF0 | MFP_DRIVE_MEDIUM) /* Volume Down Key for fastboot */ diff --git a/board/Marvell/pxa1928_helium/pxa1928_helium.c b/board/Marvell/pxa1928_helium/pxa1928_helium.c index 27398d672e..8fb240bcb9 100644 --- a/board/Marvell/pxa1928_helium/pxa1928_helium.c +++ b/board/Marvell/pxa1928_helium/pxa1928_helium.c @@ -63,6 +63,11 @@ static int highperf; int board_early_init_f(void) { u32 mfp_cfg[] = { + /* UART1 */ + UART1_RXD_GPIO51_MFP51, + UART1_TXD_GPIO52_MFP52, + UART1_CTS_GPIO53_MFP53, + UART1_RTS_GPIO54_MFP54, /* UART3 */ UART3_RXD_MMC2_DAT7_MFP33, UART3_TXD_MMC2_DAT6_MFP34, diff --git a/include/configs/pxa1928_helium.h b/include/configs/pxa1928_helium.h index b965a46995..fab16ca48a 100644 --- a/include/configs/pxa1928_helium.h +++ b/include/configs/pxa1928_helium.h @@ -30,6 +30,10 @@ #define COUNTER_FREQUENCY (0x340000) /* 3.25MHz */ #define SECONDARY_CPU_MAILBOX 0x01210000 +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_OF_STDOUT_VIA_ALIAS + #define CPU_RELEASE_ADDR 0xffffffff /* should not be touched */ #define CONFIG_SMP @@ -96,6 +100,13 @@ #undef CONFIG_ARCH_MISC_INIT +#undef CONFIG_SYS_NS16550_COM1 +#define CONFIG_SYS_NS16550_COM1 PXA1928_UART1_BASE +#define CONFIG_SYS_NS16550_COM3 PXA1928_UART3_BASE + +#undef CONFIG_CONS_INDEX +#define CONFIG_CONS_INDEX 3 /*Console on UART3 */ + /* * Boot setting */ @@ -130,6 +141,9 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=eserial0,eserial2\0" \ + "stdout=eserial0,eserial2\0" \ + "stderr=eserial0,eserial2\0" \ "autostart=yes\0" \ "verify=yes\0" \ "cdc_connect_timeout=60\0" \ -- cgit v1.2.3