armv8: add arch-pxa1928 support

add arch-pxa1928 support under arch/arm/cpu/armv8/pxa1928
arch/arm/include/asm/arch-pxa1928/

ported from m2011.09:
1. arch/arm/cpu/armv8/pxa1928/cpu.c:
1.1. removed CONFIG_PXA168_FB/I2C_MV related code
1.2. kept I2C_MV/SDHCI/USB clock enabling of APMU
2. arch/arm/cpu/armv8/pxa1928/smp_init.S: removed due to:
2.1. release slave cpu and set release addr is no need for mcpm or
psci and might be harmful.
2.2. LPM test is removed.
3. arch/arm/include/asm/arch-pxa1928/cpu.h
3.1. removed cpu_is_ca7/9
3.2. removed sdh_ functions
4. arch/arm/include/asm/arch-pxa1928/config.h
4.1. removed configures for i2c/usb/mmc/lcd

added:
1. arch/arm/include/asm/arch-pxa1928/cpu.h
1.1. extern smp_config/smp_hw_cpuid out so that no need to extern in c

Change-Id: I51bbe2d0891e1944698c4329f38d65c428fb9229
Signed-off-by: Zhou Zhu <zzhu3@marvell.com>

10 files changed, 959 insertions, 0 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 72558b8562..348db4bb95 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -198,6 +198,9 @@ config ARCH_NOMADIK
 config ORION5X
 	bool "Marvell Orion"
 
+config TARGET_PXA1928DKB
+	bool "Marvell PXA1928DKB"
+
 config TARGET_DKB
 	bool "Support dkb"
 
@@ -569,6 +572,7 @@ source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
 source "board/Marvell/dkb/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
+source "board/Marvell/pxa1928_concord/Kconfig"
 source "board/afeb9260/Kconfig"
 source "board/altera/socfpga/Kconfig"
 source "board/armadeus/apf27/Kconfig"
diff --git a/arch/arm/cpu/armv8/pxa1928/Makefile b/arch/arm/cpu/armv8/pxa1928/Makefile
new file mode 100644
index 0000000000..c79df204cf
--- /dev/null
+++ b/arch/arm/cpu/armv8/pxa1928/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor <www.marvell.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+obj-y	+= cpu.o
+obj-y   += smp_init.o
diff --git a/arch/arm/cpu/armv8/pxa1928/cpu.c b/arch/arm/cpu/armv8/pxa1928/cpu.c
new file mode 100644
index 0000000000..a434512d05
--- /dev/null
+++ b/arch/arm/cpu/armv8/pxa1928/cpu.c
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pxa1928.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+
+/* Get SoC Access to Generic Timer */
+int timer_init(void)
+{
+	u32 tmp;
+
+	/* Enable WDTR2*/
+	tmp  = readl(PXA1928_MPMU_BASE + MPMU_CPRR);
+	tmp = tmp | MPMU_APRR_WDTR;
+	writel(tmp, PXA1928_MPMU_BASE + MPMU_CPRR);
+
+	/* Initialize Counter to zero */
+	writel(0xbaba, PXA1928_TMR2_BASE + TMR_WFAR);
+	writel(0xeb10, PXA1928_TMR2_BASE + TMR_WSAR);
+	writel(0x0, PXA1928_TMR2_BASE + GEN_TMR_LD1);
+
+	/* Program Generic Timer Clk Frequency */
+	writel(0xbaba, PXA1928_TMR2_BASE + TMR_WFAR);
+	writel(0xeb10, PXA1928_TMR2_BASE + TMR_WSAR);
+	tmp = readl(PXA1928_TMR2_BASE + GEN_TMR_CFG);
+	tmp |= (3 << 4); /* 3.25MHz/32KHz Counter auto switch enabled */
+	writel(0xbaba, PXA1928_TMR2_BASE + TMR_WFAR);
+	writel(0xeb10, PXA1928_TMR2_BASE + TMR_WSAR);
+	writel(tmp, PXA1928_TMR2_BASE + GEN_TMR_CFG);
+
+	/* Start the Generic Timer Counter */
+	writel(0xbaba, PXA1928_TMR2_BASE + TMR_WFAR);
+	writel(0xeb10, PXA1928_TMR2_BASE + TMR_WSAR);
+	tmp = readl(PXA1928_TMR2_BASE + GEN_TMR_CFG);
+	tmp |= 0x3;
+	writel(0xbaba, PXA1928_TMR2_BASE + TMR_WFAR);
+	writel(0xeb10, PXA1928_TMR2_BASE + TMR_WSAR);
+	writel(tmp, PXA1928_TMR2_BASE + GEN_TMR_CFG);
+
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+	__attribute__((unused))	struct pxa1928apmu_registers *apmu =
+		(struct pxa1928apmu_registers *)PXA1928_APMU_BASE;
+	struct pxa1928mpmu_registers *mpmu =
+		(struct pxa1928mpmu_registers *)PXA1928_MPMU_BASE;
+	struct pxa1928apbc_registers *apbc =
+		(struct pxa1928apbc_registers *)PXA1928_APBC_BASE;
+	u32 val;
+
+	/* Turn on APB, PLL1, PLL2 clock */
+	writel(0x3FFFF, &apmu->gbl_clkctrl);
+
+	/* Turn on APB2 clock, select APB2 clock 26MHz */
+	writel(0x12, &apmu->apb2_clkctrl);
+
+	/* Turn on MPMU register clock */
+	writel(APBC_APBCLK, &apbc->mpmu);
+
+	/*
+	 * FIXME: This is a secure register so system may hang in global secure
+	 * mode. This register should control timer2/timer3 clock while
+	 * apbc->timers control timer1 clock.
+	 */
+	/* Turn on MPMU1 Timer register clock */
+	writel(0, &apbc->mpmu1);
+
+	/* Turn on clock gating (PMUM_CGR_PJ) */
+	/*writel(0xFFFFFFFF, &mpmu->acgr);*/
+	val = readl(&mpmu->cgr_pj);
+	val |= (0x1<<19) | (0x1<<17) | (0x7<<13) | (0x1<<9) | (0x1F<<1);
+	writel(val, &mpmu->cgr_pj);
+
+	/* Turn on AIB clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->aib);
+
+	/* Turn on uart1 clock */
+	writel(UARTCLK14745KHZ, &apbc->uart1);
+
+	/* Turn on uart3 clock */
+	writel(UARTCLK14745KHZ, &apbc->uart3);
+
+	/* Turn on GPIO clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->gpio);
+
+#ifdef CONFIG_I2C_MV
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi1);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi2);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi3);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi4);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi5);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi6);
+#endif
+
+#ifdef CONFIG_MV_SDHCI
+	/* Enable SD1 clock */
+	writel(APMU_PERIPH_CLK_EN | APMU_AXI_CLK_EN | APMU_PERIPH_RESET |
+		APMU_AXI_RESET | (6 << 10), &apmu->sd1); /* PLL1(624Mhz)/6 */
+
+	/* Enable SD3 clock */
+	writel(APMU_PERIPH_CLK_EN | APMU_AXI_CLK_EN | APMU_PERIPH_RESET |
+		APMU_AXI_RESET, &apmu->sd3);
+#endif
+
+#ifdef CONFIG_USB_GADGET_MV
+	/* Enable usb clock */
+	writel(APMU_AXI_CLK_EN | APMU_AXI_RESET , &apmu->usb);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	printf("SoC:   PXA1928 (CA53 Core)\n");
+
+	return 0;
+}
+#endif
+
+u32 smp_hw_cpuid(void)
+{
+	return 0;
+}
+
+u32 smp_config(void)
+{
+	return 1;
+}
diff --git a/arch/arm/cpu/armv8/pxa1928/smp_init.S b/arch/arm/cpu/armv8/pxa1928/smp_init.S
new file mode 100644
index 0000000000..eb53ea5230
--- /dev/null
+++ b/arch/arm/cpu/armv8/pxa1928/smp_init.S
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2013
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.ltorg
+
+.globl lowlevel_init
+        .type   lowlevel_init, %function
+lowlevel_init:
+#ifdef CONFIG_SMP
+	mrs     x0, mpidr_el1
+	tst     x0, #15
+	b.eq    master_cpu
+
+slave_cpu:
+	b	retn
+
+master_cpu:
+	/* Init the mailbox to zero */
+	ldr     x1, =SECONDARY_CPU_MAILBOX
+	str	xzr, [x1]
+
+retn:
+#endif
+	ret
+
+.ltorg
+
+.globl loop_delay
+	.type loop_delay, %function
+loop_delay:
+	subs	x0, x0, #1
+	bhi	loop_delay
+	ret
+
+.ltorg
+
+.globl save_boot_params
+save_boot_params:
+#ifdef CONFIG_OBM_PARAM_ADDR
+	ldr     x0,  =CONFIG_OBM_PARAM_ADDR
+	str	w11,	[x0]
+#endif
+	ret
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4f22..b04e8ba8ad 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -44,6 +44,7 @@ _bss_end_ofs:
 	.quad	__bss_end - _start
 
 reset:
+	bl      save_boot_params
 	/*
 	 * Could be EL3/EL2/EL1, Initial State:
 	 * Little Endian, MMU Disabled, i/dCache Disabled
diff --git a/arch/arm/include/asm/arch-pxa1928/config.h b/arch/arm/include/asm/arch-pxa1928/config.h
new file mode 100644
index 0000000000..36dd48bfcf
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa1928/config.h
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PXA1928_CONFIG_H
+#define _PXA1928_CONFIG_H
+
+#include <asm/arch/pxa1928.h>
+
+/*
+ * UART definition
+ */
+#ifdef CONFIG_PXA1928_FPGA
+#define MV_UART_CONSOLE_BASE	PXA1928_UART1_BASE
+#else
+#define MV_UART_CONSOLE_BASE	PXA1928_UART3_BASE
+#endif
+#define CONFIG_SYS_TCLK		(26000000)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(32000)	/* Timer Freq. 32KHZ */
+
+/*
+ * load definition
+ */
+#undef CONFIG_SYS_LOAD_ADDR
+#define CONFIG_ANDROID_BOOT_IMAGE
+
+#define CONFIG_LOADADDR		0xb000000
+
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_SYS_TIMERBASE	PXA1928_TIMER_BASE
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+
+/* Save some global variables in SRAM */
+#define CONFIG_SRAM_BASE                0xd1020000
+#define CONFIG_PARAM_BASE		0x090F0000
+#define CONFIG_OBM_PARAM_MAGIC          CONFIG_PARAM_BASE
+#define CONFIG_OBM_PARAM_ADDR           (CONFIG_PARAM_BASE + 0x4)
+#define CONFIG_WARM_RESET		(CONFIG_PARAM_BASE + 0x8)
+#define CONFIG_AMP_SYNC_ADDR		(CONFIG_PARAM_BASE + 0xC)
+#define CONFIG_CORE_BUSY_ADDR		(CONFIG_PARAM_BASE + 0x10)
+
+/*
+ * dram definition
+ */
+#define CONFIG_SYS_MCK5_DDR
+
+/*
+ * timer definition
+ */
+#define CONFIG_TIMER_MMP
+
+/*
+ * I2C definition
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MV           1
+#define CONFIG_MV_I2C_NUM       6
+#define CONFIG_I2C_MULTI_BUS    1
+#define CONFIG_MV_I2C_REG       {0xd4011000, 0xd4031000, 0xd4032000, \
+					0xd4033000, 0xd4033800, 0xd4034000}
+#define CONFIG_HARD_I2C         1
+#define CONFIG_SYS_I2C_SPEED    100000
+#define CONFIG_SYS_I2C_SLAVE    0
+#endif
+
+/*
+ * MMC definition
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT          1
+#define CONFIG_MMC              1
+#define CONFIG_GENERIC_MMC      1
+#define CONFIG_SDHCI            1
+#define CONFIG_MMC_SDMA         1
+#define CONFIG_MV_SDHCI         1
+#define CONFIG_DOS_PARTITION    1
+#define CONFIG_EFI_PARTITION    1
+#define CONFIG_SYS_MMC_NUM      2
+#define CONFIG_SYS_MMC_BASE     {0xd4217000, 0xD4280000}
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT   100
+#endif
+/*
+ * USB definition
+ */
+#ifdef CONFIG_USB_ETHER
+#define CONFIG_USB_GADGET_MV	1
+#define CONFIG_USB_GADGET_DUALSPEED	1
+#define CONFIG_CMD_NET		1
+#define CONFIG_IPADDR		192.168.1.101
+#define CONFIG_SERVERIP		192.168.1.100
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NET_MULTI	1
+#define CONFIG_USBNET_DEV_ADDR	"00:0a:fa:63:8b:e8"
+#define CONFIG_USBNET_HOST_ADDR	"0a:fa:63:8b:e8:0a"
+#define CONFIG_MV_UDC		1
+#define CONFIG_URB_BUF_SIZE	256
+#define CONFIG_USB_REG_BASE	0xd4208000
+#define CONFIG_USB_PHY_BASE	0xd4207000
+#endif
+
+#ifdef CONFIG_CMD_FASTBOOT
+#define CONFIG_USBD_VENDORID		0x18d1
+#define CONFIG_USBD_PRODUCTID		0x4e11
+#define CONFIG_USBD_MANUFACTURER	"Marvell Inc."
+#define CONFIG_USBD_PRODUCT_NAME	"Android 2.1"
+#define CONFIG_SERIAL_NUM		"MRUUUVLs001"
+#define CONFIG_USBD_CONFIGURATION_STR	"fastboot"
+#define CONFIG_SYS_FB_YAFFS \
+	{"cache", "system", "userdata", "telephony"}
+#define CONFIG_SYS_FASTBOOT_ONFLY_SZ	0x40000
+#define USB_LOADADDR			0x100000
+#define CONFIG_FB_RESV			512
+#endif
+
+/*
+ * GPIO/MFP definition
+ */
+#ifdef CONFIG_CMD_GPIO
+#define CONFIG_MARVELL_GPIO    1
+#endif
+#ifdef CONFIG_CMD_MFP
+#define CONFIG_MARVELL_MFP	1
+#define MV_MFPR_BASE		PXA1928_MFPR_BASE
+#endif
+
+
+/*
+ * FASTBOOT definition
+ */
+
+/*
+ * EXTRA ENV definition
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"autostart=yes\0"				\
+	"verify=yes\0"					\
+	"cdc_connect_timeout=60\0"
+
+/*
+ * LCD definition
+ */
+#endif /* _PXA1928_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pxa1928/cpu.h b/arch/arm/include/asm/arch-pxa1928/cpu.h
new file mode 100644
index 0000000000..5c7fd7b89c
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa1928/cpu.h
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PXA1928_CPU_H
+#define _PXA1928_CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * Main Power Management (MPMU) Registers
+ */
+struct pxa1928mpmu_registers {
+	u32 pcr_sp;	/*0x0*/
+	u8 pad0[0x38 - 4];
+	u32 sccr;	/*0x38*/
+	u8 pad1[0x1000 - 0x38 - 4];
+	u32 pcr_pj;	/*0x1000*/
+	u8 pad2[0x1024 - 0x1000 - 4];
+	u32 cgr_pj;	/*0x1024*/
+	u32 rsr_pj;	/*0x1028*/
+	u8 pad3[0x1140 - 0x1028 - 4];
+	u32 dvc_stb1;	/*0x1140*/
+	u32 dvc_stb2;	/*0x1144*/
+	u32 dvc_stb3;	/*0x1148*/
+	u32 dvc_stb4;	/*0x114C*/
+	u32 dvc_debug;	/*0x1150*/
+};
+
+/*
+ * I/O domains power control registers
+ */
+struct pxa1928aib_registers {
+	u8 pad0[0x20];
+	u32 nand;	/*0x20*/
+};
+
+/*
+ * APB Clock Reset/Control Registers
+ */
+struct pxa1928apbc_registers {
+	u8 pad0[0x004];
+	u32 twsi1;	/*0x004*/
+	u32 twsi2;	/*0x008*/
+	u32 twsi3;	/*0x00c*/
+	u32 twsi4;	/*0x010*/
+	u8 pad1[0x024 - 0x10 - 4];
+	u32 timers;	/*0x024*/
+	u8 pad2[0x02C - 0x24 - 4];
+	u32 uart1;	/*0x02C*/
+	u8 pad3[0x034 - 0x2C - 4];
+	u32 uart3;	/*0x034*/
+	u32 gpio;	/*0x038*/
+	u8 pad4[0x044 - 0x38 - 4];
+	u32 pwm3;	/*0x044*/
+	u8 pad5[0x064 - 0x44 - 4];
+	u32 aib;	/*0x064*/
+#define FIRST_ACCESS_KEY        0xBABA  /* AIB Code Locked First Access Key */
+#define SECOND_ACCESS_KEY       0xEB10  /* AIB Code Locked Second Access Key */
+	u32 asfar;	/*0x068*/
+	u32 assar;	/*0x06c*/
+	u8 pad6[0x074 - 0x6c - 4];
+	u32 mpmu;	/*0x74*/
+	u8 pad7[0x07c - 0x74 - 4];
+	u32 twsi5;	/*0x07c*/
+	u32 twsi6;	/*0x080*/
+	u8 pad8[0x0B0 - 0x80 - 4];
+	u32 mpmu1;	/*0x0B0*/
+};
+
+/*
+ * Application Subsystem PMU(APMU) Registers
+ */
+struct pxa1928apmu_registers {
+	u32 cc_sp;		/*0x0*/
+	u32 cc_pj;		/*0x4*/
+	u8 pad0[0x034 - 0x8];
+	u32 usb_dyn_gate;	/*0x034*/
+	u8 pad1[0x04c - 0x34 - 4];
+	union {
+		u32 display1;	/*0x04c PXA1928 Zx*/
+		u32 pad2;
+	};
+	u8 pad3[0x054 - 0x4c - 4];
+	u32 sd1;		/*0x054*/
+	u8 pad4[0x05c - 0x54 - 4];
+	u32 usb;		/*0x05c*/
+	u8 pad5[0x064 - 0x5c - 4];
+	union {
+		u32 pad6;
+		u32 dma_clk;	/*0x064 PXA1928 A0*/
+	};
+	u8 pad7[0x088 - 0x64 - 4];
+	u32 debug;		/*0x088*/
+	u8 pad8[0x0dc - 0x88 - 4];
+	u32 gbl_clkctrl;	/*0x0dc*/
+	u8 pad9[0x0e8 - 0xdc - 4];
+	u32 sd3;		/*0x0e8*/
+	u8 pad10[0x110 - 0xe8 - 4];
+	union {
+	u32 display2;		/*0x110 PXA1928 Zx*/
+	u32 pad11;
+	};
+	u8 pad12[0x134 - 0x110 - 4];
+	u32 apb2_clkctrl;	/*0x134*/
+	u8 pad13[0x184 - 0x134 - 8];
+	union {
+		u32 pad14;
+		u32 disp_rstctrl;/*0x180*/
+	};
+	union {
+		u32 pad15;
+		u32 disp_clkctrl;/*0x184*/
+	};
+	union {
+		u32 pad16;
+		u32 disp_clkctrl2;/*0x188*/
+	};
+	u8 pad17[0x1ac - 0x184 - 8];
+	u32 isld_lcd_ctrl;	/*0x1ac*/
+	u8 pad18[0x204 - 0x1ac - 4];
+	u32 isld_lcd_pwrctrl;	/*0x204*/
+	u8 pad19[0x390 - 0x204 - 4];
+	u32 debug2;	/*0x390*/
+};
+
+/*
+ * Timer registers
+ */
+struct pxa1928timer_registers {
+	u32 ccr;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 cr[3];	/* Timer count registers */
+	u32 sr[3];
+	u32 ier[3];
+	u32 plvr[3];	/* Timer preload value */
+	u32 plcr[3];
+	u32 wmer;
+	u32 wmr;
+	u32 wvr;
+	u32 wsr;
+	u32 icr[3];
+	u32 wicr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr[3];
+	u32 crsr;
+};
+
+struct pxa1928cpu_registers {
+	u32 chip_id;            /* Chip Id Reg */
+};
+
+int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
+#define SD_FIFO_PARAM                  0x104
+#define  FORCE_CLK_ON		(1 << 12)
+#define  OVRRD_CLK_OE		(1 << 11)
+#define  CLK_GATE_ON		(1 << 9)
+#define  CLK_GATE_CTL		(1 << 8)
+#define  WTC_DEF		0x1
+#define  WTC(x)			((x & 0x3) << 2)
+#define  RTC_DEF		0x1
+#define  RTC(x)			(x & 0x3)
+
+#define SD_CLOCK_AND_BURST_SIZE_SETUP  0x10a
+#define  SDCLK_SEL		(1 << 8)
+#define  WR_ENDIAN		(1 << 7)
+#define  RD_ENDIAN		(1 << 6)
+#define  DMA_FIFO_128		1
+#define  DMA_SIZE(x)		((x & 0x3) << 2)
+#define  BURST_64		1
+#define  BURST_SIZE(x)		(x & 0x3)
+
+#define RX_CFG_REG		0x114
+#define TUNING_DLY_INC(x)	((x & 0x1ff) << 17)
+#define SDCLK_DELAY(x)		((x & 0x1ff) << 8)
+#define SDCLK_SEL0(x)		((x & 0x3) << 0)
+#define SDCLK_SEL1(x)		((x & 0x3) << 2)
+
+#define TX_CFG_REG		0x118
+#define TX_MUX_DLL		(1 << 31)
+#define TX_INT_CLK_INV		(1 << 30)
+#define TX_HOLD_DELAY0(x)	((x & 0x1ff) << 0)
+#define TX_HOLD_DELAY1(x)	((x & 0x1ff) << 16)
+
+#define CHIP_ID			0xD4282C00
+static unsigned int mmp_chip_id(void)
+{
+	static unsigned int chip_id;
+	if (!chip_id)
+		chip_id = readl(CHIP_ID);
+	printf("chip_id = %x\n", chip_id);
+	return chip_id;
+}
+
+static inline int cpu_is_pxa1928_b0(void)
+{
+	return ((mmp_chip_id() & 0xffffff) == 0xb0c198);
+}
+
+static inline int cpu_is_pxa1928_a0(void)
+{
+	return ((mmp_chip_id() & 0xffffff) == 0xa0c198);
+}
+
+extern u32 smp_config(void);
+extern u32 smp_hw_cpuid(void);
+extern void loop_delay(u64 delay);
+
+#endif /* _PXA1928_CPU_H */
diff --git a/arch/arm/include/asm/arch-pxa1928/gpio.h b/arch/arm/include/asm/arch-pxa1928/gpio.h
new file mode 100644
index 0000000000..6d94ec5448
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa1928/gpio.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2013
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include <asm/types.h>
+#include <asm/arch/pxa1928.h>
+
+#define GPIO_TO_REG(gp)		(gp >> 5)
+#define GPIO_TO_BIT(gp)		(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val)	((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+	/* GPIO modes: normal/secure
+	* Current mode is normal
+	*/
+	const unsigned long offset[7] = {0, 4, 8, 0x100, 0x104, 0x108, 0x200};
+	return (struct gpio_reg *)(PXA1928_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
diff --git a/arch/arm/include/asm/arch-pxa1928/mfp.h b/arch/arm/include/asm/arch-pxa1928/mfp.h
new file mode 100644
index 0000000000..7b0e05de2a
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa1928/mfp.h
@@ -0,0 +1,196 @@
+/*
+ * Based on arch/arm/include/asm/arch-armada100/mfp.h
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PXA1928_MFP_H
+#define __PXA1928_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ *
+ * Naming: Board usage name + ball/pad name + mfp offset
+ * If board usage name is same as ball/pad name, no need to repeat.
+ */
+/* UART3 */
+#define UART3_RXD_MMC2_DAT7_MFP33		(MFP_REG(0x40) | MFP_AF7 | MFP_DRIVE_MEDIUM)
+#define UART3_TXD_MMC2_DAT6_MFP34		(MFP_REG(0x44) | MFP_AF7 | MFP_DRIVE_MEDIUM)
+
+/* PWR_TWSI */
+#define PWR_SCL_MFP67		(MFP_REG(0x140) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define PWR_SDA_MFP68		(MFP_REG(0x144) | MFP_AF0 | MFP_DRIVE_SLOW)
+
+/* TWSI2 */
+#define TWSI2_SCL_MFP43		(MFP_REG(0x19C) | MFP_AF6 | MFP_DRIVE_SLOW)
+#define TWSI2_SDA_MFP44		(MFP_REG(0x1A0) | MFP_AF6 | MFP_DRIVE_SLOW)
+
+/* TWSI3 */
+#define TWSI3_SCL_MFP31		(MFP_REG(0x194) | MFP_AF7 | MFP_DRIVE_SLOW)
+#define TWSI3_SDA_MFP32		(MFP_REG(0x198) | MFP_AF7 | MFP_DRIVE_SLOW)
+#define TWSI3_SCL_MFP18		(MFP_REG(0x160) | MFP_AF4 | MFP_DRIVE_SLOW)
+#define TWSI3_SDA_MFP19		(MFP_REG(0x164) | MFP_AF4 | MFP_DRIVE_SLOW)
+
+/* TWSI4 */
+#define TWSI4_SCL_MFP46		(MFP_REG(0x1A8) | MFP_AF6 | MFP_DRIVE_SLOW)
+#define TWSI4_SDA_MFP45		(MFP_REG(0x1A4) | MFP_AF6 | MFP_DRIVE_SLOW)
+
+/* TWSI5 */
+#define TWSI5_SCL_MFP29		(MFP_REG(0x18C) | MFP_AF7 | MFP_DRIVE_SLOW)
+#define TWSI5_SDA_MFP30		(MFP_REG(0x190) | MFP_AF7 | MFP_DRIVE_SLOW)
+
+/* TWSI6 */
+#define TWSI6_SCL_MMC2_DAT5_MFP35	(MFP_REG(0x48) | MFP_AF5 | MFP_DRIVE_SLOW)
+#define TWSI6_SDA_MMC2_DAT4_MFP36	(MFP_REG(0x4C) | MFP_AF5 | MFP_DRIVE_SLOW)
+
+/* MMC3(eMMC) */
+#define MMC3_DAT0_ND_IO8_MFP87		(MFP_REG(0x88) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC3_DAT1_ND_IO9_MFP86		(MFP_REG(0x8C) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC3_DAT2_ND_IO10_MFP85		(MFP_REG(0x90) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC3_DAT3_ND_IO11_MFP84		(MFP_REG(0x94) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC3_DAT4_ND_IO12_MFP83		(MFP_REG(0x98) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC3_DAT5_ND_IO13_MFP82		(MFP_REG(0x9C) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC3_DAT6_ND_IO14_MFP81		(MFP_REG(0xA0) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC3_DAT7_ND_IO15_MFP80		(MFP_REG(0xA4) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC3_CLK_SM_ADVMUX_MFP88	(MFP_REG(0xDC) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_LOW)
+#define MMC3_CMD_SM_RDY_MFP89		(MFP_REG(0xE0) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC3_RST_ND_CLE_MFP90		(MFP_REG(0xC0) | MFP_AF1 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+
+/* MMC1(SD) */
+#define MMC1_DAT0_MFP62		(MFP_REG(0x2C) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_DAT1_MFP61		(MFP_REG(0x28) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_DAT2_MFP60		(MFP_REG(0x24) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_DAT3_MFP59		(MFP_REG(0x20) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_DAT4_MFP58		(MFP_REG(0x1C) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_DAT5_MFP57		(MFP_REG(0x18) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_DAT6_MFP56		(MFP_REG(0x14) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_DAT7_MFP55		(MFP_REG(0x10) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_CLK_MFP64		(MFP_REG(0x34) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_LOW)
+#define MMC1_CMD_MFP63		(MFP_REG(0x30) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_CD_N_MFP65		(MFP_REG(0x38) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define MMC1_WP_MFP66		(MFP_REG(0x3C) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+
+/* LCD and backlight */
+#define BACKLIGHT_PWM2_MFP51	(MFP_REG(0x1BC) | MFP_AF2 | MFP_DRIVE_MEDIUM) /* FIXME */
+#define LCD_RESET_MFP121	(MFP_REG(0x1F4) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define LCD_BACKLIGHT_EN_MFP6	(MFP_REG(0x128) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define BOOST_5V_EN_MFP125	(MFP_REG(0x238) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define BOOST_5V_EN_MFP10	(MFP_REG(0x138) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+
+/* Volume Down Key for fastboot */
+#define GPIO17_MFP17	(MFP_REG(0x15C) | MFP_AF0 | MFP_PULL_HIGH)
+/* Volume Up Key for recovery on concord rev1 */
+#define GPIO16_MFP16	(MFP_REG(0x158) | MFP_AF0 | MFP_PULL_HIGH)
+/* Volume Up Key for recovery on concord rev2 */
+#define GPIO15_MFP15	(MFP_REG(0x154) | MFP_AF0 | MFP_PULL_HIGH)
+
+/* DVC pin */
+#define DVC_PIN0_MFP107		(MFP_REG(0xC8) | MFP_AF7 | MFP_DRIVE_MEDIUM)
+#define DVC_PIN1_MFP108		(MFP_REG(0xD0) | MFP_AF7 | MFP_DRIVE_MEDIUM)
+#define DVC_PIN2_MFP99		(MFP_REG(0xAC) | MFP_AF7 | MFP_DRIVE_MEDIUM)
+#define DVC_PIN3_MFP103		(MFP_REG(0xB0) | MFP_AF7 | MFP_DRIVE_MEDIUM)
+/* More macros can be defined here... */
+
+/* for discrete */
+/* TWSI2 */
+#define TWSI2_SCL_MFP178	(MFP_REG(0x2D0) | MFP_AF6 | MFP_DRIVE_SLOW)
+#define TWSI2_SDA_MFP179	(MFP_REG(0x2CC) | MFP_AF6 | MFP_DRIVE_SLOW)
+
+/* TWSI3 */
+#define TWSI3_SCL_MFP176	(MFP_REG(0x2D8) | MFP_AF7 | MFP_DRIVE_SLOW)
+#define TWSI3_SDA_MFP177	(MFP_REG(0x2D4) | MFP_AF7 | MFP_DRIVE_SLOW)
+
+/* TWSI4 */
+#define TWSI4_SCL_MFP181	(MFP_REG(0x2C4) | MFP_AF6 | MFP_DRIVE_SLOW)
+#define TWSI4_SDA_MFP180	(MFP_REG(0x2C8) | MFP_AF6 | MFP_DRIVE_SLOW)
+
+/* TWSI5 */
+#define TWSI5_SCL_MFP174	(MFP_REG(0x2E0) | MFP_AF7 | MFP_DRIVE_SLOW)
+#define TWSI5_SDA_MFP175	(MFP_REG(0x2DC) | MFP_AF7 | MFP_DRIVE_SLOW)
+
+/* LCD and backlight */
+#define BACKLIGHT_PWM2_MFP186	(MFP_REG(0x2B0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define LCD_BACKLIGHT_EN_MFP151	(MFP_REG(0x260) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define BOOST_5V_EN_MFP155	(MFP_REG(0x270) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+
+/* Volume Down Key for fastboot */
+#define GPIO162_MFP162		(MFP_REG(0x28C) | MFP_AF0 | MFP_PULL_HIGH)
+/* Volume Up Key for recovery on concord discrete */
+#define GPIO160_MFP160		(MFP_REG(0x284) | MFP_AF0 | MFP_PULL_HIGH)
+
+/*GPIO 00::54 */
+#define GPIO0_MFP0		(MFP_REG(0x110) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO1_MFP1		(MFP_REG(0x114) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO2_MFP2		(MFP_REG(0x118) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO3_MFP3		(MFP_REG(0x11C) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO4_MFP4		(MFP_REG(0x120) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO5_MFP5		(MFP_REG(0x124) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO6_MFP6		(MFP_REG(0x128) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO7_MFP7		(MFP_REG(0x12C) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO8_MFP8		(MFP_REG(0x130) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO9_MFP9		(MFP_REG(0x134) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO10_MFP10		(MFP_REG(0x138) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO11_MFP11		(MFP_REG(0x13C) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO12_MFP12		(MFP_REG(0x148) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO13_MFP13		(MFP_REG(0x14C) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO14_MFP14		(MFP_REG(0x150) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO18_MFP18		(MFP_REG(0x160) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO19_MFP19		(MFP_REG(0x164) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO20_MFP20		(MFP_REG(0x168) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO21_MFP21		(MFP_REG(0x16C) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO22_MFP22		(MFP_REG(0x170) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO23_MFP23		(MFP_REG(0x174) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO24_MFP24		(MFP_REG(0x178) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO25_MFP25		(MFP_REG(0x17C) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO26_MFP26		(MFP_REG(0x180) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO27_MFP27		(MFP_REG(0x184) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO28_MFP28		(MFP_REG(0x188) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO29_MFP29		(MFP_REG(0x18C) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO30_MFP30		(MFP_REG(0x190) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO31_MFP31		(MFP_REG(0x194) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO32_MFP32		(MFP_REG(0x198) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO43_MFP43		(MFP_REG(0x19C) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO44_MFP44		(MFP_REG(0x1A0) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO45_MFP45		(MFP_REG(0x1A4) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO46_MFP46		(MFP_REG(0x1A8) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO47_MFP47		(MFP_REG(0x1AC) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO48_MFP48		(MFP_REG(0x1B0) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO49_MFP49		(MFP_REG(0x1B4) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO50_MFP50		(MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO51_MFP51		(MFP_REG(0x1BC) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO52_MFP52		(MFP_REG(0x1C0) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO53_MFP53		(MFP_REG(0x1C4) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO54_MFP54		(MFP_REG(0x1C8) | MFP_AF0 | MFP_DRIVE_SLOW)
+
+/* GPIO 136::138 */
+#define GPIO136_MFP136		(MFP_REG(0x4) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define GPIO137_MFP137		(MFP_REG(0x8) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define GPIO138_MFP138		(MFP_REG(0xC) | MFP_AF1 | MFP_DRIVE_SLOW)
+
+/* GPIO 140::144 */
+#define GPIO140_MFP140		(MFP_REG(0x224) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define GPIO141_MFP141		(MFP_REG(0x21C) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define GPIO142_MFP142		(MFP_REG(0x220) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define GPIO143_MFP143		(MFP_REG(0x240) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define GPIO144_MFP144		(MFP_REG(0x244) | MFP_AF1 | MFP_DRIVE_SLOW)
+
+/* USIM */
+#define IC_USB_P_DIS_MFP193		(MFP_REG(0x308) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define IC_USB_N_DIS_MFP194		(MFP_REG(0x30C) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define USIM1_UCLK_DIS_MFP190		(MFP_REG(0x304) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define USIM1_UIO_DIS_MFP191		(MFP_REG(0x2FC) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define USIM1_NURST_DIS_MFP192		(MFP_REG(0x300) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define USIM2_UCLK_DIS_MFP195		(MFP_REG(0x318) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define USIM2_UIO_DIS_MFP196		(MFP_REG(0x310) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define USIM2_NURST_DIS_MFP197		(MFP_REG(0x314) | MFP_AF1 | MFP_DRIVE_SLOW)
+
+/* MMC1_CD */
+#define MMC1_CD_ND_NCS1_MFP100		(MFP_REG(0xB8) | MFP_AF7 | MFP_DRIVE_SLOW)
+/* GPIO */
+#define GPIO65_MFP65			(MFP_REG(0x38) | MFP_AF1 | MFP_DRIVE_SLOW)
+#endif /* __PXA1928_MFP_H */
diff --git a/arch/arm/include/asm/arch-pxa1928/pxa1928.h b/arch/arm/include/asm/arch-pxa1928/pxa1928.h
new file mode 100644
index 0000000000..e21b8e24ea
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa1928/pxa1928.h
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PXA1928_H
+#define _PXA1928_H
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK		(1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK		(1<<1)  /* Functional Clock Enable */
+#define APBC_RST		(1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0x7) << 4)
+
+/* Common APMU clock register bit definitions */
+#define APMU_PERIPH_CLK_EN	(1<<4)	/* Peripheral clock enable */
+#define APMU_AXI_CLK_EN		(1<<3)	/* AXI clock enable */
+#define APMU_PERIPH_RESET	(1<<1)	/* Peripheral reset */
+#define APMU_AXI_RESET		(1<<0)	/* AXI BUS reset */
+
+/* APMU clock register bit definitions for LCD/DSI */
+#define DISPLAY1_AXI_RST	(1<<0)
+#define DISPLAY1_RST		(1<<1)
+#define DSI_PHY_SLOW_RST	(1<<2)
+#define DISPLAY1_AXICLK_EN	(1<<3)
+#define DISPLAY1_CLK_EN		(1<<4)
+#define DSI_PHY_SLOW_CLK_EN	(1<<5)
+#define DISPLAY1_CLK_SEL_MASK	(3<<6)
+#define DISPLAY1_DEF_CLK_SEL	(3<<6)
+#define DISPLAY1_CLK_DIV_MASK	(0xf<<8)
+#define DISPLAY1_CLK_DIV(n)	((n & 0xf) << 8)
+#define DSI_ESCCLK_EN		(1<<12)
+#define DSI_PHYSLOW_DIV_MASK	(0x1f<<15)
+#define DSI_PHYSLOW_DIV(n)	((n & 0x1f) << 15)
+#define PLL1_CLKOUTP_SEL	(1<<21)
+#define DSI_ESC_CLK_SEL_MASK	(0x3<<22)
+#define DSI_ESC_DEF_CLK_SEL	(0x0<<22)
+#define	DISPLAY2_VDMA_AXICLK_EN	(0x1<<3)
+#define	DISPLAY2_VDMA_AXI_RST	(0x1<<0)
+
+/* APMU DMA CLK RESET CONTROLLER Register 0xd4282864 */
+#define MDMA_AXICLK_EN		(0x1 << 9)
+#define MDMA_AXI_RSTN		(0x1 << 8)
+#define DMA_AXICLK_EN		(0x1 << 3)
+#define DMA_AXI_RSTN		(0x1 << 0)
+
+/* APMU DISP CONTROLLER RESET Control Register 0xd4282980 */
+#define DISP_RSTCTRL_ESC_CLK_RSTN	(0x1 << 5)
+#define DISP_RSTCTRL_VDMA_CLK_RSTN	(0x1 << 4)
+#define DISP_RSTCTRL_HCLK_RSTN		(0x1 << 3)
+#define DISP_RSTCTRL_VDMA_PORSTN	(0x1 << 2)
+#define DISP_RSTCTRL_ACLK_PORSTN	(0x1 << 1)
+#define DISP_RSTCTRL_ACLK_RSTN		(0x1 << 0)
+
+/* APMU DISP CLOCK CONTROLLER Regsiters 0xd4282984 */
+#define DISP_CLKCTRL_VDMA_CLKSRC_MASK	(0x7 << 28)
+#define DISP_CLKCTRL_VDMA_CLKSRC_SEL	(0x0 << 28)
+#define DISP_CLKCTRL_VDMA_DIV		(0x1 << 24)
+#define DISP_CLKCTRL_VDMA_EN		(0x1 << 27)
+#define DISP_CLKCTRL_CLK2_CLKSRC_MASK	(0x7 << 20)
+#define DISP_CLKCTRL_CLK2_CLKSRC_SEL	(0x1 << 20)
+#define DISP_CLKCTRL_CLK2_DIV		(0x1 << 16)
+#define DISP_CLKCTRL_CLK2_EN		(0x1 << 23)
+#define DISP_CLKCTRL_CLK1_CLKSRC_MASK	(0x7 << 12)
+#define DISP_CLKCTRL_CLK1_CLKSRC_SEL	(0x1 << 12)
+#define DISP_CLKCTRL_CLK1_DIV		(0x1 << 8)
+#define DISP_CLKCTRL_CLK1_EN		(0x1 << 15)
+#define DISP_CLKCTRL_ESC_CLKSRC_MASK	(0x3 << 5)
+#define DISP_CLKCTRL_ESC_CLKSRC_SEL	(0x0 << 5)
+#define DISP_CLKCTRL_ESC_CLK_EN		(0x1 << 4)
+
+/* APMU DISP CLOCK CONTROLLER Regsiters 0xd4282988 */
+#define DISP_CLKCTRL2_ACLK_CLKSRC_SEL		(0x0 << 4)
+#define DISP_CLKCTRL2_ACLK_CLKSRC_SEL_MASK	(0x7 << 4)
+#define DISP_CLKCTRL2_ACLK_DIV			(0x1 << 0)
+#define DISP_CLKCTRL2_ACLK_EN			(0x1 << 7)
+
+/* APMU ISLD LCD CONTROLLER Register 0xd42829ac */
+#define ISLD_LCD_CTRL_RF1P_RTC		(0x2 << 30)
+#define ISLD_LCD_CTRL_RF1P_WTC		(0x2 << 28)
+#define ISLD_LCD_CTRL_RF2P_RTC		(0x2 << 26)
+#define ISLD_LCD_CTRL_RF2P_WTC		(0x1 << 24)
+#define ISLD_LCD_CTRL_SR1P_RTC		(0x2 << 22)
+#define ISLD_LCD_CTRL_SR1P_WTC		(0x2 << 20)
+#define ISLD_LCD_CTRL_SR2P_RTC		(0x2 << 18)
+#define ISLD_LCD_CTRL_SR2P_WTC		(0x2 << 16)
+#define	ISLD_LCD_CTRL_CMEM_DMMYCLK_EN	(0x1 << 4)
+#define ISLD_LCD_CTRL_MEM_FWALLBAR	(0x1 << 3)
+
+/* APMU ISLD LCD PWRCTRL Register 0xd4282a04 */
+#define ISLD_LCD_PWR_INT_STATUS		(0x1 << 8)
+#define ISLD_LCD_PWR_INT_MASK		(0x1 << 7)
+#define ISLD_LCD_PWR_INT_CLR		(0x1 << 6)
+#define ISLD_LCD_PWR_REDUN_STATUS	(0x1 << 5)
+#define	ISLD_LCD_PWR_STATUS		(0x1 << 4)
+#define ISLD_LCD_PWR_UP			(0x1 << 1)
+#define ISLD_LCD_PWR_HWMODE_EN		(0x1 << 0)
+
+/*  Marvell CPU Reset Status Register 0xd4051028*/
+#define	PMUM_RSR_PJ_TSR		(0x1 << 4)
+#define	PMUM_RSR_PJ_WDTR	(0x1 << 2)
+#define	PMUM_RSR_PJ_POR		(0x1 << 0)
+
+/* Timer2 Watchdog STatus Register */
+#define TMR2_WSR			0xD4080070
+#define TMR2_WSR_WTS			(0x1 << 0)
+
+/* Register Base Addresses */
+#define PXA1928_APBC_BASE		0xD4015000
+#define PXA1928_UART1_BASE		0xD4030000
+#define PXA1928_UART3_BASE		0xD4018000
+#define PXA1928_GPIO_BASE		0xD4019000
+#define PXA1928_MFPR_BASE		0xD401E000
+#define PXA1928_AIB_BASE		0xD401E800
+#define PXA1928_MPMU_BASE		0xD4050000
+#define PXA1928_TMR2_BASE		0xd4080000
+#define PXA1928_APMU_BASE		0xD4282800
+#define PXA1928_CPU_BASE		0xD4282C00
+#define PXA1928_USB_REG_BASE		0xd4208000
+
+/* for chip type define*/
+#define PXA_CHIP_TYPE_REG		0xD4292AB4
+#define PXA1926_2L_DISCRETE		0x0
+#define PXA1928_POP			0x1
+#define PXA1928_4L			0x2
+#define PXA1928_2L			0x3
+
+/* for arch timer*/
+#define MPMU_CPRR              0x0020
+#define MPMU_WDTPCR1           0x0204
+#define MPMU_APRR              0x1020
+
+#define MPMU_APRR_WDTR         (1 << 4)
+#define MPMU_APRR_CPR          (1 << 0)
+#define MPMU_CPRR_DSPR         (1 << 2)
+#define MPMU_CPRR_BBR          (1 << 3)
+
+#define TMR_WFAR               (0x009c)
+#define TMR_WSAR               (0x00A0)
+
+#define GEN_TMR_CFG            (0x00B0)
+#define GEN_TMR_LD1            (0x00B8)
+
+/* GIC base */
+#define GICD_BASE		0xd1e01000
+#define GICC_BASE		0xd1e02000
+/* 7 banks * 32 gpios/bank */
+#define MV_MAX_GPIO		224
+#endif /* _PXA1928_H */