pxa1928: Initial Helium board support

Copied from Ara AP module. Added GPIO/pinmux setup for USB hub and HDMI.

Change-Id: I86318b25b56d9e334b0b27a32a6ba87c9c526f0d
Signed-off-by: Rob Herring <rob.herring@linaro.org>

7 files changed, 704 insertions, 0 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a58427b3d7..e7eaa5f7a4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -204,6 +204,9 @@ config TARGET_PXA1928DKB
 config TARGET_PXA1928ARA
 	bool "Marvell PXA1928 Ara AP"
 
+config TARGET_PXA1928HELIUM
+	bool "Marvell PXA1928 Helium"
+
 config TARGET_DKB
 	bool "Support dkb"
 
@@ -577,6 +580,7 @@ source "board/Marvell/dkb/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/Marvell/pxa1928_concord/Kconfig"
 source "board/Marvell/pxa1928_ara/Kconfig"
+source "board/Marvell/pxa1928_helium/Kconfig"
 source "board/afeb9260/Kconfig"
 source "board/altera/socfpga/Kconfig"
 source "board/armadeus/apf27/Kconfig"
diff --git a/arch/arm/include/asm/arch-pxa1928/mfp.h b/arch/arm/include/asm/arch-pxa1928/mfp.h
index 9288e531db..8276ecfa40 100644
--- a/arch/arm/include/asm/arch-pxa1928/mfp.h
+++ b/arch/arm/include/asm/arch-pxa1928/mfp.h
@@ -80,6 +80,16 @@
 #define LCD_RESET_MFP121	(MFP_REG(0x1F4) | MFP_AF0 | MFP_DRIVE_MEDIUM)
 #define LCD_BACKLIGHT_EN_MFP6	(MFP_REG(0x128) | MFP_AF0 | MFP_DRIVE_MEDIUM)
 #define BOOST_5V_EN_MFP125	(MFP_REG(0x238) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+
+#define GPIO125_MFP125		(MFP_REG(0x238) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define GPIO132_MFP132		(MFP_REG(0x20C) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO135_MFP135		(MFP_REG(0x218) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO134_MFP134		(MFP_REG(0x214) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define VCXO_REQ_MFP77		(MFP_REG(0x104) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define VCXO_OUT_MFP78		(MFP_REG(0x108) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define GPIO9_IN_MFP9		(MFP_REG(0x134) | MFP_AF0 | MFP_PULL_HIGH)
+#define GPIO17_OUT_MFP17	(MFP_REG(0x15C) | MFP_AF0 | MFP_DRIVE_SLOW)
+
 #define BOOST_5V_EN_MFP10	(MFP_REG(0x138) | MFP_AF0 | MFP_DRIVE_MEDIUM)
 
 /* Volume Down Key for fastboot */
diff --git a/board/Marvell/pxa1928_helium/Kconfig b/board/Marvell/pxa1928_helium/Kconfig
new file mode 100644
index 0000000000..c55840a980
--- /dev/null
+++ b/board/Marvell/pxa1928_helium/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_PXA1928HELIUM
+
+config SYS_CPU
+	string
+	default "armv8"
+
+config SYS_BOARD
+	string
+	default "pxa1928_helium"
+
+config SYS_VENDOR
+	string
+	default "Marvell"
+
+config SYS_SOC
+	string
+	default "pxa1928"
+
+config SYS_CONFIG_NAME
+	string
+	default "pxa1928_helium"
+
+endif
diff --git a/board/Marvell/pxa1928_helium/Makefile b/board/Marvell/pxa1928_helium/Makefile
new file mode 100644
index 0000000000..0e003e8b72
--- /dev/null
+++ b/board/Marvell/pxa1928_helium/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014
+# Rob Herring, Linaro, Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := pxa1928_helium.o
diff --git a/board/Marvell/pxa1928_helium/pxa1928_helium.c b/board/Marvell/pxa1928_helium/pxa1928_helium.c
new file mode 100644
index 0000000000..27398d672e
--- /dev/null
+++ b/board/Marvell/pxa1928_helium/pxa1928_helium.c
@@ -0,0 +1,499 @@
+/*
+e* (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#ifdef CONFIG_SDHCI
+#include <sdhci.h>
+#endif
+#include <mvmfp.h>
+#include <mv_recovery.h>
+#include <asm/arch/mfp.h>
+#include <malloc.h>
+#include <usb.h>
+#include <power/pmic.h>
+#include <power/marvell88pm_pmic.h>
+#include <power/pxa1928_freq.h>
+#include <asm/gpio.h>
+#include <linux/usb/mv-phy.h>
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#endif
+#include "../common/cmdline.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DVC_CONTROL_REG	0x4F
+/*two dvc control register bits can support 4 control level
+4(control level) * 4 (DVC level registers) can support 16level DVC*/
+#define DVC_SET_ADDR1	(1 << 0)
+#define DVC_SET_ADDR2	(1 << 1)
+#define DVC_CTRl_LVL	4
+
+#define PMIC_I2C_BUS 0
+#define FG_I2C_BUS 0
+
+unsigned int mv_profile = 0xFF;
+/* Define CPU/DDR default max frequency
+   CPU: 1300MHz
+   DDR: 528MHz
+   GC3D: 624MHz
+   GC2D: 312MHz
+*/
+#define CPU_MAX_FREQ_DEFAULT	1300
+#define DDR_MAX_FREQ_DEFAULT	528
+#define GC3D_MAX_FREQ_DEFAULT	624
+#define GC2D_MAX_FREQ_DEFAULT	312
+/* Define CPU/DDR max frequency
+   CPU: 1508MHz
+   GC3D: 797MHz
+   GC2D: 416MHz
+*/
+#define CPU_MAX_FREQ	1508
+#define GC3D_MAX_FREQ	797
+#define GC2D_MAX_FREQ   416
+
+static int highperf;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* UART3 */
+		UART3_RXD_MMC2_DAT7_MFP33,
+		UART3_TXD_MMC2_DAT6_MFP34,
+		/* TWSI */
+		PWR_SCL_MFP67,
+		PWR_SDA_MFP68,
+		TWSI6_SCL_MMC2_DAT5_MFP35,
+		TWSI6_SDA_MMC2_DAT4_MFP36,
+		/* eMMC */
+		MMC3_DAT0_ND_IO8_MFP87,
+		MMC3_DAT1_ND_IO9_MFP86,
+		MMC3_DAT2_ND_IO10_MFP85,
+		MMC3_DAT3_ND_IO11_MFP84,
+		MMC3_DAT4_ND_IO12_MFP83,
+		MMC3_DAT5_ND_IO13_MFP82,
+		MMC3_DAT6_ND_IO14_MFP81,
+		MMC3_DAT7_ND_IO15_MFP80,
+		MMC3_CLK_SM_ADVMUX_MFP88,
+		MMC3_CMD_SM_RDY_MFP89,
+		MMC3_RST_ND_CLE_MFP90,
+		/* DVC pin */
+		DVC_PIN0_MFP107,
+		DVC_PIN1_MFP108,
+		DVC_PIN2_MFP99,
+		DVC_PIN3_MFP103,
+		GPIO17_OUT_MFP17,
+
+		GPIO125_MFP125,
+		GPIO134_MFP134,
+		GPIO135_MFP135,
+		VCXO_REQ_MFP77,
+		VCXO_OUT_MFP78,
+		GPIO0_MFP0,
+		GPIO2_MFP2,
+
+		GPIO3_MFP3,
+		GPIO132_MFP132,
+		GPIO9_IN_MFP9,
+
+		/*End of configureation*/
+		MFP_EOC
+	};
+	mfp_config(mfp_cfg);
+
+	gpio_direction_output(125,0);	/* Select HSCI to USB USB */
+	gpio_direction_output(17,0);	/* HSIC mux output enable */
+
+	gpio_direction_output(0, 0); 	/* Reset USB Hub */
+	gpio_direction_output(2, 1);	/* Disable USB Hub Vbus */
+	gpio_direction_output(135,1);	/* Enable USB Hub Connect */
+	gpio_direction_output(134, 1);	/* Enable USB Hub 26MHz */
+
+	gpio_direction_output(132, 0);	/* DSI mux select HDMI */
+	gpio_direction_output(3, 0);	/* DSI mux output enable */
+
+	/* Enable 26MHz clock out for USB hub */
+	writel(0x100, 0xd4050018);
+
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+        return 0;
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+	int chrg_type = mrvl_usb_phy_28nm_charger_detect(CONFIG_USB_PHY_BASE);
+	return !(chrg_type == DCP_CHARGER || chrg_type == NULL_CHARGER);
+}
+
+int board_init(void)
+{
+	/* Reset USB hub */
+	gpio_direction_output(0, 0);
+	mdelay(1);
+	gpio_direction_output(0, 1);
+	gpio_direction_output(2, 0);	// Enable USB Hub Vbus
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *devtree, bd_t *bd)
+{
+	char cmd[128];
+
+	/* set dtb addr */
+	sprintf(cmd, "fdt addr 0x%p", devtree);
+	run_command(cmd, 0);
+
+	/* pass profile number */
+	sprintf(cmd, "fdt set /profile marvell,profile-number <%d>\n", mv_profile);
+	run_command(cmd, 0);
+
+	/*
+	 * we use 1926 pp table by default, if if sethighperf cmd is set,
+	 * use pxa1928 pp instead.
+	 */
+	if (highperf)
+		run_command("fdt set /pp_version version pxa1928", 0);
+
+	/* update dtb so as not to enable ICU for B0 stepping */
+	run_command("fdt set /pxa1928_apmu_ver version bx", 0);
+	run_command("fdt rm /soc/axi/wakeupgen@d4284000", 0);
+}
+#endif
+
+#ifndef CONFIG_GLB_SECURE_EN
+#define SOC_POWER_POINT_ADDR0	0xD4292AAC
+#define SOC_POWER_POINT_ADDR1	0xD4292AB0
+static int svt_profile_map_table[] = {
+	999, 445, 433, 421, 408, 395, 383, 371,
+	358, 358, 333, 333, 309, 309, 1,
+};
+void show_dro(void)
+{
+	u32 val0, val1;
+	int lvt, nlvt, nsvt, svt;
+	int i;
+
+	val0 = readl(SOC_POWER_POINT_ADDR0);
+	val1 = readl(SOC_POWER_POINT_ADDR1);
+	lvt = val0 & 0x7FF;
+	nlvt = (val0 & 0x3FF800) >> 11;
+	nsvt = ((val1 & 0x1) << 10) | ((val0 & 0xFFC00000) >> 22);
+	svt = (val1 & 0xFFE) >> 1;
+	printf("----show dro----\n");
+	printf("LVT NUMBER: %d\n", lvt);
+	printf("NLVT NUMBER: %d\n", nlvt);
+	printf("NSVT NUMBER: %d\n", nsvt);
+	printf("SVT NUMBER: %d\n", svt);
+	printf("----------------\n");
+
+	for (i = 1; i < 15; i++) {
+		if (svt >= svt_profile_map_table[i] &&
+			svt < svt_profile_map_table[i - 1])
+			break;
+	}
+	mv_profile = i + 1;
+	if (mv_profile >= 15 || mv_profile < 0)
+		mv_profile = 0;
+	printf("SoC Profile Number: %d\n", mv_profile);
+}
+#endif
+
+static int do_sethighperf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *cmdline;
+	char *ep;
+	unsigned int new_set;
+	static unsigned int old_set;
+	u32 cpu_max = CPU_MAX_FREQ_DEFAULT;
+	u32 ddr_max = DDR_MAX_FREQ_DEFAULT;
+	u32 gc3d_max = GC3D_MAX_FREQ_DEFAULT;
+	u32 gc2d_max = GC2D_MAX_FREQ_DEFAULT;
+
+	if (argc != 2) {
+		printf("usage: sethighperf 0 or 1 to enable low or high performance\n");
+		return -1;
+	}
+	new_set = simple_strtoul((const char *)argv[1], &ep, 10);
+	if (new_set != 0 && new_set != 1) {
+		printf("usage: sethighperf 0 or 1 to enable low or high performance\n");
+		return -1;
+	}
+	if (old_set != new_set) {
+		if (new_set == 1)
+			highperf = 1;
+		else if (new_set == 0)
+			highperf = 0;
+
+		old_set = new_set;
+		cmdline = malloc(COMMAND_LINE_SIZE);
+		strncpy(cmdline, getenv("bootargs"), COMMAND_LINE_SIZE);
+		remove_cmdline_param(cmdline, "cpu_max=");
+		remove_cmdline_param(cmdline, "ddr_max=");
+		remove_cmdline_param(cmdline, "gc3d_max=");
+		remove_cmdline_param(cmdline, "gc2d_max=");
+		if (1 == new_set) {
+			cpu_max = CPU_MAX_FREQ;
+			gc3d_max = GC3D_MAX_FREQ;
+			gc2d_max = GC2D_MAX_FREQ;
+		}
+		sprintf(cmdline + strlen(cmdline), " cpu_max=%u000", cpu_max);
+		sprintf(cmdline + strlen(cmdline), " ddr_max=%u000", ddr_max);
+		sprintf(cmdline + strlen(cmdline), " gc3d_max=%u000", gc3d_max);
+		sprintf(cmdline + strlen(cmdline), " gc2d_max=%u000", gc2d_max);
+		setenv("bootargs", cmdline);
+		free(cmdline);
+	}
+	printf("sethighperf success\n");
+	return 0;
+}
+
+U_BOOT_CMD(
+	sethighperf, 3, 0, do_sethighperf,
+	"Setting cpu, ddr frequence for high performance or low performance",
+	""
+);
+
+static void set_limit_max_frequency(unsigned int type, u32 max)
+{
+	char *cmdline;
+	char *rem;
+	const char *add;
+	u32 max_default;
+	u32 max_preferred;
+
+	switch (type) {
+	case SKU_CPU_MAX_PREFER:
+		rem = "cpu_max=";
+		add = " cpu_max=%u000";
+		max_default = CPU_MAX_FREQ_DEFAULT;
+		break;
+
+	case SKU_DDR_MAX_PREFER:
+		rem = "ddr_max=";
+		add = " ddr_max=%u000";
+		max_default = DDR_MAX_FREQ_DEFAULT;
+		break;
+
+	case SKU_GC3D_MAX_PREFER:
+		rem = "gc3d_max=";
+		add = " gc3d_max=%u000";
+		max_default = GC3D_MAX_FREQ_DEFAULT;
+		break;
+
+	case SKU_GC2D_MAX_PREFER:
+		rem = "gc2d_max=";
+		add = " gc2d_max=%u000";
+		max_default = GC2D_MAX_FREQ_DEFAULT;
+		break;
+
+	default:
+		return;
+	}
+
+	if (0 == max)
+		max = max_default;
+
+	max_preferred = get_sku_max_setting(type);
+	if (0 == max_preferred)
+		max_preferred = min(max_default, max);
+	else
+		max_preferred = min(max_preferred, max);
+
+	cmdline = malloc(COMMAND_LINE_SIZE);
+	strncpy(cmdline, getenv("bootargs"), COMMAND_LINE_SIZE);
+	remove_cmdline_param(cmdline, rem);
+	sprintf(cmdline + strlen(cmdline), add, max_preferred);
+	setenv("bootargs", cmdline);
+	free(cmdline);
+}
+
+#if defined(CONFIG_PXA1928_DFC)
+static u32 get_ddr_type(void)
+{
+	if (((readl(0xd0000300) >> 4) & 0xf) == 0xa) /* lpddr3 */
+		if (((readl(0xd0000200) >> 16) & 0x1f) == 0xd) /* 1GB */
+			return 1;
+		else if (((readl(0xd0000210) >> 8) & 0xf) == 0x5)/* Hynix 2GB */
+			return readl(0xD4282C98) ? 4 : 2; /* 4 for dis, 2 for pop */
+		else /* Elpida 2GB */
+			return 3;
+	else /* lpddr2 */
+		return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+#if defined(CONFIG_PXA1928_DFC)
+	u32 ddr_type;
+	ddr_type = get_ddr_type();
+#endif
+
+	/* set cpu, gc3d, gc2d  max frequency */
+	set_limit_max_frequency(SKU_CPU_MAX_PREFER, CPU_MAX_FREQ);
+	set_limit_max_frequency(SKU_GC3D_MAX_PREFER, GC3D_MAX_FREQ);
+	set_limit_max_frequency(SKU_GC2D_MAX_PREFER, GC2D_MAX_FREQ);
+
+#ifndef CONFIG_GLB_SECURE_EN
+	show_dro();
+#endif
+	/*
+	 * bus 0 is used by pmic, set here for debug with
+	 * "i2c probe", this should be the called just before exit,
+	 * in case the default bus number is changed
+	 */
+	i2c_set_bus_num(0);
+
+#if defined(CONFIG_PXA1928_DFC)
+	pxa1928_fc_init(ddr_type);
+
+	run_command("setcpurate 624", 0);
+	run_command("setddrrate hwdfc 312", 0);
+	run_command("setaxirate 156", 0);
+#endif
+
+	srand(get_ticks());
+
+	return 0;
+}
+
+#ifdef CONFIG_MV_SDHCI
+ /* eMMC: BUCK2/VCC_IO_NAND(1.8v)->eMMC(vmmcq), LDO4/V3P3_NAND(2.8v)->eMMC(vmmc) (default on)
+ * SD: LDO6/VCC_IO_MMC1(3.3v)->SD(vmmcq), LDO10/V_MMC_CARD(3.3v)->SD(vmmc) (default off)
+ */
+int board_mmc_init(bd_t *bd)
+{
+	ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+	u8 i;
+	u32 val;
+
+	for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+		if (mv_sdh_init(mmc_base_address[i], 104000000, 0,
+				SDHCI_QUIRK_32BIT_DMA_ADDR))
+			return 1;
+		/*
+		 * use default hardware clock gating
+		 * by default, SD_FIFO_PARM = 0x70005
+		 */
+		if (i == 0) {
+			/*
+			 * emmc need to tune RX/TX under HS50
+			 * RX need to set proper delays cycles.
+			 * TX can work just invert the internal clock (TX_CFG_REG[30])
+			 * but also set the delay cycles here for safety.
+			 */
+			writel(TX_MUX_DLL | TX_HOLD_DELAY0(0x16A),
+						mmc_base_address[i] + TX_CFG_REG);
+			writel(SDCLK_DELAY(0xA0) | SDCLK_SEL1(0x1),
+						mmc_base_address[i] + RX_CFG_REG);
+		} else {
+			/*
+			 * sd card can work under HS50 by default.
+			 * but also invert TX internal clock (TX_CFG_REG[30]) here for safety.
+			 */
+			val = readl(mmc_base_address[i] + TX_CFG_REG);
+			val |= TX_INT_CLK_INV;
+			writel(val, mmc_base_address[i] + TX_CFG_REG);
+		}
+	}
+
+	return 0;
+}
+#endif
+
+void reset_cpu(ulong ignored)
+{
+#ifdef CONFIG_POWER_88PM860
+	printf("pxa1928 board rebooting...\n");
+	pmic_reset_bd();
+#endif
+}
+
+#ifdef CONFIG_POWER_88PM860
+void board_pmic_power_fixup(struct pmic *p_power)
+{
+	u32 val;
+	unsigned int mask, dvc_ctrl;
+
+	/* enable buck1 dual phase mode */
+	pmic_reg_read(p_power, 0x8e, &val);
+	val |= (1 << 2);
+	pmic_reg_write(p_power, 0x8e, val);
+
+	/* set buck1 all the DVC register 16 levels all at 1.2v
+	 * dvc_ctrl is the value of the two dvc control bits
+	 */
+	for (dvc_ctrl = 0; dvc_ctrl < DVC_CTRl_LVL; dvc_ctrl++) {
+		pmic_reg_read(p_power, DVC_CONTROL_REG, &val);
+		mask = (DVC_SET_ADDR1 | DVC_SET_ADDR2);
+		val &= ~mask;
+		val |= dvc_ctrl & mask;
+		pmic_reg_write(p_power, DVC_CONTROL_REG, val);
+
+		val = 0x30;
+		pmic_reg_write(p_power, 0x3c, val);
+		pmic_reg_write(p_power, 0x3d, val);
+		pmic_reg_write(p_power, 0x3e, val);
+		pmic_reg_write(p_power, 0x3f, val);
+
+		pmic_reg_write(p_power, 0x4b, val);
+		pmic_reg_write(p_power, 0x4c, val);
+		pmic_reg_write(p_power, 0x4d, val);
+		pmic_reg_write(p_power, 0x4e, val);
+
+		/* set buck3 all the DVC register at 1.2v */
+		val = 0x30;
+		pmic_reg_write(p_power, 0x41, val);
+		pmic_reg_write(p_power, 0x42, val);
+		pmic_reg_write(p_power, 0x43, val);
+		pmic_reg_write(p_power, 0x44, val);
+
+		/* set buck5 all the DVC register at 3.3v for WIB_SYS */
+		val = 0x72;
+		pmic_reg_write(p_power, 0x46, val);
+		pmic_reg_write(p_power, 0x47, val);
+		pmic_reg_write(p_power, 0x48, val);
+		pmic_reg_write(p_power, 0x49, val);
+	}
+}
+#endif
+
+__weak int power_init_common(void) {return -1; }
+__weak int pmic_init(unsigned char bus) {return -1; }
+int power_init_board(void)
+{
+	/* init PMIC  */
+	if (pmic_init(PMIC_I2C_BUS))
+		return -1;
+	if (power_init_common()) {
+		printf("%s: init pmic fails.\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int res = -1;
+
+#if defined(CONFIG_CI_UDC)
+	if (usb_eth_initialize(bis) >= 0)
+		res = 0;
+#endif
+	return res;
+}
+#endif
diff --git a/configs/pxa1928_helium_defconfig b/configs/pxa1928_helium_defconfig
new file mode 100644
index 0000000000..175b5db49f
--- /dev/null
+++ b/configs/pxa1928_helium_defconfig
@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_PXA1928HELIUM=y
diff --git a/include/configs/pxa1928_helium.h b/include/configs/pxa1928_helium.h
new file mode 100644
index 0000000000..b965a46995
--- /dev/null
+++ b/include/configs/pxa1928_helium.h
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_PXA1928_H
+#define __CONFIG_PXA1928_H
+
+#define CONFIG_ARM64
+#define CONFIG_REMAKE_ELF
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_PXA1928
+#define CONFIG_SYS_TEXT_BASE            0x9000000
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_88PM860
+#define CONFIG_PXA1928_POWER
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Generic Timer Definitions for arm timer */
+#define COUNTER_FREQUENCY              (0x340000)     /* 3.25MHz */
+#define SECONDARY_CPU_MAILBOX           0x01210000
+
+#define CPU_RELEASE_ADDR		0xffffffff /* should not be touched */
+
+#define CONFIG_SMP
+
+#define CONFIG_SYS_SDRAM_BASE           0
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define CONFIG_SRAM_BASE                0xd1020000
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SRAM_BASE + 0x1000)
+#define CONFIG_SYS_RELOC_END            0x09700000
+
+#define CONFIG_TZ_HYPERVISOR_SIZE       (0x01200000)
+
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_RANDOM_UUID
+#define CONFIG_CMD_UUID
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MFP
+#define CONFIG_CMD_MIPS
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_FS_EXT4
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_MRVL_USB_PHY 1
+#define CONFIG_MRVL_USB_PHY_28LP 1
+#define CONFIG_CI_UDC
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_CMD_BOOTI
+
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_PXA
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW     0
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_G_DNL_VENDOR_NUM         0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM        0xd022
+#define CONFIG_G_DNL_MANUFACTURER       "Marvell"
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR    0x10000000
+#define CONFIG_USB_FASTBOOT_BUF_SIZE    0x20000000
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV	0
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_ARCH_MISC_INIT
+
+/*
+ * Boot setting
+ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BOOTARGS \
+	"rw console=ttyS0,115200 panic_debug uart_dma"
+
+#define CONFIG_BOOTCOMMAND \
+	"while true; do " \
+	"mmc read ${fdt_addr_r} 0x10000 0x1000; " \
+	"fastboot; " \
+	"mmc read ${fdt_addr_r} 0x10000 0x1000; " \
+	"mmc read ${kernel_addr_r} 0x8000 0x8000 && " \
+	"bootm ${kernel_addr_r} ${kernel_addr_r} ${fdt_addr_r};" \
+	"done"
+
+#define CONFIG_MMC_BOOT_DEV     "mmc dev 0 0"
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_MMC		/* save env in MMV */
+#define CONFIG_SYS_MMC_ENV_DEV	0	/* save env in eMMC */
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_SIZE		0x8000		/* env size set to 32KB */
+#define CONFIG_ENV_OFFSET	(0x1000000 - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_HUSH_PARSER
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+        "autostart=yes\0" \
+        "verify=yes\0" \
+        "cdc_connect_timeout=60\0" \
+	"fdt_addr_r=0x03000000\0" \
+	"kernel_addr_r=0x0127f800\0" \
+	"partitions=" \
+	"name=DTIM,start=0x00200000,size=0x200000;" \
+	"name=recovery,start=0x00400000,size=0xb00000;" \
+	"name=bootloader,start=0x00F00000,size=0x100000;" \
+	"name=boot,start=0x01000000,size=0x1000000;" \
+	"name=dtb,start=0x02000000,size=0x1000000;" \
+	"name=system,start=0x03000000,size=0x30000000;" \
+	"name=vendor,start=0x33000000,size=0x10000000;" \
+	"name=cache,start=0x43000000,size=0x20000000;" \
+	"name=userdata,start=0x63000000,size=0x15d000000\0"
+
+/* Marvell PXAV3 MMC Controller Configuration */
+#define CONFIG_SDHCI_PXAV3
+#define CONFIG_DDR_HW_DFC
+
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_PXA1928_DFC
+#define CONFIG_PXA1928_LPM
+#define CONFIG_PXA1928_COMM_D2
+
+#endif	/* __CONFIG_PXA1928_H */