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authorCaleb Connolly <caleb.connolly@linaro.org>2023-12-11 16:02:20 +0000
committerCaleb Connolly <caleb.connolly@linaro.org>2023-12-11 16:02:20 +0000
commit00bd731671c00306c13fe642a75c4f67a07be386 (patch)
treeb8c6129eda69144e7645b8beba7653382e52ac7e
parente964a0febec9140e76c4e1b154606f13e0913e9c (diff)
fixup! mach-snapdragon: generalise board support
-rw-r--r--arch/arm/mach-snapdragon/board.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 9bd9bcad77..2aac2508f8 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -38,16 +38,13 @@ int dram_init(void)
int dram_init_banksize(void)
{
- int ret;
+ int ret, i;
phys_addr_t start, size;
ret = fdtdec_setup_memory_banksize();
if (ret < 0)
return ret;
- if (WARN(CONFIG_NR_DRAM_BANKS < 2, "CONFIG_NR_DRAM_BANKS should be at least 2"))
- return 0;
-
/* Some bootloaders populate the RAM banks in the wrong order -_- */
start = gd->bd->bi_dram[1].start;
size = gd->bd->bi_dram[1].size;
@@ -59,6 +56,17 @@ int dram_init_banksize(void)
gd->bd->bi_dram[0].size = size;
}
+ for (i = 0; gd->bd->bi_dram[i].size; i++) {
+ size = ALIGN(gd->bd->bi_dram[i].size, SZ_4K);
+ /*
+ * If you're filling out the /memory node manually, the size value should
+ * end in 3 zeros. Better yet, let ABL populate it for you.
+ */
+ WARN_ONCE(gd->bd->bi_dram[i].size != size,
+ "\nDRAM bank %d size not aligned to 4K! Patching things up...\n", i);
+ gd->bd->bi_dram[i].size = size;
+ }
+
return 0;
}