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/* SPDX-License-Identifier: GPL-2.0 */
/*
* ZynqMP DPSUB Subsystem Driver
*
* Copyright (C) 2017 - 2020 Xilinx, Inc.
*
* Authors:
* - Hyun Woo Kwon <hyun.kwon@xilinx.com>
* - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#ifndef _ZYNQMP_DPSUB_H_
#define _ZYNQMP_DPSUB_H_
#include <drm/drm_crtc.h>
#include <drm/drm_encoder.h>
struct clk;
struct device;
struct drm_bridge;
struct drm_device;
struct zynqmp_disp;
struct zynqmp_dp;
enum zynqmp_dpsub_format {
ZYNQMP_DPSUB_FORMAT_RGB,
ZYNQMP_DPSUB_FORMAT_YCRCB444,
ZYNQMP_DPSUB_FORMAT_YCRCB422,
ZYNQMP_DPSUB_FORMAT_YONLY,
};
/**
* struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
* @drm: The DRM/KMS device
* @dev: The physical device
* @apb_clk: The APB clock
* @vid_clk: Video clock
* @vid_clk_from_ps: True of the video clock comes from PS, false from PL
* @aud_clk: Audio clock
* @aud_clk_from_ps: True of the audio clock comes from PS, false from PL
* @crtc: The DRM CRTC
* @encoder: The dummy DRM encoder
* @bridge: The DP encoder bridge
* @disp: The display controller
* @dp: The DisplayPort controller
* @dma_align: DMA alignment constraint (must be a power of 2)
*/
struct zynqmp_dpsub {
struct drm_device drm;
struct device *dev;
struct clk *apb_clk;
struct clk *vid_clk;
bool vid_clk_from_ps;
struct clk *aud_clk;
bool aud_clk_from_ps;
struct drm_crtc crtc;
struct drm_encoder encoder;
struct drm_bridge *bridge;
struct zynqmp_disp *disp;
struct zynqmp_dp *dp;
unsigned int dma_align;
};
static inline struct zynqmp_dpsub *to_zynqmp_dpsub(struct drm_device *drm)
{
return container_of(drm, struct zynqmp_dpsub, drm);
}
bool zynqmp_dpsub_audio_enabled(struct zynqmp_dpsub *dpsub);
unsigned int zynqmp_dpsub_get_audio_clk_rate(struct zynqmp_dpsub *dpsub);
#endif /* _ZYNQMP_DPSUB_H_ */
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