From b542683d77b4f56cef0221b267c341616d87bce9 Mon Sep 17 00:00:00 2001 From: "Emilio G. Cota" Date: Mon, 19 Feb 2018 20:51:58 -0500 Subject: translator: merge max_insns into DisasContextBase MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While at it, use int for both num_insns and max_insns to make sure we have same-type comparisons. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael Clark Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'target/arm/translate.c') diff --git a/target/arm/translate.c b/target/arm/translate.c index 0f6629f745..731cf327a1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12243,8 +12243,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) return !thumb_insn_is_16bit(s, insn); } -static int arm_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cs, int max_insns) +static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cs->env_ptr; @@ -12305,14 +12304,14 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, /* If architectural single step active, limit to 1. */ if (is_singlestepping(dc)) { - max_insns = 1; + dc->base.max_insns = 1; } /* ARM is a fixed-length ISA. Bound the number of insns to execute to those left on the page. */ if (!dc->thumb) { int bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; - max_insns = MIN(max_insns, bound); + dc->base.max_insns = MIN(dc->base.max_insns, bound); } cpu_F0s = tcg_temp_new_i32(); @@ -12323,8 +12322,6 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, cpu_V1 = cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 = tcg_temp_new_i64(); - - return max_insns; } static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) -- cgit v1.2.3