From 6e937ba7f8fb90d66cb3781f7fed32fb4239556a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sun, 21 Feb 2021 23:26:15 +0100 Subject: target/arm: Restrict v8M IDAU to TCG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IDAU is specific to M-profile. KVM only supports A-profile. Restrict this interface to TCG, as it is pointless (and confusing) on a KVM-only build. Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Message-id: 20210221222617.2579610-2-f4bug@amsat.org Signed-off-by: Peter Maydell --- target/arm/cpu_tcg.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'target/arm/cpu_tcg.c') diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index c29b434c60..fb07a33693 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -14,6 +14,7 @@ #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ #include "internals.h" +#include "target/arm/idau.h" /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -739,10 +740,17 @@ static const ARMCPUInfo arm_tcg_cpus[] = { { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, }; +static const TypeInfo idau_interface_type_info = { + .name = TYPE_IDAU_INTERFACE, + .parent = TYPE_INTERFACE, + .class_size = sizeof(IDAUInterfaceClass), +}; + static void arm_tcg_cpu_register_types(void) { size_t i; + type_register_static(&idau_interface_type_info); for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { arm_cpu_register(&arm_tcg_cpus[i]); } -- cgit v1.2.3