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AgeCommit message (Expand)Author
2021-05-11target/riscv: Fix the RV64H decode commentAlistair Francis
2021-05-11target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis
2021-05-11target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis
2021-05-11target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis
2021-05-11target/riscv: fix a typo with interrupt namesEmmanuel Blot
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot
2021-05-11target/riscv: fix vrgather macro index variable type bugFrank Chang
2021-05-11target/riscv: Add ePMP support for the Ibex CPUAlistair Francis
2021-05-11target/riscv/pmp: Remove outdated commentAlistair Francis
2021-05-11target/riscv: Add a config option for ePMPHou Weiying
2021-05-11target/riscv: Implementation of enhanced PMP (ePMP)Hou Weiying
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying
2021-05-11target/riscv: Add the ePMP featureAlistair Francis
2021-05-11target/riscv: Define ePMP mseccfgHou Weiying
2021-05-11target/riscv: Fix the PMP is locked check when using TORAlistair Francis
2021-05-11target/riscv: Fixup saturate subtract functionLIU Zhiwei
2021-05-11riscv: don't look at SUM when accessing memory from a debugger contextJade Fink
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis
2021-05-11target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis
2021-05-11target/riscv: Add Shakti C class CPUVijai Kumar K
2021-05-11target/riscv: Align the data type of reset vector addressDylan Jhong
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth
2021-03-22target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer
2021-03-22target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer
2021-03-22target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer
2021-03-22target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer
2021-03-22target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer
2021-03-22target/riscv: flush TLB pages if PMP permission has been changedJim Shu
2021-03-22target/riscv: add log of PMP permission checkingJim Shu
2021-03-22target/riscv: propagate PMP permission to TLB pageJim Shu
2021-03-22target/riscv: fix vs() to return proper error codeFrank Chang
2021-03-11Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...Peter Maydell
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé
2021-03-09Various spelling fixesMichael Tokarev
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana
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