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AgeCommit message (Expand)Author
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li
2022-02-16target/riscv: add support for svinval extensionWeiwei Li
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li
2022-02-16target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel
2022-02-16target/riscv: Implement AIA IMSIC interface CSRsAnup Patel
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel
2022-02-16target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel
2022-02-16target/riscv: Implement AIA interrupt filtering CSRsAnup Patel
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel
2022-02-16target/riscv: Add defines for AIA CSRsAnup Patel
2022-02-16target/riscv: Add AIA cpu featureAnup Patel
2022-02-16target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel
2022-02-16target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-modeAnup Patel
2022-02-16target/riscv: Fix vill field write in vtypeLIU Zhiwei
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich
2022-02-16target/riscv: iterate over a table of decodersPhilipp Tomsich
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich
2022-02-16target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptrPhilipp Tomsich
2022-02-16target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...Philipp Tomsich
2022-02-16target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei
2022-01-21target/riscv: Set default XLEN for hypervisorLIU Zhiwei
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei
2022-01-21target/riscv: Adjust vector address with maskLIU Zhiwei
2022-01-21target/riscv: Fix check range for first fault onlyLIU Zhiwei
2022-01-21target/riscv: Remove VILL field in VTYPELIU Zhiwei
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei
2022-01-21target/riscv: Alloc tcg global for cur_pm[mask|base]LIU Zhiwei
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei
2022-01-21target/riscv: Relax debug check for pm writeLIU Zhiwei
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei
2022-01-21target/riscv: Extend pc for runtime pc writeLIU Zhiwei
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei
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