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path: root/target-arm/translate.c
AgeCommit message (Expand)Author
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée
2014-03-17target-arm: A64: Implement PMULL instructionPeter Maydell
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber
2014-03-10target-arm: Implement WFE as a yield operationpull-target-arm-20140310Peter Maydell
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton
2014-02-20target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell
2014-02-20target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell
2014-02-08target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton
2014-01-31target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTMWill Newton
2014-01-31target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTMWill Newton
2014-01-31target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZWill Newton
2014-01-31target-arm: Add support for AArch32 SIMD VRINTXWill Newton
2014-01-31target-arm: Add support for AArch32 FP VRINTXWill Newton
2014-01-31target-arm: Add support for AArch32 FP VRINTZWill Newton
2014-01-31target-arm: Add support for AArch32 FP VRINTRWill Newton
2014-01-31target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTMWill Newton
2014-01-08target-arm: Rename A32 VFP conversion helpersWill Newton
2014-01-08target-arm: Use VFP_BINOP macro for min, max, minnum, maxnumPeter Maydell
2014-01-08target-arm: Widen exclusive-access support struct fields to 64 bitsPeter Maydell
2014-01-07target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoderPeter Maydell
2013-12-17target-arm: A64: add support for conditional branchesAlexander Graf
2013-12-17target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()Peter Maydell
2013-12-17target-arm: add support for v8 AES instructionsArd Biesheuvel
2013-12-10target-arm: Use new qemu_ld/st opcodesRichard Henderson
2013-12-10target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.Will Newton
2013-12-10target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.Will Newton
2013-12-10target-arm: Implement ARMv8 VSEL instruction.Will Newton
2013-12-10target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.Will Newton
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson
2013-09-10target-arm: Add AArch64 translation stubAlexander Graf
2013-09-10target-arm: Prepare translation for AArch64 codeAlexander Graf
2013-09-10target-arm: Pass DisasContext* to gen_set_pc_im()Peter Maydell
2013-09-10target-arm: Fix target_ulong/uint32_t confusionsAlexander Graf
2013-09-10target-arm: Export cpu_envAlexander Graf
2013-09-10target-arm: Extract the disas struct to a header fileAlexander Graf
2013-09-10target-arm: Abstract out load/store from a vaddr in AArch32Peter Maydell
2013-09-10target-arm: Use sextract32() in branch decodePeter Maydell
2013-09-03Merge remote-tracking branch 'mjt/trivial-patches' into stagingAnthony Liguori
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson
2013-09-01target-arm: Report unimplemented opcodes (LOG_UNIMP)Stefan Weil
2013-08-20target-arm: Support coprocessor registers which do I/OPeter Maydell
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber
2013-07-15target-arm: explicitly decode SEVL instructionMans Rullgard
2013-07-15target-arm: implement LDA/STL instructionsMans Rullgard
2013-07-15target-arm: add feature flag for ARMv8Mans Rullgard
2013-07-09target-arm: Change gen_intermediate_code_internal() argument to ARMCPUAndreas Färber
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber
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