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authorRichard Henderson <richard.henderson@linaro.org>2024-03-05 06:39:31 -1000
committerPeter Maydell <peter.maydell@linaro.org>2024-03-07 12:49:16 +0000
commitd572bcb222010b38b382871a23b2f38e2c3f4d2d (patch)
tree834c1a8de70a4fcfee1ea74b660b33eb0c2c3117 /tests
parentddcc4b4b5250f800d500ef1217b28c39812bac2a (diff)
target/arm: Fix 32-bit SMOPA
While the 8-bit input elements are sequential in the input vector, the 32-bit output elements are not sequential in the output matrix. Do not attempt to compute 2 32-bit outputs at the same time. Cc: qemu-stable@nongnu.org Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240305163931.242795-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests')
-rw-r--r--tests/tcg/aarch64/Makefile.target2
-rw-r--r--tests/tcg/aarch64/sme-smopa-1.c47
-rw-r--r--tests/tcg/aarch64/sme-smopa-2.c54
3 files changed, 102 insertions, 1 deletions
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index cded1d01fc..ea3e232e65 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -67,7 +67,7 @@ endif
# SME Tests
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
-AARCH64_TESTS += sme-outprod1
+AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
endif
# System Registers Tests
diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-1.c
new file mode 100644
index 0000000000..c62d5e0007
--- /dev/null
+++ b/tests/tcg/aarch64/sme-smopa-1.c
@@ -0,0 +1,47 @@
+#include <stdio.h>
+#include <string.h>
+
+int main()
+{
+ static const int cmp[4][4] = {
+ { 110, 134, 158, 182 },
+ { 390, 478, 566, 654 },
+ { 670, 822, 974, 1126 },
+ { 950, 1166, 1382, 1598 }
+ };
+ int dst[4][4];
+ int *tmp = &dst[0][0];
+
+ asm volatile(
+ ".arch armv8-r+sme\n\t"
+ "smstart\n\t"
+ "index z0.b, #0, #1\n\t"
+ "movprfx z1, z0\n\t"
+ "add z1.b, z1.b, #16\n\t"
+ "ptrue p0.b\n\t"
+ "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t"
+ "ptrue p0.s, vl4\n\t"
+ "mov w12, #0\n\t"
+ "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t"
+ "smstop"
+ : "+r"(tmp) : : "memory");
+
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
+ return 0;
+ }
+
+ /* See above for correct results. */
+ for (int i = 0; i < 4; ++i) {
+ for (int j = 0; j < 4; ++j) {
+ printf("%6d", dst[i][j]);
+ }
+ printf("\n");
+ }
+ return 1;
+}
diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c
new file mode 100644
index 0000000000..c9f48c3bfc
--- /dev/null
+++ b/tests/tcg/aarch64/sme-smopa-2.c
@@ -0,0 +1,54 @@
+#include <stdio.h>
+#include <string.h>
+
+int main()
+{
+ static const long cmp[4][4] = {
+ { 110, 134, 158, 182 },
+ { 390, 478, 566, 654 },
+ { 670, 822, 974, 1126 },
+ { 950, 1166, 1382, 1598 }
+ };
+ long dst[4][4];
+ long *tmp = &dst[0][0];
+ long svl;
+
+ /* Validate that we have a wide enough vector for 4 elements. */
+ asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl));
+ if (svl < 32) {
+ return 0;
+ }
+
+ asm volatile(
+ "smstart\n\t"
+ "index z0.h, #0, #1\n\t"
+ "movprfx z1, z0\n\t"
+ "add z1.h, z1.h, #16\n\t"
+ "ptrue p0.b\n\t"
+ "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t"
+ "ptrue p0.d, vl4\n\t"
+ "mov w12, #0\n\t"
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
+ "add %0, %0, #32\n\t"
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
+ "mov w12, #2\n\t"
+ "add %0, %0, #32\n\t"
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
+ "add %0, %0, #32\n\t"
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
+ "smstop"
+ : "+r"(tmp) : : "memory");
+
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
+ return 0;
+ }
+
+ /* See above for correct results. */
+ for (int i = 0; i < 4; ++i) {
+ for (int j = 0; j < 4; ++j) {
+ printf("%6ld", dst[i][j]);
+ }
+ printf("\n");
+ }
+ return 1;
+}