diff options
| author | Markus Armbruster <armbru@redhat.com> | 2019-06-04 20:16:18 +0200 |
|---|---|---|
| committer | Markus Armbruster <armbru@redhat.com> | 2019-06-12 13:20:21 +0200 |
| commit | f91005e195e7e1485e60cb121731589960f1a3c9 (patch) | |
| tree | e734135671b02f0c6bbf5785006401843e925a06 /tcg | |
| parent | 37677d7db39a3c250ad661d00fb7c3b59d047b1f (diff) | |
Supply missing header guards
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20190604181618.19980-5-armbru@redhat.com>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/tcg-gvec-desc.h | 5 | ||||
| -rw-r--r-- | tcg/tcg-op-gvec.h | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/tcg/tcg-gvec-desc.h b/tcg/tcg-gvec-desc.h index 2dda7d6ba1..0224ac3e78 100644 --- a/tcg/tcg-gvec-desc.h +++ b/tcg/tcg-gvec-desc.h @@ -17,6 +17,9 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ +#ifndef TCG_TCG_GVEC_DESC_H +#define TCG_TCG_GVEC_DESC_H + /* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */ #define SIMD_OPRSZ_SHIFT 0 #define SIMD_OPRSZ_BITS 5 @@ -47,3 +50,5 @@ static inline int32_t simd_data(uint32_t desc) { return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS); } + +#endif diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 2a9e0c7c0a..830d68f697 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -17,6 +17,9 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ +#ifndef TCG_TCG_OP_GVEC_H +#define TCG_TCG_OP_GVEC_H + /* * "Generic" vectors. All operands are given as offsets from ENV, * and therefore cannot also be allocated via tcg_global_mem_new_*. @@ -373,3 +376,5 @@ void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); + +#endif |