diff options
author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-02-18 08:34:14 +0100 |
---|---|---|
committer | Cédric Le Goater <clg@kaod.org> | 2022-02-18 08:34:14 +0100 |
commit | acd1f78870aca0b7f9e54d788b9bc3d36f80f01d (patch) | |
tree | 435c4b52a884d109db08c35ab8f8a4c2c482a83b /target | |
parent | 4ffb8c5e434195ce1d8a6bc148e6f4971d089258 (diff) |
target/ppc: cpu_init: Move 405 SPRs into register_405_sprs
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/ppc/cpu_init.c | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 53409a176a..c0990b43a2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1425,6 +1425,18 @@ static void register_405_sprs(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, spr_read_generic, &spr_write_generic, 0x00000000); + + /* Bus access control */ + /* not emulated, as QEMU never does speculative access */ + spr_register(env, SPR_40x_SGR, "SGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0xFFFFFFFF); + /* not emulated, as QEMU do not emulate caches */ + spr_register(env, SPR_40x_DCWR, "DCWR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); } @@ -2316,17 +2328,7 @@ static void init_proc_405(CPUPPCState *env) register_40x_sprs(env); register_405_sprs(env); register_usprgh_sprs(env); - /* Bus access control */ - /* not emulated, as QEMU never does speculative access */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); + /* Memory management */ #if !defined(CONFIG_USER_ONLY) env->nb_tlb = 64; |