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authorPeter Maydell <peter.maydell@linaro.org>2019-06-11 16:39:42 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-06-13 15:14:03 +0100
commit973751fd798d41402d34f9f705c0c6d1633d0cda (patch)
tree715898f29e0bf180140ab000989a82f682d75a73 /target
parent3de79d335c9aa7d726865e3933d9b21781032183 (diff)
target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max
At the moment our -cpu max for AArch32 supports VFP short-vectors because we always implement them, even for CPUs which should not have them. The following commits are going to switch to using the correct ID-register-check to enable or disable short vector support, so we need to turn it on explicitly for -cpu max, because Cortex-A15 doesn't implement it. We don't enable this for the AArch64 -cpu max, because the v8A architecture never supports short-vectors. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/arm/cpu.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c8441fc07b..2335659a85 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2023,6 +2023,10 @@ static void arm_max_initfn(Object *obj)
kvm_arm_set_cpu_features_from_host(cpu);
} else {
cortex_a15_initfn(obj);
+
+ /* old-style VFP short-vector support */
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+
#ifdef CONFIG_USER_ONLY
/* We don't set these in system emulation mode for the moment,
* since we don't correctly set (all of) the ID registers to