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authorPeter Maydell <peter.maydell@linaro.org>2021-05-20 16:28:40 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-06-03 16:43:25 +0100
commit7cda2149521f25b7caedd464f2e35104d9990315 (patch)
treecdf53b94448eedcef37c0d842135a109c925cdb4 /target/arm
parentb26b5629c0be4a9539833de4189184a224590d14 (diff)
target/arm: Allow board models to specify initial NS VTOR
Currently we allow board models to specify the initial value of the Secure VTOR register, using an init-svtor property on the TYPE_ARMV7M object which is plumbed through to the CPU. Allow board models to also specify the initial value of the Non-secure VTOR via a similar init-nsvtor property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210520152840.24453-10-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
-rw-r--r--target/arm/cpu.c10
-rw-r--r--target/arm/cpu.h2
2 files changed, 12 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ad65b60b04..9ad6f5911b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -327,6 +327,7 @@ static void arm_cpu_reset(DeviceState *dev)
env->regs[14] = 0xffffffff;
env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
+ env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80;
/* Load the initial SP and PC from offset 0 and 4 in the vector table */
vecbase = env->v7m.vecbase[env->v7m.secure];
@@ -1272,6 +1273,15 @@ void arm_cpu_post_init(Object *obj)
&cpu->init_svtor,
OBJ_PROP_FLAG_READWRITE);
}
+ if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
+ /*
+ * Initial value of the NS VTOR (for cores without the Security
+ * extension, this is the only VTOR)
+ */
+ object_property_add_uint32_ptr(obj, "init-nsvtor",
+ &cpu->init_nsvtor,
+ OBJ_PROP_FLAG_READWRITE);
+ }
qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c389b1e969..5f234834c0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -869,6 +869,8 @@ struct ARMCPU {
/* For v8M, initial value of the Secure VTOR */
uint32_t init_svtor;
+ /* For v8M, initial value of the Non-secure VTOR */
+ uint32_t init_nsvtor;
/* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
* QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.