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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-24 07:50:19 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-10-24 07:51:37 +0100 |
| commit | eabcd6faa90461e0b7463f4ebe75b8d050487c9c (patch) | |
| tree | 85b6e04ee8329421c14f475dd7c77054138a0202 /target/arm/translate.h | |
| parent | 246fa4aca95e213fba10c8222dbc6bd0a9a2a8d4 (diff) | |
target/arm: Use gvec for NEON_3R_LOGIC insns
Move expanders for VBSL, VBIT, and VBIF from translate-a64.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011205206.3552-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
| -rw-r--r-- | target/arm/translate.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h index 5bc15819c3..dea59c7214 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -191,6 +191,12 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } + +/* Vector operations shared between ARM and AArch64. */ +extern const GVecGen3 bsl_op; +extern const GVecGen3 bit_op; +extern const GVecGen3 bif_op; + /* * Forward to the isar_feature_* tests given a DisasContext pointer. */ |