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authorRichard Henderson <richard.henderson@linaro.org>2019-01-21 10:23:12 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-01-21 10:38:54 +0000
commit476a4692f06e381117fb7ad0d04d37c9c2612198 (patch)
treead1e04698d9f052f6f70f7caf62aa5dd0351f6a0 /target/arm/translate.h
parentba97be9f4a4ecaf16a1454dc669e5f3d935d3b63 (diff)
target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
We will shortly want to talk about TBI as it relates to data. Passing around a pair of variables is less convenient than a single variable. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
-rw-r--r--target/arm/translate.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h
index d8a8bb4e9c..bb37d35741 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -26,8 +26,7 @@ typedef struct DisasContext {
int user;
#endif
ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
- bool tbi0; /* TBI0 for EL0/1 or TBI for EL2/3 */
- bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */
+ uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */
bool ns; /* Use non-secure CPREG bank on access */
int fp_excp_el; /* FP exception EL or 0 if enabled */
int sve_excp_el; /* SVE exception EL or 0 if enabled */