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authorRichard Henderson <richard.henderson@linaro.org>2022-04-26 09:30:31 -0700
committerPeter Maydell <peter.maydell@linaro.org>2022-04-28 13:38:15 +0100
commit0b188ea05acb57b32604706a6f22d82121414ec9 (patch)
tree380b827adc6b082ddcf5323abd90cbb426db2ced /target/arm/translate.c
parent5b95562c50379ee7263fe60cc26ab05dce66ab49 (diff)
target/arm: Use tcg_constant in trans_CSEL
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.c')
-rw-r--r--target/arm/translate.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5ce23947a1..37fb17cdaa 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8982,13 +8982,14 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
}
/* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
+ zero = tcg_constant_i32(0);
if (a->rn == 15) {
- rn = tcg_const_i32(0);
+ rn = zero;
} else {
rn = load_reg(s, a->rn);
}
if (a->rm == 15) {
- rm = tcg_const_i32(0);
+ rm = zero;
} else {
rm = load_reg(s, a->rm);
}
@@ -9010,10 +9011,8 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
}
arm_test_cc(&c, a->fcond);
- zero = tcg_const_i32(0);
tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
arm_free_cc(&c);
- tcg_temp_free_i32(zero);
store_reg(s, a->rd, rn);
tcg_temp_free_i32(rm);