diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-04-30 14:27:39 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-05-10 13:24:09 +0100 |
| commit | b5c8a457fab78e08d0ab5f9ca242b85b31c72c87 (patch) | |
| tree | d8f991d33b37b0a2d3b9c8b2bc3cde32b62515e7 /target/arm/translate-a32.h | |
| parent | 9194a9cbc75e7af63eff26c87b995bdc52078ca6 (diff) | |
target/arm: Make functions used by translate-neon global
Make the remaining functions needed by the translate-neon code
global.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-13-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate-a32.h')
| -rw-r--r-- | target/arm/translate-a32.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index e767366f69..3ddb76b76b 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -39,6 +39,8 @@ void gen_set_pc_im(DisasContext *s, target_ulong val); void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); +long neon_element_offset(int reg, int element, MemOp memop); +void gen_rev16(TCGv_i32 dest, TCGv_i32 var); static inline TCGv_i32 load_cpu_offset(int offset) { @@ -130,4 +132,10 @@ DO_GEN_ST(32, MO_UL) /* Set NZCV flags from the high 4 bits of var. */ #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) +/* Swap low and high halfwords. */ +static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) +{ + tcg_gen_rotri_i32(dest, var, 16); +} + #endif |