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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-18 18:01:29 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-18 18:01:29 +0000
commit2cfc5f17d366b801484b36b548708fe0f3552737 (patch)
treebf35a5924a55035f6a44089943a0b5dccae32d09 /target-arm
parentd1b5c20dcde176df50f1955e498af252e87a3e9d (diff)
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/translate.c15
1 files changed, 7 insertions, 8 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 1753213f49..3183ef8ba0 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8544,9 +8544,9 @@ undef:
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
basic block 'tb'. If search_pc is TRUE, also generate PC
information for each intermediate instruction. */
-static inline int gen_intermediate_code_internal(CPUState *env,
- TranslationBlock *tb,
- int search_pc)
+static inline void gen_intermediate_code_internal(CPUState *env,
+ TranslationBlock *tb,
+ int search_pc)
{
DisasContext dc1, *dc = &dc1;
uint16_t *gen_opc_end;
@@ -8787,17 +8787,16 @@ done_generating:
tb->size = dc->pc - pc_start;
tb->icount = num_insns;
}
- return 0;
}
-int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
{
- return gen_intermediate_code_internal(env, tb, 0);
+ gen_intermediate_code_internal(env, tb, 0);
}
-int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
+void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
{
- return gen_intermediate_code_internal(env, tb, 1);
+ gen_intermediate_code_internal(env, tb, 1);
}
static const char *cpu_mode_names[16] = {