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authorJoel Stanley <joel@jms.id.au>2021-05-01 10:03:51 +0200
committerCédric Le Goater <clg@kaod.org>2021-05-01 10:03:51 +0200
commita3888d757acdd92c4c49fb9cad5f5733d8280a86 (patch)
treea458b8ac08971a908bc0991d19fd5349d2f00336 /docs
parentc5475b3f9aa28c1c1422c7de0bab40c5dff77341 (diff)
aspeed: Integrate HACE
Add the hash and crypto engine model to the Aspeed socs. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210409000253.1475587-3-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'docs')
-rw-r--r--docs/system/arm/aspeed.rst1
1 files changed, 0 insertions, 1 deletions
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 23a1468cd1..a1911f9403 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -60,7 +60,6 @@ Missing devices
* PWM and Fan Controller
* Slave GPIO Controller
* Super I/O Controller
- * Hash/Crypto Engine
* PCI-Express 1 Controller
* Graphic Display Controller
* PECI Controller