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authorMichael Clark <mjc@sifive.com>2018-03-04 13:50:12 +1300
committerMichael Clark <mjc@sifive.com>2018-05-06 10:39:38 +1200
commit6296a799b14142ccb813b678227ae9e6bf0ffa79 (patch)
tree54a1f1db84c4c3aef0c18354b9d52b1050add12a /disas
parent42b3a4b7ccbbf419df926939b273fe3b8a6dca1f (diff)
RISC-V: Include instruction hex in disassembly
This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas')
-rw-r--r--disas/riscv.c39
1 files changed, 20 insertions, 19 deletions
diff --git a/disas/riscv.c b/disas/riscv.c
index 74ad16eacd..2cecf0d855 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2769,25 +2769,6 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
char tmp[64];
const char *fmt;
- if (dec->op == rv_op_illegal) {
- size_t len = inst_length(dec->inst);
- switch (len) {
- case 2:
- snprintf(buf, buflen, "(0x%04" PRIx64 ")", dec->inst);
- break;
- case 4:
- snprintf(buf, buflen, "(0x%08" PRIx64 ")", dec->inst);
- break;
- case 6:
- snprintf(buf, buflen, "(0x%012" PRIx64 ")", dec->inst);
- break;
- default:
- snprintf(buf, buflen, "(0x%016" PRIx64 ")", dec->inst);
- break;
- }
- return;
- }
-
fmt = opcode_data[dec->op].format;
while (*fmt) {
switch (*fmt) {
@@ -3004,6 +2985,11 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
format_inst(buf, buflen, 16, &dec);
}
+#define INST_FMT_2 "%04" PRIx64 " "
+#define INST_FMT_4 "%08" PRIx64 " "
+#define INST_FMT_6 "%012" PRIx64 " "
+#define INST_FMT_8 "%016" PRIx64 " "
+
static int
print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
{
@@ -3031,6 +3017,21 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
}
}
+ switch (len) {
+ case 2:
+ (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
+ break;
+ case 4:
+ (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
+ break;
+ case 6:
+ (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
+ break;
+ default:
+ (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
+ break;
+ }
+
disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
(*info->fprintf_func)(info->stream, "%s", buf);