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authorJiajie Chen <c@jia.je>2023-08-22 09:19:50 +0200
committerSong Gao <gaosong@loongson.cn>2023-08-24 11:17:57 +0800
commit6496269d7e0b7f0d42499d7e4dde19c8b6c759c9 (patch)
tree31216488985550f3884244b9b94adbb3d9d84647
parent7033c0e6dd36cd2bfa9a323c3a51ecb0b55903fc (diff)
target/loongarch: Sign extend results in VA32 mode
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> Message-Id: <20230822071959.35620-1-philmd@linaro.org>
-rw-r--r--target/loongarch/translate.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 9a23ec786d..de7c1c5d1f 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -238,6 +238,9 @@ static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
{
+ if (ctx->va32) {
+ addr = (int32_t)addr;
+ }
return addr;
}