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2022-01-06Merge changes Icf5e3045,Ie5fb0b72 into integrationAndré Przywara
* changes: docs(allwinner): update SoC list and build options docs(allwinner): add SUNXI_SETUP_REGULATORS build option
2021-12-27docs(allwinner): update SoC list and build optionsAndre Przywara
Our list of possible Allwinner build targets was missing the newly introduced R329 support. Fix that by adding a table with maps the SoC names to the build target names. Also add some explanation about the recently introduced PSCI power management providers. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Icf5e304562c3082552bf08d7b26904caf9074936
2021-12-27docs(allwinner): add SUNXI_SETUP_REGULATORS build optionAndre Przywara
Document the newly introduced SUNXI_SETUP_REGULATORS build option, that allows to disable PMIC regulator setup at build time. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ie5fb0b7220426b67cfffc95df4cabb31a6ec174a
2021-12-22Merge "fix(errata): workaround for Cortex X2 erratum 2058056" into integrationMadhukar Pappireddy
2021-12-22Merge "fix(errata): workaround for Cortex X2 erratum 2002765" into integrationBipin Ravi
2021-12-22Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integrationBipin Ravi
2021-12-21Merge "fix(doc): update TF-A v2.7 release date in the release information ↵Mark Dykes
page" into integration
2021-12-21fix(errata): workaround for Cortex X2 erratum 2058056johpow01
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core. It applies to revisions r0p0, r1p0, and r2p0 and is still open. There are 2 ways this workaround can be accomplished, the first of which involves executing a few additional instructions around MSR writes to CPUECTLR when disabling the prefetcher. (see SDEN for details) However, this patch implements the 2nd possible workaround which sets the prefetcher into its most conservative mode, since this workaround is generic. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775100 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
2021-12-21fix(doc): update TF-A v2.7 release date in the release information pageBipin Ravi
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Iae84f82518ab89edc204a23083d5f4168449c2bf
2021-12-17fix(errata): workaround for Cortex X2 erratum 2002765johpow01
Cortex X2 erratum 2002765 is a Cat B erratum present in the X2 core. It applies to revisions r0p0, r1p0, and r2p0 and is still open. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775100 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I11576a03bfd8a6b1bd9ffef4430a097d763ca3cf
2021-12-16fix(errata): workaround for Cortex X2 erratum 2083908johpow01
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex X2 core. It applies to revision r2p0 and is still open. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775100 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Id9dca2b042bf48e75fb3013ab37d1c5925824728
2021-12-16Merge "feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support" into integrationMadhukar Pappireddy
2021-12-16Merge "docs(ff-a): boot order field of SPs manifest" into integrationMadhukar Pappireddy
2021-12-16feat(plat/fvp_r): Threat Model for TF-A v8-R64 SupportGary Morrison
Threat model for the current, BL1-only R-class support. Signed-off-by: Gary Morrison <gary.morrison@arm.com> Change-Id: I8479d5cb30f3cf3919281cc8dc1f21cada9511e0
2021-12-16docs(ff-a): boot order field of SPs manifestJ-Alves
Document `boot-order` field from FF-A partitions manifest, in accordance to Hafnium's (SPM) implementation. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I9fd070100ee52e0d465d2cce830cc91d78bddfc0
2021-12-13Merge changes from topic "jc/AMUv1" into integrationManish Pandey
* changes: docs(build-options): add build macros for features FGT,AMUv1 and ECV fix(amu): fault handling on EL2 context switch
2021-12-10docs(build-options): add build macros for features FGT,AMUv1 and ECVJayanth Dodderi Chidanand
This patch adds macros explicit to the features - FEAT_FGT,FEAT_AMUv1 and FEAT_ECV respectively. It assists in controlled access to the set of registers (HDFGRTR_EL2, HAFGRTR_EL2 and CNTPOFF_EL2) under the influence of these features during context save and restore routines. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I5082ea6687a686d8c5af3fe8bf769957cf3078b0
2021-12-08docs(measured-boot): add a platform function for critical dataManish V Badarkhe
Added a platform function to measure the critical data and record its measurement. Also, corrected a return value of 'plat_mboot_measure_image' function in the documentation. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I576676f654e517c2010ca1d5a87a1f7277d581c3
2021-12-07fix(docs): update the v2.6 change-logManish V Badarkhe
Updated the v2.6 change-log for below: 1. Moved ETE/ETM related changes under separate scope 2. Added manually commit log for Demeter CPU Change-Id: Ib5b5f994f603af6c82b1400256752581a7931268 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-12-06docs: mark STM32MP_USE_STM32IMAGE as deprecatedYann Gautier
This macro was used for the legacy boot mode on SPM32MP platforms. The recommended boot method is now FIP. The code under this macro will be removed after tag v2.7. Change-Id: Id3b7baea2d3e6ea8b36a4cd0b107cb92591a172b Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-01feat(mt8186): initialize platform for MediaTek MT8186Rex-BC Chen
- Add basic platform setup. - Add MT8186 documentation at docs/plat/. - Add generic CPU helper functions. - Add basic register address. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Id3e2f46a8c3ab2f3e29137e508d4c671e8f4aad5
2021-11-26Merge "docs(spm): update threat model with FF-A v1.1" into integrationOlivier Deprez
2021-11-23docs(spm): update threat model with FF-A v1.1J-Alves
Update SPM's threat model to contain threats related to notifications feature, compliant with FF-A v1.1 spec. Change-Id: I4a825be5dd14137a0d04d532adfe5343714794c5 Signed-off-by: J-Alves <joao.alves@arm.com>
2021-11-22docs(changelog): generate changelogManish V Badarkhe
For future reference, this changelog was generated with the following command: npm run release -- --skip.commit --skip.tag --release-as 2.6.0 Change-Id: Idf6be5c3be15ddfdb1d32fafb9e0e4b399b269f3 Signed-off-by: Chris Kay <chris.kay@arm.com> Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-11-22Merge "docs(ff-a): update documentation of FF-A interfaces" into integrationOlivier Deprez
2021-11-18docs(ff-a): update documentation of FF-A interfacesJ-Alves
- Overview of FF-A v1.1 notifications feature, and list of all the new related interface. - FFA_RXTX_UNMAP now implemented, so provided description. - FF-A v1.1 interfaces documented: FFA_SPM_ID_GET and FFA_SECONDARY_EP_REGISTER. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: If40b4d2b2473f81ecfb2ddbf14852c3f10682867
2021-11-17docs(commit-style): add commit style documentationChris Kay
This change adds a new documentation page describing the commit style, acceptable Conventional Commits types and scopes, and documents the process for expanding the list of scopes. Change-Id: Iad957b67fa71a879e8aa0790c58a5b08cec300d6 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17build(docs): introduce release scriptChris Kay
This change introduces a new NPM run script to automatically generate the release changelog, as well as bump version numbers across the code-base and create the release tag. This script runs [Standard Version] to execute this, which is a tool designed around automating substantial parts of the release process. This can be done by running: npm run release -- [<standard-version args>] Standard Version expects the project to adhere to the [Semantic Versioning] convention which TF-A does not, so you may need to specify the version manually, e.g.: npm run release -- --release-as 2.6.0 Individual steps of the release process may also be skipped at-will, which may be necessary when, for example, tweaking the changelog: npm run release -- --skip.commit --skip.tag Standard Version is configured by the `.versionrc.js` file, which contains information about the Conventional Commits types and scopes used by the project, and how they map to the changelog. To maintain continuity with the existing changelog style - at least to the extent possible in the move from manual to automatic creation - a customized changelog template has been introduced, based on the Conventional Commits template provided by Standard Version. This template package extends the Conventional Commits template package by introducing support for parsing the Conventional Commits scopes into changelog sections, similarly to how they were previously organized. [Standard Version]: https://github.com/conventional-changelog/standard-version [Semantic Versioning]: https://semver.org Change-Id: I5bafa512daedc631baae951651c38c1c62046b0a Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17build(docs): add support for Markdown documentationChris Kay
This changes adds support for building Markdown documentation into Sphinx with [MyST]. We'll make use of this in a later patch, where we introduce automatically-generated Markdown documentation that needs to be compiled as part of the Sphinx documentation. [MyST]: https://myst-parser.readthedocs.io/en/latest Change-Id: I2a241a588c579fac1a81e1853479908928be1fc8 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17docs(prerequisites): update to Node.js v16Chris Kay
Updates the Node.js version installed by the prerequisite instructions from v14 to v16, which is the latest LTS release. The instructions for installing the Node Version Manager (NVM) have also been updated for v0.39.0 (previously v0.38.0). Change-Id: I85528b3906305914ba6169b4dc5aafcf5b36a339 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17build(docs): update Python dependenciesChris Kay
Updates the Python dependencies used to build the project's Sphinx documentation to their latest versions. Change-Id: I8baee89c85179a667a3850a7b9705ab76f4d702a Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17build(docs): pin Python dependenciesChris Kay
Recently some of our dependencies' dependencies have come into conflict and are now causing errors when trying to install the Python requirements. This change introduces `requirements.in` - a list of our own direct dependencies, and pins them to specific versions. The existing `requirements.txt` file is now automatically generated by the `pip-compile` tool - part of the pip-tools package - and ensures that our dependency tree is also pinned. This is a manual process at present, but our dependencies are updated infrequently enough that it's not introducing any major overhead. Change-Id: I3cd0c11a1a4eccaf0d77b538cfdb94474833b811 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17fix(docs): fix `FF-A` substitutionChris Kay
In this change the `FFA` substitution has been renamed to `FF-A`, as well as the term it substitutes to - the `FFA` term does not exist. Change-Id: I0c33d00d82a5498f7088e6a2b088a0006dfe7f65 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17Merge "docs(spm): document s-el0 partition support" into integrationOlivier Deprez
2021-11-16Merge "fix(spm_mm): do not compile if SVE/SME is enabled" into integrationManish Pandey
2021-11-16fix(spm_mm): do not compile if SVE/SME is enabledManish Pandey
As spm_mm cannot handle SVE/SME usage in NS world so its better to give compilation error when ENABLE_SVE_FOR_NS=1 or ENABLE_SME_FOR_NS=1. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I69dbb272ca681bb020501342008eda20d4c0b096
2021-11-15docs(rme): add description of TF-A changes for RMEZelalem Aweke
This patch expands the RME documentation with description of TF-A changes for RME. It also modifies some other parts of TF-A documentation to account for RME changes. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I9e6feeee235f0ba4b767d239f15840f1e0c540bb
2021-11-15docs(gpt): add documentation page for GPT libraryjohpow01
This patch adds some documentation for the GPT library as well as adds code owners for it. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: If1cd79626eadb27e1024d731b26ee2e20af74a66
2021-11-12feat(sme): enable SME functionalityjohpow01
This patch adds two new compile time options to enable SME in TF-A: ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and secure worlds respectively. Setting ENABLE_SME_FOR_NS=1 will enable SME for non-secure worlds and trap SME, SVE, and FPU/SIMD instructions in secure context. Setting ENABLE_SME_FOR_SWD=1 will disable these traps, but support for SME context management does not yet exist in SPM so building with SPD=spmd will fail. The existing ENABLE_SVE_FOR_NS and ENABLE_SVE_FOR_SWD options cannot be used with SME as it is a superset of SVE and will enable SVE and FPU/SIMD along with SME. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iaaac9d22fe37b4a92315207891da848a8fd0ed73
2021-11-10docs(spm): secure interrupt management in SPMCMadhukar Pappireddy
Change-Id: I9bed67e4146ae92123ab925334e37fb0d3677ef1 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-11-09Merge "feat(measured boot): add documentation to build and run PoC" into ↵Joanna Farley
integration
2021-11-08Merge changes Ic2f90d79,Ieca02425,I615bcc1f,I6a9cb4a2,I5247f8f8, ... into ↵Madhukar Pappireddy
integration * changes: fix(errata): workaround for Neoverse V1 erratum 2216392 fix(errata): workaround for Cortex A78 erratum 2242635 fix(errata): workaround for Neoverse-N2 erratum 2280757 fix(errata): workaround for Neoverse-N2 erratum 2242400 fix(errata): workaround for Neoverse-N2 erratum 2138958 fix(errata): workaround for Neoverse-N2 erratum 2242415
2021-11-08feat(measured boot): add documentation to build and run PoCJavier Almansa Sobrino
Add documentation to build and run a PoC based on the OP-TEE toolkit to show how TF-A Measured Boot can interact with a third party (f)TPM service. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I11ac99c4ff54ea52aba0731aa7f707d7cd0c4216
2021-11-05fix(errata): workaround for Neoverse V1 erratum 2216392johpow01
Neoverse V1 erratum 2216392 is a Cat B erratum present in the V1 core. It applies to revisions r1p0 and r1p1 and is still open. The issue is also present in r0p0 but there is no workaround in that revision. SDEN can be found here: https://developer.arm.com/documentation/SDEN1401781 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ic2f90d79c75e8ffef01aac81eddf1bfd8b7164ab
2021-11-05docs(spm): document s-el0 partition supportRaghu Krishnamurthy
This patch adds a brief description of S-EL0 partition support in the SPMC using ARMv8.1 FEAT_VHE. Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com> Change-Id: Ie079265476604f62d5f2a66684f01341000969d0
2021-11-05fix(errata): workaround for Cortex A78 erratum 2242635johpow01
Cortex A78 erratum 2242635 is a Cat B erratum present in the A78 Core. It applies to revisions r1p0, r1p1, r1p2, and is still open. The issue is also present in r0p0 but there is no workaround for this revision. SDEN can be found here: https://developer.arm.com/documentation/SDEN1401784 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ieca024254cabbc683ff13a70f3aeb8f2f3c5ce07
2021-11-04fix(errata): workaround for Neoverse-N2 erratum 2280757nayanpatel-arm
Neoverse-N2 erratum 2280757 is a Cat B erratum that applies to revision r0p0 of CPU. It is still open. The workaround is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22] will cause CFP instruction to invalidate all branch predictor resources regardless of context. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com> Change-Id: I615bcc1f993c45659b8b6f1a34fca0eb490f8add
2021-11-04fix(errata): workaround for Neoverse-N2 erratum 2242400nayanpatel-arm
Neoverse-N2 erratum 2242400 is a Cat B erratum that applies to revision r0p0 of CPU. It is still open. The workaround is to set CPUACTLR5_EL1[17] to 1'b1 followed by setting few system control registers to specific values as per attached SDEN document. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com> Change-Id: I6a9cb4a23238b8b511802a1ee9fcc5b207137649
2021-11-04fix(errata): workaround for Neoverse-N2 erratum 2138958nayanpatel-arm
Neoverse-N2 erratum 2138958 is a Cat B erratum that applies to revision r0p0 of CPU. It is still open. The workaround is to set CPUACTLR5_EL1[13] to 1'b1. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com> Change-Id: I5247f8f8eef08d38c169aad6d2c5501ac387c720
2021-11-04fix(errata): workaround for Neoverse-N2 erratum 2242415nayanpatel-arm
Neoverse-N2 erratum 2242415 is a Cat B erratum that applies to revision r0p0 of CPU. It is still open. The workaround is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22] will cause CFP instruction to invalidate all branch predictor resources regardless of context. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com> Change-Id: I442be81fbc32e21fed51a84f59584df17f845e96
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-24 19:53:02 +0000