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2021-12-22Merge "fix(sve): disable ENABLE_SVE_FOR_NS for AARCH32" into integrationMadhukar Pappireddy
2021-12-22Merge "fix(fiptool): respect OPENSSL_DIR" into integrationMadhukar Pappireddy
2021-12-22fix(sve): disable ENABLE_SVE_FOR_NS for AARCH32Yann Gautier
With patch [1], ENABLE_SVE_FOR_NS is always enable. Disable it for AARCH32 platforms, as the feature is not supported. The warning message is replaced with an error, and the second override is removed. [1] dc78e62d80e6 ("feat(sme): enable SME functionality") Change-Id: Ic9c5e2612c9e00bd0d37ca3b59537e39270c9799 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-10fix(amu): fault handling on EL2 context switchJayanth Dodderi Chidanand
The HAFGRTR_EL2 register is UNDEFINED unless the CPU supports both FEAT_FGT and FEAT_AMUv1. FEAT_FGT is mandatory for v8.6-A and upwards, but FEAT_AMUv1 is optional (from v8.4-A upwards), and as such any 8.6-A cores today without support for FEAT_AMUv1 will trigger an undefined instruction exception on accessing this register. Currently ARM_ARCH_AT_LEAST macro has been used to associate with an architecture extension allowing to access HAFGRTR_EL2 register. This condition should be replaced with macros specific to individual features. This patch adds a new set of macros "ENABLE_FEAT_FGT, ENABLE_FEAT_AMUv1, ENABLE_FEAT_ECV" under build options to provide controlled access to the HAFGRTR_EL2 register. Further to ensure that the the build options passed comply with the given hardware implementation, a feature detection mechanism, checking whether build options match with the architecture is required at bootime. This will be implemented and pushed later in a separate patch. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: Ie390f4babe233b8b09455290277edbddecd33ead
2021-12-08fix(fiptool): respect OPENSSL_DIRRoss Burton
fiptool links to libcrypto, so as with the other tools it should respect OPENSSL_DIR for include/library paths. Change-Id: Icd8c15fa5097db1da9a3a9222d9e267548c4c7e2 Signed-off-by: Ross Burton <ross.burton@arm.com>
2021-11-22docs(changelog): generate changelogManish V Badarkhe
For future reference, this changelog was generated with the following command: npm run release -- --skip.commit --skip.tag --release-as 2.6.0 Change-Id: Idf6be5c3be15ddfdb1d32fafb9e0e4b399b269f3 Signed-off-by: Chris Kay <chris.kay@arm.com> Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-11-12feat(sme): enable SME functionalityjohpow01
This patch adds two new compile time options to enable SME in TF-A: ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and secure worlds respectively. Setting ENABLE_SME_FOR_NS=1 will enable SME for non-secure worlds and trap SME, SVE, and FPU/SIMD instructions in secure context. Setting ENABLE_SME_FOR_SWD=1 will disable these traps, but support for SME context management does not yet exist in SPM so building with SPD=spmd will fail. The existing ENABLE_SVE_FOR_NS and ENABLE_SVE_FOR_SWD options cannot be used with SME as it is a superset of SVE and will enable SVE and FPU/SIMD along with SME. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iaaac9d22fe37b4a92315207891da848a8fd0ed73
2021-11-02fix(checkpatch): do not check merge commitsYann Gautier
Add the --no-merges option when listing patches to check with rev-list command, when running make checkpatch. Change-Id: I47f3f5dfe358ed2b960a754f70aec0dc3c2b4536 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-10-29Merge changes from topic "ck/mpmm" into integrationManish Pandey
* changes: docs(maintainers): add Chris Kay to AMU and MPMM feat(tc): enable MPMM feat(mpmm): add support for MPMM feat(amu): enable per-core AMU auxiliary counters docs(amu): add AMU documentation refactor(amu): refactor enablement and context switching refactor(amu): detect auxiliary counters at runtime refactor(amu): detect architected counters at runtime refactor(amu): conditionally compile auxiliary counter support refactor(amu): factor out register accesses refactor(amu)!: privatize unused AMU APIs refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK` build(amu): introduce `amu.mk` build(fconf)!: clean up source collection feat(fdt-wrappers): add CPU enumeration utility function build(fdt-wrappers): introduce FDT wrappers makefile build(bl2): deduplicate sources build(bl1): deduplicate sources
2021-10-26feat(mpmm): add support for MPMMChris Kay
MPMM - the Maximum Power Mitigation Mechanism - is an optional microarchitectural feature present on some Armv9-A cores, introduced with the Cortex-X2, Cortex-A710 and Cortex-A510 cores. MPMM allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. This feature is enabled via the `ENABLE_MPMM` build option. Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or by via the plaform-implemented `plat_mpmm_topology` function. Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26feat(amu): enable per-core AMU auxiliary countersChris Kay
This change makes AMU auxiliary counters configurable on a per-core basis, controlled by `ENABLE_AMU_AUXILIARY_COUNTERS`. Auxiliary counters can be described via the `HW_CONFIG` device tree if the `ENABLE_AMU_FCONF` build option is enabled, or the platform must otherwise implement the `plat_amu_topology` function. A new phandle property for `cpu` nodes (`amu`) has been introduced to the `HW_CONFIG` specification to allow CPUs to describe the view of their own AMU: ``` cpu0: cpu@0 { ... amu = <&cpu0_amu>; }; ``` Multiple cores may share an `amu` handle if they implement the same set of auxiliary counters. AMU counters are described for one or more AMUs through the use of a new `amus` node: ``` amus { cpu0_amu: amu-0 { #address-cells = <1>; #size-cells = <0>; counter@0 { reg = <0>; enable-at-el3; }; counter@n { reg = <n>; ... }; }; }; ``` This structure describes the **auxiliary** (group 1) AMU counters. Architected counters have architecturally-defined behaviour, and as such do not require DTB entries. These `counter` nodes support two properties: - The `reg` property represents the counter register index. - The presence of the `enable-at-el3` property determines whether the firmware should enable the counter prior to exiting EL3. Change-Id: Ie43aee010518c5725a3b338a4899b0857caf4c28 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26refactor(amu): conditionally compile auxiliary counter supportChris Kay
This change reduces preprocessor dependencies on the `AMU_GROUP1_NR_COUNTERS` and `AMU_GROUP1_COUNTERS_MASK` definitions, as these values will eventually be discovered dynamically. In their stead, we introduce the `ENABLE_AMU_AUXILIARY_COUNTERS` build option, which will enable support for dynamically detecting and enabling auxiliary AMU counters. This substantially reduces the amount of memory used by platforms that know ahead of time that they do not have any auxiliary AMU counters. Change-Id: I3d998aff44ed5489af4857e337e97634d06e3ea1 Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-10-26build(bl2): deduplicate sourcesChris Kay
Deduplicating sources prevents the build system from complaining about multiply-compiled files, which can happen if multiple makefiles depend on a component. This already occurs for BL31. Signed-off-by: Chris Kay <chris.kay@arm.com> Change-Id: Ic9e67932550f07cb9e4d199f68bc46c33a611748
2021-10-26build(bl1): deduplicate sourcesChris Kay
Deduplicating sources prevents the build system from complaining about multiply-compiled files, which can happen if multiple makefiles depend on a component. This already occurs for BL31. Signed-off-by: Chris Kay <chris.kay@arm.com> Change-Id: I9b40402f6f04600061fba7d6ad5d222a71e7d4a7
2021-10-22fix: remove "experimental" tag for stable featuresManish Pandey
there are features which are marked as experimental even though they are stable and used for quite some time. Following features are no longer marked as experimental - SPMD - MEASURED_BOOT - FCONF and associated build flags - DECRYPTION_SUPPORT and associated build flags - ENABLE_PAUTH - ENABLE_BTI - USE_SPINLOCK_CAS - GICv3 Multichip support Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I4bb653d9c413c66095ec31f0b8aefeb13ea04ee9
2021-10-06Merge changes from topic "fvpr_cleanup" into integrationMark Dykes
* changes: refactor(tbbr): remove "fvp_r" platform specific check refactor(Makefile): move NEED_<IMAGE> before their use
2021-10-06refactor(Makefile): move NEED_<IMAGE> before their useManish Pandey
In later patch tbbr_tools.mk requires NEED_BL2 definition which is defined after inclusion of this mk file. Move NEED_<IMAGE> definitions earlier to their use Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ieff999b255690755779d0cd35d5aba2d3794873c
2021-10-05feat(rme): add ENABLE_RME build option and support for RMM imageZelalem Aweke
The changes include: - A new build option (ENABLE_RME) to enable FEAT_RME - New image called RMM. RMM is R-EL2 firmware that manages Realms. When building TF-A, a path to RMM image can be specified using the "RMM" build flag. If RMM image is not provided, TRP is built by default and used as RMM image. - Support for RMM image in fiptool Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I017c23ef02e465a5198baafd665a60858ecd1b25
2021-10-05refactor(makefile): remove BL prefixes in build macrosZelalem Aweke
The current Makefile assumes all TF-A binaries have BL prefixes (BL1, BL2, etc). Now that we have other binary names with FEAT_RME feature, remove this assumption. With this change, we need to pass the full name of a binary when using build macros. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I44e094b2366aa526f807d92dffa709390d14d145
2021-09-29Merge "build(bl2): enable SP pkg loading for S-EL1 SPMC" into integrationOlivier Deprez
2021-09-28build(bl2): enable SP pkg loading for S-EL1 SPMCBalint Dobszay
Currently the SP package loading mechanism is only enabled when S-EL2 SPMC is selected. Remove this limitation. Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Change-Id: I5bf5a32248e85a26d0345cacff7d539eed824cfc
2021-09-27feat(hcx): add build option to enable FEAT_HCXjohpow01
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2) and access to this register must be explicitly enabled through the SCR_EL3.HXEn bit. This patch adds a new build flag ENABLE_FEAT_HCX to allow the register to be accessed from EL2. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ibb36ad90622f1dc857adab4b0d4d7a89456a522b
2021-09-17Merge changes from topic "TrcDbgExt" into integrationManish Pandey
* changes: feat(plat/fvp): enable trace extension features by default feat(trf): enable trace filter control register access from lower NS EL feat(trf): initialize trap settings of trace filter control registers access feat(sys_reg_trace): enable trace system registers access from lower NS ELs feat(sys_reg_trace): initialize trap settings of trace system registers access feat(trbe): enable access to trace buffer control registers from lower NS EL feat(trbe): initialize trap settings of trace buffer control registers access
2021-09-03feat(fvp): enable external SP images in BL2 configBalint Dobszay
Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT. This is a problem when building a system with other SPs (e.g. from Trusted Services). This commit implements a workaround to enable adding SP UUIDs to the list at build time. Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Change-Id: Iff85d3778596d23d777dec458f131bd7a8647031
2021-08-26feat(trf): enable trace filter control register access from lower NS ELManish V Badarkhe
Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is implemented but unused). Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-26feat(sys_reg_trace): enable trace system registers access from lower NS ELsManish V Badarkhe
Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is implemented but unused). Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-26feat(trbe): enable access to trace buffer control registers from lower NS ELManish V Badarkhe
Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is implemented but unused). Change-Id: I285a672ccd395eebd377714c992bb21062a729cc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-02feat(fwu): initialize FWU driver in BL2Manish V Badarkhe
Initialized FWU driver module in BL2 component under build flag PSA_FWU_SUPPORT. Change-Id: I08b191599835925c355981d695667828561b9a21 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-02feat(fwu_metadata): add FWU metadata header and build optionsManish V Badarkhe
Added a firmware update metadata structure as per section 4.1 in the specification document[1]. Also, added the build options used in defining the firmware update metadata structure. [1]: https://developer.arm.com/documentation/den0118/a/ Change-Id: I8f43264a46fde777ceae7fd2a5bb0326f1711928 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-07-05Merge changes from topic "sb/measured-boot" into integrationSandrine Bailleux
* changes: refactor(plat/fvp): tidy up list of images to measure docs: explain Measured Boot dependency on Trusted Boot
2021-06-30Merge "feat(sve): enable SVE for the secure world" into integrationOlivier Deprez
2021-06-29docs: explain Measured Boot dependency on Trusted BootSandrine Bailleux
Change-Id: I04d9439d5967e93896dfdb0f3d7b0aec96c743f9 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-06-28Merge "fix(makefile): use space in WARNINGS list" into integrationMadhukar Pappireddy
2021-06-28feat(sve): enable SVE for the secure worldMax Shvetsov
Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD. ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the platform. SVE is configured during initial setup and then uses EL3 context save/restore routine to switch between SVE configurations for different contexts. Reset value of CPTR_EL3 changed to be most restrictive by default. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116
2021-05-31Merge "feat(tc0): add support for trusted services" into integrationOlivier Deprez
2021-05-27fix(makefile): use space in WARNINGS listYann Gautier
The tab between -Wdisabled-optimization and -Wvla is replaced with a space. This avoids having it removed when copy/pasting the compilation command line, and having the following error: arm-none-eabi-gcc: error: unrecognized command line option '-Wdisabled-optimization-Wvla'; did you mean '-Wdisabled-optimization'? Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I72de2a70d192a7813b1f9b55485914142d1fc428
2021-05-12feat(makefile): incrementing minor version to reflect v2.5 releaseMadhukar Pappireddy
Updated the minor version in the makefile Change-Id: Ie2b3ce5b36a105a0e2fff52c3740cc9702ca3108 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-05-10feat(tc0): add support for trusted servicesDavidson K
This patch adds support for the crypto and secure storage secure partitions for the Total Compute platform. These secure partitions have to be managed by Hafnium executing at S-EL2 Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
2021-04-21Add PIE support for AARCH32Yann Gautier
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done for PIE support on AARCH64. The RELA_SECTION is redefined for AARCH32, as the created section is .rel.dyn and the symbols are .rel*. Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-04-13Merge "fiptool: Do not print duplicate verbose lines about building fiptool" ↵Madhukar Pappireddy
into integration
2021-04-08fiptool: Do not print duplicate verbose lines about building fiptoolPali Rohár
Makefile for fiptool already prints verbose line when is (re)building fiptool, so there is no need to print it also from top level Makefile. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I6936a508702f1bf796d17578bb1f043f06365319
2021-03-18arch: Enable `FEAT_SB` for supported non-Armv8.5-A platformsChris Kay
The speculation barrier feature (`FEAT_SB`) was introduced with and made mandatory in the Armv8.5-A extension. It was retroactively made optional in prior extensions, but the checks in our code-base do not reflect that, assuming that it is only available in Armv8.5-A or later. This change introduces the `ENABLE_FEAT_SB` definition, which derives support for the `sb` instruction in the assembler from the feature flags passed to it. Note that we assume that if this feature is enabled then all the cores in the system support it - enabling speculation barriers for only a subset of the cores is unsupported. Signed-off-by: Chris Kay <chris.kay@arm.com> Change-Id: I978ed38829385b221b10ba56d49b78f4756e20ea
2021-02-25Enable v8.6 AMU enhancements (FEAT_AMUv1p1)johpow01
ARMv8.6 adds virtual offset registers to support virtualization of the event counters in EL1 and EL0. This patch enables support for this feature in EL3 firmware. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
2021-02-05Add TRNG Firmware Interface serviceJimmy Brisson
This adds the TRNG Firmware Interface Service to the standard service dispatcher. This includes a method for dispatching entropy requests to platforms and includes an entropy pool implementation to avoid dropping any entropy requested from the platform. Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-26Merge changes from topic "tp-feat-rng" into integrationSandrine Bailleux
* changes: plat/qemu: Use RNDR in stack protector Makefile: Add FEAT_RNG support define Define registers for FEAT_RNG support
2021-01-15Makefile: Add FEAT_RNG support defineTomas Pilar
Define ENABLE_FEAT_RNG that describes whether the armv8.5 FEAT_RNG is supported in this build. This allows conditional inclusion of code targetting RNDR and RNDRRS registers. Signed-off-by: Tomas Pilar <tomas@nuviainc.com> Change-Id: Idd632f8b9bc20ea3d8793f55ead88fa12cb08821
2021-01-08Makefile: Fix ${FIP_NAME} to be rebuilt only when neededPali Rohár
Currently ${FIP_DEPS} as prerequisite for ${BUILD_PLAT}/${FIP_NAME} contains .PHONY targets check_$(1) and therefore ${BUILD_PLAT}/${FIP_NAME} is always rebuilt even when other file target prerequisites are not changed. These changes fix above issue and ${BUILD_PLAT}/${FIP_NAME} target is rebuilt only when its prerequisites are changed. There are 3 changes: Content of check_$(1) target is moved into check_$(1)_cmd variable so it can be easily reused. .PHONY check_$(1) targets are not put into ${FIP_DEPS} and ${FWU_FIP_DEPS} dependencies anymore and required checks which are in ${CHECK_FIP_CMD} and ${CHECK_FWU_FIP_CMD} variables are executed as part of targets ${BUILD_PLAT}/${FIP_NAME} and ${BUILD_PLAT}/${FWU_FIP_NAME} itself. To ensure that ${BUILD_PLAT}/${FIP_NAME} and ${BUILD_PLAT}/${FWU_FIP_NAME} are rebuilt even when additional dependency file image added by TOOL_ADD_IMG is changed, this file image (if exists) is added as file dependency to ${FIP_DEPS} and ${FWU_FIP_DEPS}. If it does not exist then FORCE target is added to ensure that FIP/FWU_FIP is rebuilt. Command ${CHECK_FIP_CMD}/${CHECK_FWU_FIP_CMD} will then thrown an error message if the file is required but not present. So this change ensures that if BL33 image is updated then final FIP image is updated too. And if BL33 image is not specified or does not exist and is required to be present then check_$(1)_cmd call from ${CHECK_FIP_CMD} would ensure that error message is thrown during build. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I635cf82e2b667ff57e2af83500d4aca71d235e3e
2021-01-07Makefile: Do not mark file targets as .PHONY targetPali Rohár
Only non-file targets should be set a .PHONY. Otherwise if file target is set as .PHONY then targets which depends on those file .PHONY targets would be always rebuilt even when their prerequisites are not changed. File target which needs to be always rebuilt can be specified in Make system via having a prerequisite on some .PHONY target, instead of marking whole target as .PHONY. In Makefile projects it is common to create empty .PHONY target named FORCE for this purpose. This patch changes all file targets which are set as .PHONY to depends on new .PHONY target FORCE, to ensure that these file targets are always rebuilt (as before). Basically they are those targets which calls external make subprocess. After FORCE target is specified in main Makefile, remove it from other Makefile files to prevent duplicate definitions. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iee3b4e0de93879b95eb29a1745a041538412e69e
2020-12-15Merge "Add support for FEAT_MTPMU for Armv8.6" into integrationMark Dykes
2020-12-11Add support for FEAT_MTPMU for Armv8.6Javier Almansa Sobrino
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happening on other threads. If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit leaving it to effective state of 0 regardless of any write to it. This patch introduces the DISABLE_MTPMU flag, which allows to diable multithread event count from EL3 (or EL2). The flag is disabled by default so the behavior is consistent with those architectures that do not implement FEAT_MTPMU. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
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