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authorMichael Tretter <m.tretter@pengutronix.de>2021-01-21 08:16:50 +0100
committerStephen Boyd <sboyd@kernel.org>2021-02-08 18:31:25 -0800
commitf1bc982e7ceda6d0124ce65290727eaa49d0fd5a (patch)
treee6c4da3f01b8928b897caa0b2c009daf2f3a2000 /drivers/soc
parent354dcf7b02a3755b662b148afb7d7ecf1fbbdf71 (diff)
soc: xilinx: vcu: implement PLL disable
The disabling of the PLL is not fully implemented, because according to the ZynqMP register reference the RESET, POR_IN and PWR_POR bits have to be set to bring the PLL into reset. Set the bits to disable the PLL. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-7-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/xilinx/xlnx_vcu.c28
1 files changed, 19 insertions, 9 deletions
diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c
index ff66551a5966..34f3299afc0d 100644
--- a/drivers/soc/xilinx/xlnx_vcu.c
+++ b/drivers/soc/xilinx/xlnx_vcu.c
@@ -329,6 +329,10 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu)
return ret;
}
+ xvcu_write_field_reg(base, VCU_PLL_CTRL,
+ 1, VCU_PLL_CTRL_BYPASS_MASK,
+ VCU_PLL_CTRL_BYPASS_SHIFT);
+
vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK <<
VCU_PLL_CTRL_POR_IN_SHIFT);
@@ -340,15 +344,9 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu)
VCU_PLL_CTRL_PWR_POR_SHIFT;
xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
- xvcu_write_field_reg(base, VCU_PLL_CTRL,
- 1, VCU_PLL_CTRL_BYPASS_MASK,
- VCU_PLL_CTRL_BYPASS_SHIFT);
- xvcu_write_field_reg(base, VCU_PLL_CTRL,
- 1, VCU_PLL_CTRL_RESET_MASK,
- VCU_PLL_CTRL_RESET_SHIFT);
- xvcu_write_field_reg(base, VCU_PLL_CTRL,
- 0, VCU_PLL_CTRL_RESET_MASK,
- VCU_PLL_CTRL_RESET_SHIFT);
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
+ vcu_pll_ctrl |= (0 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
+ xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
ret = xvcu_pll_wait_for_lock(xvcu);
if (ret) {
@@ -368,6 +366,18 @@ err:
static void xvcu_pll_disable(struct xvcu_device *xvcu)
{
+ void __iomem *base = xvcu->vcu_slcr_ba;
+ u32 vcu_pll_ctrl;
+
+ vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK << VCU_PLL_CTRL_POR_IN_SHIFT);
+ vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_POR_IN_MASK) << VCU_PLL_CTRL_POR_IN_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_PWR_POR_MASK << VCU_PLL_CTRL_PWR_POR_SHIFT);
+ vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_PWR_POR_MASK) << VCU_PLL_CTRL_PWR_POR_SHIFT;
+ vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
+ vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
+ xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
+
clk_disable_unprepare(xvcu->pll_ref);
}