diff options
| author | Nick Clifton <nickc@redhat.com> | 2015-10-07 14:20:19 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2015-10-07 14:20:19 +0100 |
| commit | 886a250647ac0c608f20a7007fc2167a70f64e20 (patch) | |
| tree | 4a2ccd0c452f7802a11e2549c74b713621f36c0e /gas | |
| parent | 3b0357dadaf2366cc418ec725dec55b1cea1a2e7 (diff) | |
New ARC implementation.
bfd * archures.c: Remove support for older ARC. Added support for new
ARC cpus (ARC600, ARC601, ARC700, ARCV2).
* bfd-in2.h: Likewise.
* config.bfd: Likewise.
* cpu-arc.c: Likewise.
* elf32-arc.c: Totally changed file with a refactored
inplementation of the ARC port.
* libbfd.h: Added ARC specific relocation types.
* reloc.c: Likewise.
gas * config/tc-arc.c: Revamped file for ARC support.
* config/tc-arc.h: Likewise.
* doc/as.texinfo: Add new ARC options.
* doc/c-arc.texi: Likewise.
ld * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
* emulparams/arcebelf_prof.sh: New file
* emulparams/arcebelf.sh: Likewise.
* emulparams/arceblinux_prof.sh: Likewise.
* emulparams/arceblinux.sh: Likewise.
* emulparams/arcelf_prof.sh: Likewise.
* emulparams/arcelf.sh: Likewise.
* emulparams/arclinux_prof.sh: Likewise.
* emulparams/arclinux.sh: Likewise.
* emulparams/arcv2elfx.sh: Likewise.
* emulparams/arcv2elf.sh: Likewise.
* emultempl/arclinux.em: Likewise.
* scripttempl/arclinux.sc: Likewise.
* scripttempl/elfarc.sc: Likewise.
* scripttempl/elfarcv2.sc: Likewise
* Makefile.am: Add new ARC emulations.
* Makefile.in: Regenerate.
* NEWS: Mention the new feature.
opcodes * arc-dis.c: Revamped file for ARC support
* arc-dis.h: Likewise.
* arc-ext.c: Likewise.
* arc-ext.h: Likewise.
* arc-opc.c: Likewise.
* arc-fxi.h: New file.
* arc-regs.h: Likewise.
* arc-tbl.h: Likewise.
binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
and ARCv2.
(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
(guess_is_rela): Likewise.
(dump_relocations): Likewise.
(is_32bit_abs_reloc): Likewise.
(is_16bit_abs_reloc): Likewise.
(is_none_reloc): Likewise.
* NEWS: Mention the new feature.
include * dis-asm.h (arc_get_disassembler): Correct declaration.
* arc-reloc.def: Macro file with definition of all relocation
types.
* arc.h: Changed macros for the newly supported ARC cpus. Altered
enum defining the supported relocations.
* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
macro for EM_ARC_COMPACT2.
* arc-func.h: New file.
* arc.h: Likewise.
Diffstat (limited to 'gas')
86 files changed, 5014 insertions, 4760 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 2ece5c0db4..14b1647bc3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2015-10-07 Claudiu Zissulescu <claziss@synopsys.com> + + * config/tc-arc.c: Revamped file for ARC support. + * config/tc-arc.h: Likewise. + * doc/as.texinfo: Add new ARC options. + * doc/c-arc.texi: Likewise. + 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (s_tlsdescadd): New. @@ -1,5 +1,8 @@ -*- text -*- +* Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + Changes in 2.26: * Symbol and label names can now be enclosed in double quotes (") which allows diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c index 4806ed82ed..cc56797208 100644 --- a/gas/config/tc-arc.c +++ b/gas/config/tc-arc.c @@ -1,6 +1,7 @@ /* tc-arc.c -- Assembler for the ARC Copyright (C) 1994-2015 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). + + Contributor: Claudiu Zissulescu <claziss@synopsys.com> This file is part of GAS, the GNU Assembler. @@ -20,62 +21,57 @@ 02110-1301, USA. */ #include "as.h" +#include "subsegs.h" #include "struc-symbol.h" +#include "dwarf2dbg.h" #include "safe-ctype.h" -#include "subsegs.h" + #include "opcode/arc.h" -#include "../opcodes/arc-ext.h" #include "elf/arc.h" -#include "dwarf2dbg.h" -const struct suffix_classes -{ - char *name; - int len; -} suffixclass[] = -{ - { "SUFFIX_COND|SUFFIX_FLAG",23 }, - { "SUFFIX_FLAG", 11 }, - { "SUFFIX_COND", 11 }, - { "SUFFIX_NONE", 11 } -}; +/* Defines section. */ -#define MAXSUFFIXCLASS (sizeof (suffixclass) / sizeof (struct suffix_classes)) +#define MAX_FLAG_NAME_LENGHT 3 +#define MAX_INSN_FIXUPS 2 +#define MAX_CONSTR_STR 20 -const struct syntax_classes -{ - char *name; - int len; - int s_class; -} syntaxclass[] = -{ - { "SYNTAX_3OP|OP1_MUST_BE_IMM", 26, SYNTAX_3OP|OP1_MUST_BE_IMM|SYNTAX_VALID }, - { "OP1_MUST_BE_IMM|SYNTAX_3OP", 26, OP1_MUST_BE_IMM|SYNTAX_3OP|SYNTAX_VALID }, - { "SYNTAX_2OP|OP1_IMM_IMPLIED", 26, SYNTAX_2OP|OP1_IMM_IMPLIED|SYNTAX_VALID }, - { "OP1_IMM_IMPLIED|SYNTAX_2OP", 26, OP1_IMM_IMPLIED|SYNTAX_2OP|SYNTAX_VALID }, - { "SYNTAX_3OP", 10, SYNTAX_3OP|SYNTAX_VALID }, - { "SYNTAX_2OP", 10, SYNTAX_2OP|SYNTAX_VALID } -}; +#ifdef DEBUG +# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args) +#else +# define pr_debug(fmt, args...) +#endif + +#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27) +#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16) +#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \ + (SUB_OPCODE (x) == 0x28)) -#define MAXSYNTAXCLASS (sizeof (syntaxclass) / sizeof (struct syntax_classes)) +/* Equal to MAX_PRECISION in atof-ieee.c. */ +#define MAX_LITTLENUMS 6 -/* This array holds the chars that always start a comment. If the - pre-processor is disabled, these aren't very useful. */ +/* Macros section. */ + +#define regno(x) ((x) & 0x3F) +#define is_ir_num(x) (((x) & ~0x3F) == 0) +#define is_code_density_p(op) (((op)->subclass == CD1 || (op)->subclass == CD2)) +#define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP)) +#define is_kernel_insn_p(op) (((op)->class == KERNEL)) + +/* Generic assembler global variables which must be defined by all + targets. */ + +/* Characters which always start a comment. */ const char comment_chars[] = "#;"; -/* This array holds the chars that only start a comment at the beginning of - a line. If the line seems to have the form '# 123 filename' - .line and .file directives will appear in the pre-processed output */ -/* Note that input_file.c hand checks for '#' at the beginning of the - first line of the input file. This is because the compiler outputs - #NO_APP at the beginning of its output. */ -/* Also note that comments started like this one will always - work if '/' isn't otherwise defined. */ +/* Characters which start a comment at the beginning of a line. */ const char line_comment_chars[] = "#"; -const char line_separator_chars[] = ""; +/* Characters which may be used to separate multiple commands on a + single line. */ +const char line_separator_chars[] = "`"; -/* Chars that can be used to separate mant from exp in floating point nums. */ +/* Characters which are used to indicate an exponent in a floating + point number. */ const char EXP_CHARS[] = "eE"; /* Chars that mean this number is a floating point constant @@ -87,1807 +83,3061 @@ extern int target_big_endian; const char *arc_target_format = DEFAULT_TARGET_FORMAT; static int byte_order = DEFAULT_BYTE_ORDER; -static segT arcext_section; +extern int arc_get_mach (char *); -/* One of bfd_mach_arc_n. */ -static int arc_mach_type = bfd_mach_arc_6; +/* Forward declaration. */ +static void arc_lcomm (int); +static void arc_option (int); +static void arc_extra_reloc (int); -/* Non-zero if the cpu type has been explicitly specified. */ -static int mach_type_specified_p = 0; +const pseudo_typeS md_pseudo_table[] = + { + /* Make sure that .word is 32 bits. */ + { "word", cons, 4 }, + + { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ + { "lcomm", arc_lcomm, 0 }, + { "lcommon", arc_lcomm, 0 }, + { "cpu", arc_option, 0 }, -/* Non-zero if opcode tables have been initialized. - A .option command must appear before any instructions. */ -static int cpu_tables_init_p = 0; + { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD }, + { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL }, + + { NULL, NULL, 0 } + }; -static struct hash_control *arc_suffix_hash = NULL; - const char *md_shortopts = ""; enum options -{ - OPTION_EB = OPTION_MD_BASE, - OPTION_EL, - OPTION_ARC5, - OPTION_ARC6, - OPTION_ARC7, - OPTION_ARC8, - OPTION_ARC -}; + { + OPTION_EB = OPTION_MD_BASE, + OPTION_EL, + + OPTION_ARC600, + OPTION_ARC601, + OPTION_ARC700, + OPTION_ARCEM, + OPTION_ARCHS, + + OPTION_MCPU, + OPTION_CD, + + /* The following options are deprecated and provided here only for + compatibility reasons. */ + OPTION_USER_MODE, + OPTION_LD_EXT_MASK, + OPTION_SWAP, + OPTION_NORM, + OPTION_BARREL_SHIFT, + OPTION_MIN_MAX, + OPTION_NO_MPY, + OPTION_EA, + OPTION_MUL64, + OPTION_SIMD, + OPTION_SPFP, + OPTION_DPFP, + OPTION_XMAC_D16, + OPTION_XMAC_24, + OPTION_DSP_PACKA, + OPTION_CRC, + OPTION_DVBF, + OPTION_TELEPHONY, + OPTION_XYMEMORY, + OPTION_LOCK, + OPTION_SWAPE, + OPTION_RTSC, + OPTION_FPUDA + }; struct option md_longopts[] = -{ - { "EB", no_argument, NULL, OPTION_EB }, - { "EL", no_argument, NULL, OPTION_EL }, - { "marc5", no_argument, NULL, OPTION_ARC5 }, - { "pre-v6", no_argument, NULL, OPTION_ARC5 }, - { "marc6", no_argument, NULL, OPTION_ARC6 }, - { "marc7", no_argument, NULL, OPTION_ARC7 }, - { "marc8", no_argument, NULL, OPTION_ARC8 }, - { "marc", no_argument, NULL, OPTION_ARC }, - { NULL, no_argument, NULL, 0 } -}; -size_t md_longopts_size = sizeof (md_longopts); + { + { "EB", no_argument, NULL, OPTION_EB }, + { "EL", no_argument, NULL, OPTION_EL }, + { "mcpu", required_argument, NULL, OPTION_MCPU }, + { "mA6", no_argument, NULL, OPTION_ARC600 }, + { "mARC600", no_argument, NULL, OPTION_ARC600 }, + { "mARC601", no_argument, NULL, OPTION_ARC601 }, + { "mARC700", no_argument, NULL, OPTION_ARC700 }, + { "mA7", no_argument, NULL, OPTION_ARC700 }, + { "mEM", no_argument, NULL, OPTION_ARCEM }, + { "mHS", no_argument, NULL, OPTION_ARCHS }, + { "mcode-density", no_argument, NULL, OPTION_CD }, + + /* The following options are deprecated and provided here only for + compatibility reasons. */ + { "mav2em", no_argument, NULL, OPTION_ARCEM }, + { "mav2hs", no_argument, NULL, OPTION_ARCHS }, + { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE }, + { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK }, + { "mswap", no_argument, NULL, OPTION_SWAP }, + { "mnorm", no_argument, NULL, OPTION_NORM }, + { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT }, + { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT }, + { "mmin-max", no_argument, NULL, OPTION_MIN_MAX }, + { "mmin_max", no_argument, NULL, OPTION_MIN_MAX }, + { "mno-mpy", no_argument, NULL, OPTION_NO_MPY }, + { "mea", no_argument, NULL, OPTION_EA }, + { "mEA", no_argument, NULL, OPTION_EA }, + { "mmul64", no_argument, NULL, OPTION_MUL64 }, + { "msimd", no_argument, NULL, OPTION_SIMD}, + { "mspfp", no_argument, NULL, OPTION_SPFP}, + { "mspfp-compact", no_argument, NULL, OPTION_SPFP}, + { "mspfp_compact", no_argument, NULL, OPTION_SPFP}, + { "mspfp-fast", no_argument, NULL, OPTION_SPFP}, + { "mspfp_fast", no_argument, NULL, OPTION_SPFP}, + { "mdpfp", no_argument, NULL, OPTION_DPFP}, + { "mdpfp-compact", no_argument, NULL, OPTION_DPFP}, + { "mdpfp_compact", no_argument, NULL, OPTION_DPFP}, + { "mdpfp-fast", no_argument, NULL, OPTION_DPFP}, + { "mdpfp_fast", no_argument, NULL, OPTION_DPFP}, + { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16}, + { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16}, + { "mmac-24", no_argument, NULL, OPTION_XMAC_24}, + { "mmac_24", no_argument, NULL, OPTION_XMAC_24}, + { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA}, + { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA}, + { "mcrc", no_argument, NULL, OPTION_CRC}, + { "mdvbf", no_argument, NULL, OPTION_DVBF}, + { "mtelephony", no_argument, NULL, OPTION_TELEPHONY}, + { "mxy", no_argument, NULL, OPTION_XYMEMORY}, + { "mlock", no_argument, NULL, OPTION_LOCK}, + { "mswape", no_argument, NULL, OPTION_SWAPE}, + { "mrtsc", no_argument, NULL, OPTION_RTSC}, + { "mfpuda", no_argument, NULL, OPTION_FPUDA}, + + { NULL, no_argument, NULL, 0 } + }; -#define IS_SYMBOL_OPERAND(o) \ - ((o) == 'b' || (o) == 'c' || (o) == 's' || (o) == 'o' || (o) == 'O') - -struct arc_operand_value *get_ext_suffix (char *s); +size_t md_longopts_size = sizeof (md_longopts); -/* Invocation line includes a switch not recognized by the base assembler. - See if it's a processor-specific option. */ +/* Local data and data types. */ -int -md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) -{ - switch (c) - { - case OPTION_ARC5: - arc_mach_type = bfd_mach_arc_5; - break; - case OPTION_ARC: - case OPTION_ARC6: - arc_mach_type = bfd_mach_arc_6; - break; - case OPTION_ARC7: - arc_mach_type = bfd_mach_arc_7; - break; - case OPTION_ARC8: - arc_mach_type = bfd_mach_arc_8; - break; - case OPTION_EB: - byte_order = BIG_ENDIAN; - arc_target_format = "elf32-bigarc"; - break; - case OPTION_EL: - byte_order = LITTLE_ENDIAN; - arc_target_format = "elf32-littlearc"; - break; - default: - return 0; - } - return 1; -} +/* Used since new relocation types are introduced in this + file (DUMMY_RELOC_LITUSE_*). */ +typedef int extended_bfd_reloc_code_real_type; -void -md_show_usage (FILE *stream) +struct arc_fixup { - fprintf (stream, "\ -ARC Options:\n\ - -marc[5|6|7|8] select processor variant (default arc%d)\n\ - -EB assemble code for a big endian cpu\n\ - -EL assemble code for a little endian cpu\n", arc_mach_type + 5); -} + expressionS exp; -/* This function is called once, at assembler startup time. It should - set up all the tables, etc. that the MD part of the assembler will need. - Opcode selection is deferred until later because we might see a .option - command. */ + extended_bfd_reloc_code_real_type reloc; -void -md_begin (void) -{ - /* The endianness can be chosen "at the factory". */ - target_big_endian = byte_order == BIG_ENDIAN; + /* index into arc_operands. */ + unsigned int opindex; - if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type)) - as_warn (_("could not set architecture and machine")); + /* PC-relative, used by internals fixups. */ + unsigned char pcrel; - /* This call is necessary because we need to initialize `arc_operand_map' - which may be needed before we see the first insn. */ - arc_opcode_init_tables (arc_get_opcode_mach (arc_mach_type, - target_big_endian)); -} + /* TRUE if this fixup is for LIMM operand. */ + bfd_boolean islong; +}; -/* Initialize the various opcode and operand tables. - MACH is one of bfd_mach_arc_xxx. */ +struct arc_insn +{ + unsigned int insn; + int nfixups; + struct arc_fixup fixups[MAX_INSN_FIXUPS]; + long limm; + bfd_boolean short_insn; /* Boolean value: TRUE if current insn is + short. */ + bfd_boolean has_limm; /* Boolean value: TRUE if limm field is + valid. */ +}; -static void -init_opcode_tables (int mach) +/* Structure to hold any last two instructions. */ +static struct arc_last_insn { - int i; - char *last; + /* Saved instruction opcode. */ + const struct arc_opcode *opcode; - if ((arc_suffix_hash = hash_new ()) == NULL) - as_fatal (_("virtual memory exhausted")); + /* Boolean value: TRUE if current insn is short. */ + bfd_boolean has_limm; - if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach)) - as_warn (_("could not set architecture and machine")); + /* Boolean value: TRUE if current insn has delay slot. */ + bfd_boolean has_delay_slot; +} arc_last_insns[2]; - /* This initializes a few things in arc-opc.c that we need. - This must be called before the various arc_xxx_supported fns. */ - arc_opcode_init_tables (arc_get_opcode_mach (mach, target_big_endian)); +/* The cpu for which we are generating code. */ +static unsigned arc_target = ARC_OPCODE_BASE; +static const char *arc_target_name = "<all>"; +static unsigned arc_features = 0x00; - /* Only put the first entry of each equivalently named suffix in the - table. */ - last = ""; - for (i = 0; i < arc_suffixes_count; i++) - { - if (strcmp (arc_suffixes[i].name, last) != 0) - hash_insert (arc_suffix_hash, arc_suffixes[i].name, (void *) (arc_suffixes + i)); - last = arc_suffixes[i].name; - } +/* The default architecture. */ +static int arc_mach_type = bfd_mach_arc_arcv2; - /* Since registers don't have a prefix, we put them in the symbol table so - they can't be used as symbols. This also simplifies argument parsing as - we can let gas parse registers for us. The recorded register number is - the address of the register's entry in arc_reg_names. +/* Non-zero if the cpu type has been explicitly specified. */ +static int mach_type_specified_p = 0; - If the register name is already in the table, then the existing - definition is assumed to be from an .ExtCoreRegister pseudo-op. */ +/* The hash table of instruction opcodes. */ +static struct hash_control *arc_opcode_hash; - for (i = 0; i < arc_reg_names_count; i++) - { - if (symbol_find (arc_reg_names[i].name)) - continue; - /* Use symbol_create here instead of symbol_new so we don't try to - output registers into the object file's symbol table. */ - symbol_table_insert (symbol_create (arc_reg_names[i].name, - reg_section, - (valueT) &arc_reg_names[i], - &zero_address_frag)); - } +/* The hash table of register symbols. */ +static struct hash_control *arc_reg_hash; - /* Tell `.option' it's too late. */ - cpu_tables_init_p = 1; +/* A table of CPU names and opcode sets. */ +static const struct cpu_type +{ + const char *name; + unsigned flags; + int mach; + unsigned eflags; + unsigned features; } - -/* Insert an operand value into an instruction. - If REG is non-NULL, it is a register number and ignore VAL. */ - -static arc_insn -arc_insert_operand (arc_insn insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value *reg, - offsetT val, - char *file, - unsigned int line) + cpu_types[] = { - if (operand->bits != 32) - { - long min, max; - offsetT test; - - if ((operand->flags & ARC_OPERAND_SIGNED) != 0) - { - if ((operand->flags & ARC_OPERAND_SIGNOPT) != 0) - max = (1 << operand->bits) - 1; - else - max = (1 << (operand->bits - 1)) - 1; - min = - (1 << (operand->bits - 1)); - } - else - { - max = (1 << operand->bits) - 1; - min = 0; - } + { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600, + E_ARC_MACH_ARC600, 0x00}, + { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700, + E_ARC_MACH_ARC700, 0x00}, + { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, + EF_ARC_CPU_ARCV2EM, 0x00}, + { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, + EF_ARC_CPU_ARCV2HS, ARC_CD}, + { "all", ARC_OPCODE_BASE, bfd_mach_arc_arcv2, + 0x00, 0x00 }, + { 0, 0, 0, 0, 0 } +}; - if ((operand->flags & ARC_OPERAND_NEGATIVE) != 0) - test = - val; - else - test = val; +struct arc_flags +{ + /* Name of the parsed flag. */ + char name[MAX_FLAG_NAME_LENGHT+1]; - if (test < (offsetT) min || test > (offsetT) max) - as_warn_value_out_of_range (_("operand"), test, (offsetT) min, (offsetT) max, file, line); - } + /* The code of the parsed flag. Valid when is not zero. */ + unsigned char code; +}; - if (operand->insert) +/* Used by the arc_reloc_op table. Order is important. */ +#define O_gotoff O_md1 /* @gotoff relocation. */ +#define O_gotpc O_md2 /* @gotpc relocation. */ +#define O_plt O_md3 /* @plt relocation. */ +#define O_sda O_md4 /* @sda relocation. */ +#define O_pcl O_md5 /* @pcl relocation. */ +#define O_tlsgd O_md6 /* @tlsgd relocation. */ +#define O_tlsie O_md7 /* @tlsie relocation. */ +#define O_tpoff9 O_md8 /* @tpoff9 relocation. */ +#define O_tpoff O_md9 /* @tpoff relocation. */ +#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */ +#define O_dtpoff O_md11 /* @dtpoff relocation. */ +#define O_last O_dtpoff + +/* Used to define a bracket as operand in tokens. */ +#define O_bracket O_md32 + +/* Dummy relocation, to be sorted out. */ +#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1) + +#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last) + +/* A table to map the spelling of a relocation operand into an appropriate + bfd_reloc_code_real_type type. The table is assumed to be ordered such + that op-O_literal indexes into it. */ +#define ARC_RELOC_TABLE(op) \ + (&arc_reloc_op[ ((!USER_RELOC_P (op)) \ + ? (abort (), 0) \ + : (int) (op) - (int) O_gotoff) ]) + +#define DEF(NAME, RELOC, REQ) \ + { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ} + +static const struct arc_reloc_op_tag +{ + /* String to lookup. */ + const char *name; + /* Size of the string. */ + size_t length; + /* Which operator to use. */ + operatorT op; + extended_bfd_reloc_code_real_type reloc; + /* Allows complex relocation expression like identifier@reloc + + const. */ + unsigned int complex_expr : 1; +} + arc_reloc_op[] = { - const char *errmsg; + DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1), + DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0), + DEF (plt, BFD_RELOC_ARC_PLT32, 0), + DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1), + DEF (pcl, BFD_RELOC_ARC_PC32, 1), + DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0), + DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0), + DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0), + DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 0), + DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0), + DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 0), + }; - errmsg = NULL; - insn = (*operand->insert) (insn, operand, mods, reg, (long) val, &errmsg); - if (errmsg != (const char *) NULL) - as_warn ("%s", errmsg); +static const int arc_num_reloc_op += sizeof (arc_reloc_op) / sizeof (*arc_reloc_op); + +/* Flags to set in the elf header. */ +static flagword arc_eflag = 0x00; + +/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ +symbolS * GOT_symbol = 0; + +/* Set to TRUE when we assemble instructions. */ +static bfd_boolean assembling_insn = FALSE; + +/* Functions declaration. */ + +static void assemble_tokens (const char *, expressionS *, int, + struct arc_flags *, int); +static const struct arc_opcode *find_opcode_match (const struct arc_opcode *, + expressionS *, int *, + struct arc_flags *, + int, int *); +static void assemble_insn (const struct arc_opcode *, const expressionS *, + int, const struct arc_flags *, int, + struct arc_insn *); +static void emit_insn (struct arc_insn *); +static unsigned insert_operand (unsigned, const struct arc_operand *, + offsetT, char *, unsigned); +static const struct arc_opcode *find_special_case_flag (const char *, + int *, + struct arc_flags *); +static const struct arc_opcode *find_special_case (const char *, + int *, + struct arc_flags *, + expressionS *, int *); +static const struct arc_opcode *find_special_case_pseudo (const char *, + int *, + expressionS *, + int *, + struct arc_flags *); + +/* Functions implementation. */ + +/* Like md_number_to_chars but used for limms. The 4-byte limm value, + is encoded as 'middle-endian' for a little-endian target. FIXME! + this function is used for regular 4 byte instructions as well. */ + +static void +md_number_to_chars_midend (char *buf, + valueT val, + int n) +{ + if (n == 4) + { + md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2); + md_number_to_chars (buf + 2, (val & 0xffff), 2); } else - insn |= (((long) val & ((1 << operand->bits) - 1)) - << operand->shift); - - return insn; + { + md_number_to_chars (buf, val, n); + } } -/* We need to keep a list of fixups. We can't simply generate them as - we go, because that would require us to first create the frag, and - that would screw up references to ``.''. */ +/* Here ends all the ARCompact extension instruction assembling + stuff. */ -struct arc_fixup +static void +arc_extra_reloc (int r_type) { - /* index into `arc_operands' */ - int opindex; - expressionS exp; -}; + char *sym_name, c; + symbolS *sym, *lab = NULL; + + if (*input_line_pointer == '@') + input_line_pointer++; + c = get_symbol_name (&sym_name); + sym = symbol_find_or_make (sym_name); + restore_line_pointer (c); + if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD) + { + ++input_line_pointer; + char *lab_name; + c = get_symbol_name (&lab_name); + lab = symbol_find_or_make (lab_name); + restore_line_pointer (c); + } + fixS *fixP + = fix_new (frag_now, /* Which frag? */ + frag_now_fix (), /* Where in that frag? */ + 2, /* size: 1, 2, or 4 usually. */ + sym, /* X_add_symbol. */ + 0, /* X_add_number. */ + FALSE, /* TRUE if PC-relative relocation. */ + r_type /* Relocation type. */); + fixP->fx_subsy = lab; +} -#define MAX_FIXUPS 5 +static symbolS * +arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED, + symbolS *symbolP, addressT size) +{ + addressT align = 0; + SKIP_WHITESPACE (); -#define MAX_SUFFIXES 5 + if (*input_line_pointer == ',') + { + align = parse_align (1); -/* Compute the reloc type of an expression. - The possibly modified expression is stored in EXPNEW. + if (align == (addressT) -1) + return NULL; + } + else + { + if (size >= 8) + align = 3; + else if (size >= 4) + align = 2; + else if (size >= 2) + align = 1; + else + align = 0; + } - This is used to convert the expressions generated by the %-op's into - the appropriate operand type. It is called for both data in instructions - (operands) and data outside instructions (variables, debugging info, etc.). + bss_alloc (symbolP, size, align); + S_CLEAR_EXTERNAL (symbolP); - Currently supported %-ops: + return symbolP; +} - %st(symbol): represented as "symbol >> 2" - "st" is short for STatus as in the status register (pc) +static void +arc_lcomm (int ignore) +{ + symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal); - DEFAULT_TYPE is the type to use if no special processing is required. + if (symbolP) + symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; +} - DATA_P is non-zero for data or limm values, zero for insn operands. - Remember that the opcode "insertion fns" cannot be used on data, they're - only for inserting operands into insns. They also can't be used for limm - values as the insertion routines don't handle limm values. When called for - insns we return fudged reloc types (real_value - BFD_RELOC_UNUSED). When - called for data or limm values we use real reloc types. */ +/* Select the cpu we're assembling for. */ -static int -get_arc_exp_reloc_type (int data_p, - int default_type, - expressionS *exp, - expressionS *expnew) +static void +arc_option (int ignore ATTRIBUTE_UNUSED) { - /* If the expression is "symbol >> 2" we must change it to just "symbol", - as fix_new_exp can't handle it. Similarly for (symbol - symbol) >> 2. - That's ok though. What's really going on here is that we're using - ">> 2" as a special syntax for specifying BFD_RELOC_ARC_B26. */ + int mach = -1; + char c; + char *cpu; - if (exp->X_op == O_right_shift - && exp->X_op_symbol != NULL - && exp->X_op_symbol->sy_value.X_op == O_constant - && exp->X_op_symbol->sy_value.X_add_number == 2 - && exp->X_add_number == 0) - { - if (exp->X_add_symbol != NULL - && (exp->X_add_symbol->sy_value.X_op == O_constant - || exp->X_add_symbol->sy_value.X_op == O_symbol)) - { - *expnew = *exp; - expnew->X_op = O_symbol; - expnew->X_op_symbol = NULL; - return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J']; - } - else if (exp->X_add_symbol != NULL - && exp->X_add_symbol->sy_value.X_op == O_subtract) - { - *expnew = exp->X_add_symbol->sy_value; - return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J']; - } - } + c = get_symbol_name (&cpu); + mach = arc_get_mach (cpu); + restore_line_pointer (c); - *expnew = *exp; - return default_type; -} - -static int -arc_set_ext_seg (void) -{ - if (!arcext_section) + if (mach == -1) + goto bad_cpu; + + if (!mach_type_specified_p) { - arcext_section = subseg_new (".arcextmap", 0); - bfd_set_section_flags (stdoutput, arcext_section, - SEC_READONLY | SEC_HAS_CONTENTS); + arc_mach_type = mach; + if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach)) + as_fatal ("could not set architecture and machine"); + + mach_type_specified_p = 1; } else - subseg_set (arcext_section, 0); - return 1; + if (arc_mach_type != mach) + as_warn ("Command-line value overrides \".cpu\" directive"); + + demand_empty_rest_of_line (); + + return; + + bad_cpu: + as_bad ("invalid identifier for \".cpu\""); + ignore_rest_of_line (); } +/* Smartly print an expression. */ + static void -arc_extoper (int opertype) +debug_exp (expressionS *t) { - char *name; - char *mode; - char c; - char *p; - int imode = 0; - int number; - struct arc_ext_operand_value *ext_oper; - symbolS *symbolP; - - segT old_sec; - int old_subsec; + const char *name ATTRIBUTE_UNUSED; + const char *namemd ATTRIBUTE_UNUSED; - c = get_symbol_name (&name); - name = xstrdup (name); + pr_debug ("debug_exp: "); - p = name; - while (*p) + switch (t->X_op) { - *p = TOLOWER (*p); - p++; + default: name = "unknown"; break; + case O_illegal: name = "O_illegal"; break; + case O_absent: name = "O_absent"; break; + case O_constant: name = "O_constant"; break; + case O_symbol: name = "O_symbol"; break; + case O_symbol_rva: name = "O_symbol_rva"; break; + case O_register: name = "O_register"; break; + case O_big: name = "O_big"; break; + case O_uminus: name = "O_uminus"; break; + case O_bit_not: name = "O_bit_not"; break; + case O_logical_not: name = "O_logical_not"; break; + case O_multiply: name = "O_multiply"; break; + case O_divide: name = "O_divide"; break; + case O_modulus: name = "O_modulus"; break; + case O_left_shift: name = "O_left_shift"; break; + case O_right_shift: name = "O_right_shift"; break; + case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break; + case O_bit_or_not: name = "O_bit_or_not"; break; + case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break; + case O_bit_and: name = "O_bit_and"; break; + case O_add: name = "O_add"; break; + case O_subtract: name = "O_subtract"; break; + case O_eq: name = "O_eq"; break; + case O_ne: name = "O_ne"; break; + case O_lt: name = "O_lt"; break; + case O_le: name = "O_le"; break; + case O_ge: name = "O_ge"; break; + case O_gt: name = "O_gt"; break; + case O_logical_and: name = "O_logical_and"; break; + case O_logical_or: name = "O_logical_or"; break; + case O_index: name = "O_index"; break; + case O_bracket: name = "O_bracket"; break; } - /* just after name is now '\0' */ - p = input_line_pointer; - (void) restore_line_pointer (c); - SKIP_WHITESPACE (); - - if (*input_line_pointer != ',') + switch (t->X_md) { - as_bad (_("expected comma after operand name")); - ignore_rest_of_line (); - free (name); - return; + default: namemd = "unknown"; break; + case O_gotoff: namemd = "O_gotoff"; break; + case O_gotpc: namemd = "O_gotpc"; break; + case O_plt: namemd = "O_plt"; break; + case O_sda: namemd = "O_sda"; break; + case O_pcl: namemd = "O_pcl"; break; + case O_tlsgd: namemd = "O_tlsgd"; break; + case O_tlsie: namemd = "O_tlsie"; break; + case O_tpoff9: namemd = "O_tpoff9"; break; + case O_tpoff: namemd = "O_tpoff"; break; + case O_dtpoff9: namemd = "O_dtpoff9"; break; + case O_dtpoff: namemd = "O_dtpoff"; break; } - input_line_pointer++; /* skip ',' */ - number = get_absolute_expression (); + pr_debug ("%s (%s, %s, %d, %s)", name, + (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--", + (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--", + (int) t->X_add_number, + (t->X_md) ? namemd : "--"); + pr_debug ("\n"); + fflush (stderr); +} - if (number < 0) - { - as_bad (_("negative operand number %d"), number); - ignore_rest_of_line (); - free (name); - return; - } +/* Parse the arguments to an opcode. */ + +static int +tokenize_arguments (char *str, + expressionS *tok, + int ntok) +{ + char *old_input_line_pointer; + bfd_boolean saw_comma = FALSE; + bfd_boolean saw_arg = FALSE; + int brk_lvl = 0; + int num_args = 0; + const char *p; + int i; + size_t len; + const struct arc_reloc_op_tag *r; + expressionS tmpE; - if (opertype) + memset (tok, 0, sizeof (*tok) * ntok); + + /* Save and restore input_line_pointer around this function. */ + old_input_line_pointer = input_line_pointer; + input_line_pointer = str; + + while (*input_line_pointer) { SKIP_WHITESPACE (); - - if (*input_line_pointer != ',') + switch (*input_line_pointer) { - as_bad (_("expected comma after register-number")); - ignore_rest_of_line (); - free (name); - return; - } + case '\0': + goto fini; + + case ',': + input_line_pointer++; + if (saw_comma || !saw_arg) + goto err; + saw_comma = TRUE; + break; - input_line_pointer++; /* skip ',' */ - mode = input_line_pointer; + case '}': + case ']': + ++input_line_pointer; + --brk_lvl; + if (!saw_arg) + goto err; + tok->X_op = O_bracket; + ++tok; + ++num_args; + break; - if (!strncmp (mode, "r|w", 3)) - { - imode = 0; - input_line_pointer += 3; - } - else - { - if (!strncmp (mode, "r", 1)) - { - imode = ARC_REGISTER_READONLY; - input_line_pointer += 1; - } - else + case '{': + case '[': + input_line_pointer++; + if (brk_lvl) + goto err; + ++brk_lvl; + tok->X_op = O_bracket; + ++tok; + ++num_args; + break; + + case '@': + /* We have labels, function names and relocations, all + starting with @ symbol. Sort them out. */ + if (saw_arg && !saw_comma) + goto err; + + /* Parse @label. */ + tok->X_op = O_symbol; + tok->X_md = O_absent; + expression (tok); + if (*input_line_pointer != '@') + goto normalsymbol; /* This is not a relocation. */ + + /* A relocation opernad has the following form + @identifier@relocation_type. The identifier is already + in tok! */ + if (tok->X_op != O_symbol) { - if (strncmp (mode, "w", 1)) - { - as_bad (_("invalid mode")); - ignore_rest_of_line (); - free (name); - return; - } - else - { - imode = ARC_REGISTER_WRITEONLY; - input_line_pointer += 1; - } + as_bad (_("No valid label relocation operand")); + goto err; } - } - SKIP_WHITESPACE (); - if (1 == opertype) - { - if (*input_line_pointer != ',') + + /* Parse @relocation_type. */ + memset (&tmpE, 0, sizeof (tmpE)); + tmpE.X_op = O_symbol; + expression (&tmpE); + + if (tmpE.X_op != O_symbol) { - as_bad (_("expected comma after register-mode")); - ignore_rest_of_line (); - free (name); - return; + as_bad (_("No relocation operand")); + goto err; } + p = S_GET_NAME (tmpE.X_add_symbol); + len = strlen (p); - input_line_pointer++; /* skip ',' */ + /* Go through known relocation and try to find a match. */ + r = &arc_reloc_op[0]; + for (i = arc_num_reloc_op - 1; i >= 0; i--, r++) + if (len == r->length && memcmp (p, r->name, len) == 0) + break; - if (!strncmp (input_line_pointer, "cannot_shortcut", 15)) + if (i < 0) { - imode |= arc_get_noshortcut_flag (); - input_line_pointer += 15; + as_bad (_("Unknown relocation operand: @%s"), p); + goto err; } - else + tok->X_md = r->op; + tok->X_add_number = tmpE.X_add_number; + if (tmpE.X_add_number && !r->complex_expr) { - if (strncmp (input_line_pointer, "can_shortcut", 12)) - { - as_bad (_("shortcut designator invalid")); - ignore_rest_of_line (); - free (name); - return; - } - else + as_bad (_("Complex relocation operand.")); + goto err; + } + + /* Extra check for TLS: base. */ + if (*input_line_pointer == '@') + { + symbolS *base; + if (tok->X_op_symbol != NULL + || tok->X_op != O_symbol) { - input_line_pointer += 12; + as_bad (_("Unable to parse this reloc")); + goto err; } + input_line_pointer++; + char *sym_name; + char c = get_symbol_name (&sym_name); + base = symbol_find_or_make (sym_name); + tok->X_op = O_subtract; + tok->X_op_symbol = base; + restore_line_pointer (c); } + + debug_exp (tok); + + saw_comma = FALSE; + saw_arg = TRUE; + tok++; + num_args++; + break; + + case '%': + /* Can be a register. */ + ++input_line_pointer; + /* Fall through. */ + default: + + if (saw_arg && !saw_comma) + goto err; + + tok->X_op = O_absent; + expression (tok); + + normalsymbol: + debug_exp (tok); + + if (tok->X_op == O_illegal || tok->X_op == O_absent) + goto err; + + saw_comma = FALSE; + saw_arg = TRUE; + tok++; + num_args++; + break; } } - if ((opertype == 1) && number > 60) + fini: + if (saw_comma || brk_lvl) + goto err; + input_line_pointer = old_input_line_pointer; + + return num_args; + + err: + if (brk_lvl) + as_bad (_("Brackets in operand field incorrect")); + else if (saw_comma) + as_bad (_("extra comma")); + else if (!saw_arg) + as_bad (_("missing argument")); + else + as_bad (_("missing comma or colon")); + input_line_pointer = old_input_line_pointer; + return -1; +} + +/* Parse the flags to a structure. */ + +static int +tokenize_flags (const char *str, + struct arc_flags flags[], + int nflg) +{ + char *old_input_line_pointer; + bfd_boolean saw_flg = FALSE; + bfd_boolean saw_dot = FALSE; + int num_flags = 0; + size_t flgnamelen; + + memset (flags, 0, sizeof (*flags) * nflg); + + /* Save and restore input_line_pointer around this function. */ + old_input_line_pointer = input_line_pointer; + input_line_pointer = (char *) str; + + while (*input_line_pointer) { - as_bad (_("core register value (%d) too large"), number); - ignore_rest_of_line (); - free (name); + switch (*input_line_pointer) + { + case ' ': + case '\0': + goto fini; + + case '.': + input_line_pointer++; + if (saw_dot) + goto err; + saw_dot = TRUE; + saw_flg = FALSE; + break; + + default: + if (saw_flg && !saw_dot) + goto err; + + if (num_flags >= nflg) + goto err; + + flgnamelen = strspn (input_line_pointer, "abcdefghilmnopqrstvwxz"); + if (flgnamelen > MAX_FLAG_NAME_LENGHT) + goto err; + + memcpy (flags->name, input_line_pointer, flgnamelen); + + input_line_pointer += flgnamelen; + flags++; + saw_dot = FALSE; + saw_flg = TRUE; + num_flags++; + break; + } + } + + fini: + input_line_pointer = old_input_line_pointer; + return num_flags; + + err: + if (saw_dot) + as_bad (_("extra dot")); + else if (!saw_flg) + as_bad (_("unrecognized flag")); + else + as_bad (_("failed to parse flags")); + input_line_pointer = old_input_line_pointer; + return -1; +} + +/* The public interface to the instruction assembler. */ + +void +md_assemble (char *str) +{ + char *opname; + expressionS tok[MAX_INSN_ARGS]; + int ntok, nflg; + size_t opnamelen; + struct arc_flags flags[MAX_INSN_FLGS]; + + /* Split off the opcode. */ + opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468"); + opname = xmalloc (opnamelen + 1); + memcpy (opname, str, opnamelen); + opname[opnamelen] = '\0'; + + /* Signalize we are assmbling the instructions. */ + assembling_insn = TRUE; + + /* Tokenize the flags. */ + if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1) + { + as_bad (_("syntax error")); return; } - if ((opertype == 0) && number > 31) + /* Scan up to the end of the mnemonic which must end in space or end + of string. */ + str += opnamelen; + for (; *str != '\0'; str++) + if (*str == ' ') + break; + + /* Tokenize the rest of the line. */ + if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0) { - as_bad (_("condition code value (%d) too large"), number); - ignore_rest_of_line (); - free (name); + as_bad (_("syntax error")); return; } - ext_oper = (struct arc_ext_operand_value *) - xmalloc (sizeof (struct arc_ext_operand_value)); + /* Finish it off. */ + assemble_tokens (opname, tok, ntok, flags, nflg); + assembling_insn = FALSE; +} + +/* Callback to insert a register into the hash table. */ + +static void +declare_register (char *name, int number) +{ + const char *err; + symbolS *regS = symbol_create (name, reg_section, + number, &zero_address_frag); + + err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS); + if (err) + as_fatal ("Inserting \"%s\" into register table failed: %s", + name, err); +} - if (opertype) +/* Construct symbols for each of the general registers. */ + +static void +declare_register_set (void) +{ + int i; + for (i = 0; i < 32; ++i) { - /* If the symbol already exists, point it at the new definition. */ - if ((symbolP = symbol_find (name))) - { - if (S_GET_SEGMENT (symbolP) == reg_section) - S_SET_VALUE (symbolP, (valueT) &ext_oper->operand); - else - { - as_bad (_("attempt to override symbol: %s"), name); - ignore_rest_of_line (); - free (name); - free (ext_oper); - return; - } - } - else + char name[7]; + + sprintf (name, "r%d", i); + declare_register (name, i); + if ((i & 0x01) == 0) { - /* If its not there, add it. */ - symbol_table_insert (symbol_create (name, reg_section, - (valueT) &ext_oper->operand, - &zero_address_frag)); + sprintf (name, "r%dr%d", i, i+1); + declare_register (name, i); } } +} - ext_oper->operand.name = name; - ext_oper->operand.value = number; - ext_oper->operand.type = arc_operand_type (opertype); - ext_oper->operand.flags = imode; +/* Port-specific assembler initialization. This function is called + once, at assembler startup time. */ - ext_oper->next = arc_ext_operands; - arc_ext_operands = ext_oper; +void +md_begin (void) +{ + unsigned int i; - /* OK, now that we know what this operand is, put a description in - the arc extension section of the output file. */ + /* The endianness can be chosen "at the factory". */ + target_big_endian = byte_order == BIG_ENDIAN; - old_sec = now_seg; - old_subsec = now_subseg; + if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type)) + as_warn (_("could not set architecture and machine")); - arc_set_ext_seg (); + /* Set elf header flags. */ + bfd_set_private_flags (stdoutput, arc_eflag); - switch (opertype) + /* Set up a hash table for the instructions. */ + arc_opcode_hash = hash_new (); + if (arc_opcode_hash == NULL) + as_fatal (_("Virtual memory exhausted")); + + /* Initialize the hash table with the insns. */ + for (i = 0; i < arc_num_opcodes;) { - case 0: - p = frag_more (1); - *p = 3 + strlen (name) + 1; - p = frag_more (1); - *p = EXT_COND_CODE; - p = frag_more (1); - *p = number; - p = frag_more (strlen (name) + 1); - strcpy (p, name); - break; - case 1: - p = frag_more (1); - *p = 3 + strlen (name) + 1; - p = frag_more (1); - *p = EXT_CORE_REGISTER; - p = frag_more (1); - *p = number; - p = frag_more (strlen (name) + 1); - strcpy (p, name); - break; - case 2: - p = frag_more (1); - *p = 6 + strlen (name) + 1; - p = frag_more (1); - *p = EXT_AUX_REGISTER; - p = frag_more (1); - *p = number >> 24 & 0xff; - p = frag_more (1); - *p = number >> 16 & 0xff; - p = frag_more (1); - *p = number >> 8 & 0xff; - p = frag_more (1); - *p = number & 0xff; - p = frag_more (strlen (name) + 1); - strcpy (p, name); - break; - default: - as_bad (_("invalid opertype")); - ignore_rest_of_line (); - free (name); - return; - break; + const char *name, *retval; + + name = arc_opcodes[i].name; + retval = hash_insert (arc_opcode_hash, name, (void *) &arc_opcodes[i]); + if (retval) + as_fatal (_("internal error: can't hash opcode '%s': %s"), + name, retval); + + while (++i < arc_num_opcodes + && (arc_opcodes[i].name == name + || !strcmp (arc_opcodes[i].name, name))) + continue; } - subseg_set (old_sec, old_subsec); + /* Register declaration. */ + arc_reg_hash = hash_new (); + if (arc_reg_hash == NULL) + as_fatal (_("Virtual memory exhausted")); - /* Enter all registers into the symbol table. */ + declare_register_set (); + declare_register ("gp", 26); + declare_register ("fp", 27); + declare_register ("sp", 28); + declare_register ("ilink", 29); + declare_register ("ilink1", 29); + declare_register ("ilink2", 30); + declare_register ("blink", 31); - demand_empty_rest_of_line (); + declare_register ("mlo", 57); + declare_register ("mmid", 58); + declare_register ("mhi", 59); + + declare_register ("acc1", 56); + declare_register ("acc2", 57); + + declare_register ("lp_count", 60); + declare_register ("pcl", 63); + + /* Initialize the last instructions. */ + memset (&arc_last_insns[0], 0, sizeof (arc_last_insns)); } -static void -arc_extinst (int ignore ATTRIBUTE_UNUSED) +/* Write a value out to the object file, using the appropriate + endianness. */ + +void +md_number_to_chars (char *buf, + valueT val, + int n) { - char syntax[129]; - char *name; - char *p; - char c; - int suffixcode = -1; - int opcode, subopcode; - int i; - int s_class = 0; - int name_len; - struct arc_opcode *ext_op; + if (target_big_endian) + number_to_chars_bigendian (buf, val, n); + else + number_to_chars_littleendian (buf, val, n); +} - segT old_sec; - int old_subsec; +/* Round up a section size to the appropriate boundary. */ - c = get_symbol_name (&name); - name = xstrdup (name); - strcpy (syntax, name); - name_len = strlen (name); +valueT +md_section_align (segT segment, + valueT size) +{ + int align = bfd_get_section_alignment (stdoutput, segment); - /* just after name is now '\0' */ - p = input_line_pointer; - (void) restore_line_pointer (c); + return ((size + (1 << align) - 1) & (-1 << align)); +} - SKIP_WHITESPACE (); +/* The location from which a PC relative jump should be calculated, + given a PC relative reloc. */ - if (*input_line_pointer != ',') - { - as_bad (_("expected comma after operand name")); - ignore_rest_of_line (); - return; - } +long +md_pcrel_from_section (fixS *fixP, + segT sec) +{ + offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; - input_line_pointer++; /* skip ',' */ - opcode = get_absolute_expression (); + pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset); - SKIP_WHITESPACE (); + if (fixP->fx_addsy != (symbolS *) NULL + && (!S_IS_DEFINED (fixP->fx_addsy) + || S_GET_SEGMENT (fixP->fx_addsy) != sec)) + { + pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy)); + + /* The symbol is undefined (or is defined but not in this section). + Let the linker figure it out. */ + return 0; + } - if (*input_line_pointer != ',') + if ((int) fixP->fx_r_type < 0) { - as_bad (_("expected comma after opcode")); - ignore_rest_of_line (); - return; + /* These are the "internal" relocations. Align them to + 32 bit boundary (PCL), for the moment. */ + base &= ~3; + } + else + { + switch (fixP->fx_r_type) + { + case BFD_RELOC_ARC_PC32: + /* The hardware calculates relative to the start of the + insn, but this relocation is relative to location of the + LIMM, compensate. TIP: the base always needs to be + substracted by 4 as we do not support this type of PCrel + relocation for short instructions. */ + base -= fixP->fx_where - fixP->fx_dot_value; + gas_assert ((fixP->fx_where - fixP->fx_dot_value) == 4); + /* Fall through. */ + case BFD_RELOC_ARC_PLT32: + case BFD_RELOC_ARC_S25H_PCREL_PLT: + case BFD_RELOC_ARC_S21H_PCREL_PLT: + case BFD_RELOC_ARC_S25W_PCREL_PLT: + case BFD_RELOC_ARC_S21W_PCREL_PLT: + + case BFD_RELOC_ARC_S21H_PCREL: + case BFD_RELOC_ARC_S25H_PCREL: + case BFD_RELOC_ARC_S13_PCREL: + case BFD_RELOC_ARC_S21W_PCREL: + case BFD_RELOC_ARC_S25W_PCREL: + base &= ~3; + break; + default: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("unhandled reloc %s in md_pcrel_from_section"), + bfd_get_reloc_code_name (fixP->fx_r_type)); + break; + } } - input_line_pointer++; /* skip ',' */ - subopcode = get_absolute_expression (); + pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n", + fixP->fx_frag->fr_address, fixP->fx_where, base, + fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)", + fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0); - if (subopcode < 0) + return base; +} + +/* Given a BFD relocation find the coresponding operand. */ + +static const struct arc_operand * +find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc) +{ + unsigned i; + + for (i = 0; i < arc_num_operands; i++) + if (arc_operands[i].default_reloc == reloc) + return &arc_operands[i]; + return NULL; +} + +/* Apply a fixup to the object code. At this point all symbol values + should be fully resolved, and we attempt to completely resolve the + reloc. If we can not do that, we determine the correct reloc code + and put it back in the fixup. To indicate that a fixup has been + eliminated, set fixP->fx_done. */ + +void +md_apply_fix (fixS *fixP, + valueT *valP, + segT seg) +{ + char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; + valueT value = *valP; + unsigned insn = 0; + symbolS *fx_addsy, *fx_subsy; + offsetT fx_offset; + segT add_symbol_segment = absolute_section; + segT sub_symbol_segment = absolute_section; + const struct arc_operand *operand = NULL; + extended_bfd_reloc_code_real_type reloc; + + pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n", + fixP->fx_file, fixP->fx_line, fixP->fx_r_type, + ((int) fixP->fx_r_type < 0) ? "Internal": + bfd_get_reloc_code_name (fixP->fx_r_type), value, + fixP->fx_offset); + + fx_addsy = fixP->fx_addsy; + fx_subsy = fixP->fx_subsy; + fx_offset = 0; + + if (fx_addsy) { - as_bad (_("negative subopcode %d"), subopcode); - ignore_rest_of_line (); - return; + add_symbol_segment = S_GET_SEGMENT (fx_addsy); } - if (subopcode) + if (fx_subsy + && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF + && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9 + && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD) { - if (3 != opcode) + resolve_symbol_value (fx_subsy); + sub_symbol_segment = S_GET_SEGMENT (fx_subsy); + + if (sub_symbol_segment == absolute_section) { - as_bad (_("subcode value found when opcode not equal 0x03")); - ignore_rest_of_line (); - return; + /* The symbol is really a constant. */ + fx_offset -= S_GET_VALUE (fx_subsy); + fx_subsy = NULL; } else { - if (subopcode < 0x09 || subopcode == 0x3f) - { - as_bad (_("invalid subopcode %d"), subopcode); - ignore_rest_of_line (); - return; - } + as_bad_where (fixP->fx_file, fixP->fx_line, + _("can't resolve `%s' {%s section} - `%s' {%s section}"), + fx_addsy ? S_GET_NAME (fx_addsy) : "0", + segment_name (add_symbol_segment), + S_GET_NAME (fx_subsy), + segment_name (sub_symbol_segment)); + return; } } - SKIP_WHITESPACE (); - - if (*input_line_pointer != ',') + if (fx_addsy + && !S_IS_WEAK (fx_addsy)) { - as_bad (_("expected comma after subopcode")); - ignore_rest_of_line (); - return; + if (add_symbol_segment == seg + && fixP->fx_pcrel) + { + value += S_GET_VALUE (fx_addsy); + value -= md_pcrel_from_section (fixP, seg); + fx_addsy = NULL; + fixP->fx_pcrel = FALSE; + } + else if (add_symbol_segment == absolute_section) + { + value = fixP->fx_offset; + fx_offset += S_GET_VALUE (fixP->fx_addsy); + fx_addsy = NULL; + fixP->fx_pcrel = FALSE; + } } - input_line_pointer++; /* skip ',' */ + if (!fx_addsy) + fixP->fx_done = TRUE; - for (i = 0; i < (int) MAXSUFFIXCLASS; i++) + if (fixP->fx_pcrel) { - if (!strncmp (suffixclass[i].name,input_line_pointer, suffixclass[i].len)) + if (fx_addsy + && ((S_IS_DEFINED (fx_addsy) + && S_GET_SEGMENT (fx_addsy) != seg) + || S_IS_WEAK (fx_addsy))) + value += md_pcrel_from_section (fixP, seg); + + switch (fixP->fx_r_type) { - suffixcode = i; - input_line_pointer += suffixclass[i].len; + case BFD_RELOC_ARC_32_ME: + /* This is a pc-relative value in a LIMM. Adjust it to the + address of the instruction not to the address of the + LIMM. Note: it is not anylonger valid this afirmation as + the linker consider ARC_PC32 a fixup to entire 64 bit + insn. */ + fixP->fx_offset += fixP->fx_frag->fr_address; + /* Fall through. */ + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_ARC_PC32; + /* Fall through. */ + case BFD_RELOC_ARC_PC32: + break; + default: + if ((int) fixP->fx_r_type < 0) + as_fatal (_("PC relative relocation not allowed for (internal) type %d"), + fixP->fx_r_type); break; } } - if (-1 == suffixcode) + pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n", + fixP->fx_file, fixP->fx_line, fixP->fx_r_type, + ((int) fixP->fx_r_type < 0) ? "Internal": + bfd_get_reloc_code_name (fixP->fx_r_type), value, + fixP->fx_offset); + + if (!fixP->fx_done) + return; + + /* Addjust the value if we have a constant. */ + value += fx_offset; + + /* For hosts with longs bigger than 32-bits make sure that the top + bits of a 32-bit negative value read in by the parser are set, + so that the correct comparisons are made. */ + if (value & 0x80000000) + value |= (-1L << 31); + + reloc = fixP->fx_r_type; + switch (reloc) { - as_bad (_("invalid suffix class")); - ignore_rest_of_line (); + case BFD_RELOC_8: + case BFD_RELOC_16: + case BFD_RELOC_24: + case BFD_RELOC_32: + case BFD_RELOC_64: + md_number_to_chars (fixpos, value, fixP->fx_size); return; - } - SKIP_WHITESPACE (); + case BFD_RELOC_ARC_GOTPC32: + /* I cannot fix an GOTPC relocation because I need to relax it + from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */ + as_bad (_("Unsupported operation on reloc")); + return; + case BFD_RELOC_ARC_GOTOFF: + case BFD_RELOC_ARC_32_ME: + case BFD_RELOC_ARC_PC32: + md_number_to_chars_midend (fixpos, value, fixP->fx_size); + return; - if (*input_line_pointer != ',') - { - as_bad (_("expected comma after suffix class")); - ignore_rest_of_line (); + case BFD_RELOC_ARC_PLT32: + md_number_to_chars_midend (fixpos, value, fixP->fx_size); return; - } - input_line_pointer++; /* skip ',' */ + case BFD_RELOC_ARC_S25H_PCREL_PLT: + reloc = BFD_RELOC_ARC_S25W_PCREL; + goto solve_plt; + + case BFD_RELOC_ARC_S21H_PCREL_PLT: + reloc = BFD_RELOC_ARC_S21H_PCREL; + goto solve_plt; + + case BFD_RELOC_ARC_S25W_PCREL_PLT: + reloc = BFD_RELOC_ARC_S25W_PCREL; + goto solve_plt; + + case BFD_RELOC_ARC_S21W_PCREL_PLT: + reloc = BFD_RELOC_ARC_S21W_PCREL; + + case BFD_RELOC_ARC_S25W_PCREL: + case BFD_RELOC_ARC_S21W_PCREL: + case BFD_RELOC_ARC_S21H_PCREL: + case BFD_RELOC_ARC_S25H_PCREL: + case BFD_RELOC_ARC_S13_PCREL: + solve_plt: + operand = find_operand_for_reloc (reloc); + gas_assert (operand); + break; - for (i = 0; i < (int) MAXSYNTAXCLASS; i++) - { - if (!strncmp (syntaxclass[i].name,input_line_pointer, syntaxclass[i].len)) + case BFD_RELOC_ARC_TLS_DTPOFF: + case BFD_RELOC_ARC_TLS_LE_32: + if (fixP->fx_done) { - s_class = syntaxclass[i].s_class; - input_line_pointer += syntaxclass[i].len; - break; + gas_assert (!fixP->fx_addsy); + gas_assert (!fixP->fx_subsy); + md_number_to_chars_midend (fixpos, value, fixP->fx_size); + return; } - } + else + { + value = fixP->fx_offset; + fixP->fx_offset = 0; + } + /* Fall through. */ + case BFD_RELOC_ARC_TLS_GD_GOT: + case BFD_RELOC_ARC_TLS_IE_GOT: + S_SET_THREAD_LOCAL (fixP->fx_addsy); + md_number_to_chars_midend (fixpos, value, fixP->fx_size); + return; - if (0 == (SYNTAX_VALID & s_class)) - { - as_bad (_("invalid syntax class")); - ignore_rest_of_line (); + case BFD_RELOC_ARC_TLS_GD_LD: + gas_assert (!fixP->fx_offset); + if (fixP->fx_subsy) + fixP->fx_offset + = (S_GET_VALUE (fixP->fx_subsy) + - fixP->fx_frag->fr_address- fixP->fx_where); + fixP->fx_subsy = NULL; + /* Fall through. */ + case BFD_RELOC_ARC_TLS_GD_CALL: + /* These two relocs are there just to allow ld to change the tls + model for this symbol, by patching the code. */ + /* Fall through. */ + /* The offset - and scale, if any - will be installed by the + linker. */ + gas_assert (!fixP->fx_done); + S_SET_THREAD_LOCAL (fixP->fx_addsy); return; + + case BFD_RELOC_ARC_TLS_LE_S9: + case BFD_RELOC_ARC_TLS_DTPOFF_S9: + as_bad (_("TLS_*_S9 relocs are not supported yet")); + break; + + default: + { + if ((int) fixP->fx_r_type >= 0) + as_fatal (_("unhandled relocation type %s"), + bfd_get_reloc_code_name (fixP->fx_r_type)); + + /* The rest of these fixups needs to be completely resolved as + constants. */ + if (fixP->fx_addsy != 0 + && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("non-absolute expression in constant field")); + + gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands); + operand = &arc_operands[-(int) fixP->fx_r_type]; + break; + } } - if ((0x3 == opcode) & (s_class & SYNTAX_3OP)) + if (target_big_endian) { - as_bad (_("opcode 0x3 and SYNTAX_3OP invalid")); - ignore_rest_of_line (); - return; + switch (fixP->fx_size) + { + case 4: + insn = bfd_getb32 (fixpos); + break; + case 2: + insn = bfd_getb16 (fixpos); + break; + default: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("unknown fixup size")); + } } - - switch (suffixcode) + else { - case 0: - strcat (syntax, "%.q%.f "); - break; - case 1: - strcat (syntax, "%.f "); - break; - case 2: - strcat (syntax, "%.q "); - break; - case 3: - strcat (syntax, " "); - break; - default: - as_bad (_("unknown suffix class")); - ignore_rest_of_line (); - return; - break; - }; + insn = 0; + switch (fixP->fx_size) + { + case 4: + insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2); + break; + case 2: + insn = bfd_getl16 (fixpos); + break; + default: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("unknown fixup size")); + } + } - strcat (syntax, ((opcode == 0x3) ? "%a,%b" : ((s_class & SYNTAX_3OP) ? "%a,%b,%c" : "%b,%c"))); - if (suffixcode < 2) - strcat (syntax, "%F"); - strcat (syntax, "%S%L"); - - ext_op = (struct arc_opcode *) xmalloc (sizeof (struct arc_opcode)); - ext_op->syntax = xstrdup (syntax); - - ext_op->mask = I (-1) | ((0x3 == opcode) ? C (-1) : 0); - ext_op->value = I (opcode) | ((0x3 == opcode) ? C (subopcode) : 0); - ext_op->flags = s_class; - ext_op->next_asm = arc_ext_opcodes; - ext_op->next_dis = arc_ext_opcodes; - arc_ext_opcodes = ext_op; - - /* OK, now that we know what this inst is, put a description in the - arc extension section of the output file. */ - - old_sec = now_seg; - old_subsec = now_subseg; - - arc_set_ext_seg (); - - p = frag_more (1); - *p = 5 + name_len + 1; - p = frag_more (1); - *p = EXT_INSTRUCTION; - p = frag_more (1); - *p = opcode; - p = frag_more (1); - *p = subopcode; - p = frag_more (1); - *p = (s_class & (OP1_MUST_BE_IMM | OP1_IMM_IMPLIED) ? IGNORE_FIRST_OPD : 0); - p = frag_more (name_len); - strncpy (p, syntax, name_len); - p = frag_more (1); - *p = '\0'; - - subseg_set (old_sec, old_subsec); + insn = insert_operand (insn, operand, (offsetT) value, + fixP->fx_file, fixP->fx_line); - demand_empty_rest_of_line (); + md_number_to_chars_midend (fixpos, insn, fixP->fx_size); } -static void -arc_common (int localScope) +/* Prepare machine-dependent frags for relaxation. + + Called just before relaxation starts. Any symbol that is now undefined + will not become defined. + + Return the correct fr_subtype in the frag. + + Return the initial "guess for fr_var" to caller. The guess for fr_var + is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix + or fr_var contributes to our returned value. + + Although it may not be explicit in the frag, pretend + fr_var starts with a value. */ + +int +md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, + segT segment ATTRIBUTE_UNUSED) { - char *name; - char c; - char *p; - int align, size; - symbolS *symbolP; - - c = get_symbol_name (&name); - /* just after name is now '\0' */ - p = input_line_pointer; - (void) restore_line_pointer (c); - SKIP_WHITESPACE (); + int growth = 4; - if (*input_line_pointer != ',') - { - as_bad (_("expected comma after symbol name")); - ignore_rest_of_line (); - return; - } + fragP->fr_var = 4; + pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n", + fragP->fr_file, fragP->fr_line, growth); - input_line_pointer++; /* skip ',' */ - size = get_absolute_expression (); + as_fatal (_("md_estimate_size_before_relax\n")); + return growth; +} - if (size < 0) - { - as_bad (_("negative symbol length")); - ignore_rest_of_line (); - return; - } +/* Translate internal representation of relocation info to BFD target + format. */ - *p = 0; - symbolP = symbol_find_or_make (name); - *p = c; +arelent * +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, + fixS *fixP) +{ + arelent *reloc; + bfd_reloc_code_real_type code; - if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) - { - as_bad (_("ignoring attempt to re-define symbol")); - ignore_rest_of_line (); - return; - } - if (((int) S_GET_VALUE (symbolP) != 0) \ - && ((int) S_GET_VALUE (symbolP) != size)) + reloc = (arelent *) xmalloc (sizeof (* reloc)); + reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); + reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; + + /* Make sure none of our internal relocations make it this far. + They'd better have been fully resolved by this point. */ + gas_assert ((int) fixP->fx_r_type > 0); + + code = fixP->fx_r_type; + + /* if we have something like add gp, pcl, + _GLOBAL_OFFSET_TABLE_@gotpc. */ + if (code == BFD_RELOC_ARC_GOTPC32 + && GOT_symbol + && fixP->fx_addsy == GOT_symbol) + code = BFD_RELOC_ARC_GOTPC; + + reloc->howto = bfd_reloc_type_lookup (stdoutput, code); + if (reloc->howto == NULL) { - as_warn (_("length of symbol \"%s\" already %ld, ignoring %d"), - S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); + as_bad_where (fixP->fx_file, fixP->fx_line, + _("cannot represent `%s' relocation in object file"), + bfd_get_reloc_code_name (code)); + return NULL; } - gas_assert (symbolP->sy_frag == &zero_address_frag); - /* Now parse the alignment field. This field is optional for - local and global symbols. Default alignment is zero. */ - if (*input_line_pointer == ',') + if (!fixP->fx_pcrel != !reloc->howto->pc_relative) + as_fatal (_("internal error? cannot generate `%s' relocation"), + bfd_get_reloc_code_name (code)); + + gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); + + if (code == BFD_RELOC_ARC_TLS_DTPOFF + || code == BFD_RELOC_ARC_TLS_DTPOFF_S9) { - input_line_pointer++; - align = get_absolute_expression (); - if (align < 0) + asymbol *sym + = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL; + /* We just want to store a 24 bit index, but we have to wait + till after write_contents has been called via + bfd_map_over_sections before we can get the index from + _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs + function is elf32-arc.c has to pick up the slack. + Unfortunately, this leads to problems with hosts that have + pointers wider than long (bfd_vma). There would be various + ways to handle this, all error-prone :-( */ + reloc->addend = (bfd_vma) sym; + if ((asymbol *) reloc->addend != sym) { - align = 0; - as_warn (_("assuming symbol alignment of zero")); + as_bad ("Can't store pointer\n"); + return NULL; } } else - align = 0; + reloc->addend = fixP->fx_offset; - if (localScope != 0) - { - segT old_sec; - int old_subsec; - char *pfrag; - - old_sec = now_seg; - old_subsec = now_subseg; - record_alignment (bss_section, align); - subseg_set (bss_section, 0); /* ??? subseg_set (bss_section, 1); ??? */ - - if (align) - /* Do alignment. */ - frag_align (align, 0, 0); - - /* Detach from old frag. */ - if (S_GET_SEGMENT (symbolP) == bss_section) - symbolP->sy_frag->fr_symbol = NULL; - - symbolP->sy_frag = frag_now; - pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, - (offsetT) size, (char *) 0); - *pfrag = 0; - - S_SET_SIZE (symbolP, size); - S_SET_SEGMENT (symbolP, bss_section); - S_CLEAR_EXTERNAL (symbolP); - symbol_get_obj (symbolP)->local = 1; - subseg_set (old_sec, old_subsec); - } - else - { - S_SET_VALUE (symbolP, (valueT) size); - S_SET_ALIGN (symbolP, align); - S_SET_EXTERNAL (symbolP); - S_SET_SEGMENT (symbolP, bfd_com_section_ptr); - } + return reloc; +} - symbolP->bsym->flags |= BSF_OBJECT; +/* Perform post-processing of machine-dependent frags after relaxation. + Called after relaxation is finished. + In: Address of frag. + fr_type == rs_machine_dependent. + fr_subtype is what the address relaxed to. - demand_empty_rest_of_line (); -} - -/* Select the cpu we're assembling for. */ + Out: Any fixS:s and constants are set up. */ -static void -arc_option (int ignore ATTRIBUTE_UNUSED) +void +md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, + segT segment ATTRIBUTE_UNUSED, + fragS *fragP ATTRIBUTE_UNUSED) { - extern int arc_get_mach (char *); - int mach; - char c; - char *cpu; + pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n", + fragP->fr_file, fragP->fr_line, + fragP->fr_subtype, fragP->fr_fix, fragP->fr_var); + abort (); +} - c = get_symbol_name (&cpu); - mach = arc_get_mach (cpu); - (void) restore_line_pointer (c); +/* We have no need to default values of symbols. We could catch + register names here, but that is handled by inserting them all in + the symbol table to begin with. */ - /* If an instruction has already been seen, it's too late. */ - if (cpu_tables_init_p) +symbolS * +md_undefined_symbol (char *name) +{ + /* The arc abi demands that a GOT[0] should be referencible as + [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a + GOTPC reference to _GLOBAL_OFFSET_TABLE_. */ + if (((*name == '_') + && (*(name+1) == 'G') + && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)) + || ((*name == '_') + && (*(name+1) == 'D') + && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0))) { - as_bad (_("\".option\" directive must appear before any instructions")); - ignore_rest_of_line (); - return; - } - - if (mach == -1) - goto bad_cpu; + if (!GOT_symbol) + { + if (symbol_find (name)) + as_bad ("GOT already in symbol table"); - if (mach_type_specified_p && mach != arc_mach_type) - { - as_bad (_("\".option\" directive conflicts with initial definition")); - ignore_rest_of_line (); - return; + GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section, + (valueT) 0, &zero_address_frag); + }; + return GOT_symbol; } - else - { - /* The cpu may have been selected on the command line. */ - if (mach != arc_mach_type) - as_warn (_("\".option\" directive overrides command-line (default) value")); - arc_mach_type = mach; - if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach)) - as_fatal (_("could not set architecture and machine")); - mach_type_specified_p = 1; - } - demand_empty_rest_of_line (); - return; - - bad_cpu: - as_bad (_("invalid identifier for \".option\"")); - ignore_rest_of_line (); + return NULL; } - + +/* Turn a string in input_line_pointer into a floating point constant + of type type, and store the appropriate bytes in *litP. The number + of LITTLENUMS emitted is stored in *sizeP. An error message is + returned, or NULL on OK. */ + char * md_atof (int type, char *litP, int *sizeP) { - return ieee_md_atof (type, litP, sizeP, TRUE); + return ieee_md_atof (type, litP, sizeP, target_big_endian); } -/* Write a value out to the object file, using the appropriate - endianness. */ +/* Called for any expression that can not be recognized. When the + function is called, `input_line_pointer' will point to the start of + the expression. */ void -md_number_to_chars (char *buf, valueT val, int n) +md_operand (expressionS *expressionP ATTRIBUTE_UNUSED) { - if (target_big_endian) - number_to_chars_bigendian (buf, val, n); - else - number_to_chars_littleendian (buf, val, n); + char *p = input_line_pointer; + if (*p == '@') + { + input_line_pointer++; + expressionP->X_op = O_symbol; + expression (expressionP); + } } -/* Round up a section size to the appropriate boundary. */ +/* This function is called from the function 'expression', it attempts + to parse special names (in our case register names). It fills in + the expression with the identified register. It returns TRUE if + it is a register and FALSE otherwise. */ -valueT -md_section_align (segT segment, valueT size) +bfd_boolean +arc_parse_name (const char *name, + struct expressionS *e) { - int align = bfd_get_section_alignment (stdoutput, segment); + struct symbol *sym; - return ((size + (1 << align) - 1) & (-1 << align)); + if (!assembling_insn) + return FALSE; + + /* Handle only registers. */ + if (e->X_op != O_absent) + return FALSE; + + sym = hash_find (arc_reg_hash, name); + if (sym) + { + e->X_op = O_register; + e->X_add_number = S_GET_VALUE (sym); + return TRUE; + } + return FALSE; } -/* We don't have any form of relaxing. */ +/* md_parse_option + Invocation line includes a switch not recognized by the base assembler. + See if it's a processor-specific option. + + New options (supported) are: + + -mcpu=<cpu name> Assemble for selected processor + -EB/-mbig-endian Big-endian + -EL/-mlittle-endian Little-endian + + The following CPU names are recognized: + arc700, av2em, av2hs. */ int -md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, - asection *seg ATTRIBUTE_UNUSED) +md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) { - as_fatal (_("relaxation not supported\n")); + int cpu_flags = EF_ARC_CPU_GENERIC; + + switch (c) + { + case OPTION_ARC600: + case OPTION_ARC601: + return md_parse_option (OPTION_MCPU, "arc600"); + + case OPTION_ARC700: + return md_parse_option (OPTION_MCPU, "arc700"); + + case OPTION_ARCEM: + return md_parse_option (OPTION_MCPU, "arcem"); + + case OPTION_ARCHS: + return md_parse_option (OPTION_MCPU, "archs"); + + case OPTION_MCPU: + { + int i; + char *s = alloca (strlen (arg) + 1); + + { + char *t = s; + char *arg1 = arg; + + do + *t = TOLOWER (*arg1++); + while (*t++); + } + + for (i = 0; cpu_types[i].name; ++i) + { + if (!strcmp (cpu_types[i].name, s)) + { + arc_target = cpu_types[i].flags; + arc_target_name = cpu_types[i].name; + arc_features = cpu_types[i].features; + arc_mach_type = cpu_types[i].mach; + cpu_flags = cpu_types[i].eflags; + + mach_type_specified_p = 1; + break; + } + } + + if (!cpu_types[i].name) + { + as_fatal (_("unknown architecture: %s\n"), arg); + } + break; + } + + case OPTION_EB: + arc_target_format = "elf32-bigarc"; + byte_order = BIG_ENDIAN; + break; + + case OPTION_EL: + arc_target_format = "elf32-littlearc"; + byte_order = LITTLE_ENDIAN; + break; + + case OPTION_CD: + /* This option has an effect only on ARC EM. */ + if (arc_target & ARC_OPCODE_ARCv2EM) + arc_features |= ARC_CD; + break; + + case OPTION_USER_MODE: + case OPTION_LD_EXT_MASK: + case OPTION_SWAP: + case OPTION_NORM: + case OPTION_BARREL_SHIFT: + case OPTION_MIN_MAX: + case OPTION_NO_MPY: + case OPTION_EA: + case OPTION_MUL64: + case OPTION_SIMD: + case OPTION_SPFP: + case OPTION_DPFP: + case OPTION_XMAC_D16: + case OPTION_XMAC_24: + case OPTION_DSP_PACKA: + case OPTION_CRC: + case OPTION_DVBF: + case OPTION_TELEPHONY: + case OPTION_XYMEMORY: + case OPTION_LOCK: + case OPTION_SWAPE: + case OPTION_RTSC: + case OPTION_FPUDA: + /* Dummy options. */ + + default: + return 0; + } + + if (cpu_flags != EF_ARC_CPU_GENERIC) + arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags; + return 1; } -/* Convert a machine dependent frag. We never generate these. */ - void -md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, - asection *sec ATTRIBUTE_UNUSED, - fragS *fragp ATTRIBUTE_UNUSED) +md_show_usage (FILE *stream) { - abort (); + fprintf (stream, _("ARC-specific assembler options:\n")); + + fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n"); + fprintf (stream, + " -mcode-density\t enable code density option for ARC EM\n"); + + fprintf (stream, _("\ + -EB assemble code for a big-endian cpu\n")); + fprintf (stream, _("\ + -EL assemble code for a little-endian cpu\n")); } static void -arc_code_symbol (expressionS *expressionP) +preprocess_operands (const struct arc_opcode *opcode, + expressionS *tok, + int ntok) { - if (expressionP->X_op == O_symbol && expressionP->X_add_number == 0) - { - expressionS two; - - expressionP->X_op = O_right_shift; - expressionP->X_add_symbol->sy_value.X_op = O_constant; - two.X_op = O_constant; - two.X_add_symbol = two.X_op_symbol = NULL; - two.X_add_number = 2; - expressionP->X_op_symbol = make_expr_symbol (&two); - } - /* Allow %st(sym1-sym2) */ - else if (expressionP->X_op == O_subtract - && expressionP->X_add_symbol != NULL - && expressionP->X_op_symbol != NULL - && expressionP->X_add_number == 0) + int i; + size_t len; + const char *p; + unsigned j; + const struct arc_aux_reg *auxr; + + for (i = 0; i < ntok; i++) { - expressionS two; - - expressionP->X_add_symbol = make_expr_symbol (expressionP); - expressionP->X_op = O_right_shift; - two.X_op = O_constant; - two.X_add_symbol = two.X_op_symbol = NULL; - two.X_add_number = 2; - expressionP->X_op_symbol = make_expr_symbol (&two); + switch (tok[i].X_op) + { + case O_illegal: + case O_absent: + break; /* Throw and error. */ + + case O_symbol: + if (opcode->class != AUXREG) + break; + /* Convert the symbol to a constant if possible. */ + p = S_GET_NAME (tok[i].X_add_symbol); + len = strlen (p); + + auxr = &arc_aux_regs[0]; + for (j = 0; j < arc_num_aux_regs; j++, auxr++) + if (len == auxr->length + && strcasecmp (auxr->name, p) == 0) + { + tok[i].X_op = O_constant; + tok[i].X_add_number = auxr->address; + break; + } + break; + default: + break; + } } - else - as_bad (_("expression too complex code symbol")); } -/* Parse an operand that is machine-specific. +/* Given an opcode name, pre-tockenized set of argumenst and the + opcode flags, take it all the way through emission. */ - The ARC has a special %-op to adjust addresses so they're usable in - branches. The "st" is short for the STatus register. - ??? Later expand this to take a flags value too. - - ??? We can't create new expression types so we map the %-op's onto the - existing syntax. This means that the user could use the chosen syntax - to achieve the same effect. */ - -void -md_operand (expressionS *expressionP) +static void +assemble_tokens (const char *opname, + expressionS *tok, + int ntok, + struct arc_flags *pflags, + int nflgs) { - char *p = input_line_pointer; + bfd_boolean found_something = FALSE; + const struct arc_opcode *opcode; + int cpumatch = 1; - if (*p != '%') - return; + /* Search opcodes. */ + opcode = (const struct arc_opcode *) hash_find (arc_opcode_hash, opname); + + /* Couldn't find opcode conventional way, try special cases. */ + if (!opcode) + opcode = find_special_case (opname, &nflgs, pflags, tok, &ntok); - if (strncmp (p, "%st(", 4) == 0) + if (opcode) { - input_line_pointer += 4; - expression (expressionP); - if (*input_line_pointer != ')') + pr_debug ("%s:%d: assemble_tokens: %s trying opcode 0x%08X\n", + frag_now->fr_file, frag_now->fr_line, opcode->name, + opcode->opcode); + + preprocess_operands (opcode, tok, ntok); + + found_something = TRUE; + opcode = find_opcode_match (opcode, tok, &ntok, pflags, nflgs, &cpumatch); + if (opcode) { - as_bad (_("missing ')' in %%-op")); + struct arc_insn insn; + assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn); + emit_insn (&insn); return; } - ++input_line_pointer; - arc_code_symbol (expressionP); } - else - { - /* It could be a register. */ - int i, l; - struct arc_ext_operand_value *ext_oper = arc_ext_operands; - p++; - while (ext_oper) - { - l = strlen (ext_oper->operand.name); - if (!strncmp (p, ext_oper->operand.name, l) && !ISALNUM (*(p + l))) - { - input_line_pointer += l + 1; - expressionP->X_op = O_register; - expressionP->X_add_number = (offsetT) &ext_oper->operand; - return; - } - ext_oper = ext_oper->next; - } - for (i = 0; i < arc_reg_names_count; i++) - { - l = strlen (arc_reg_names[i].name); - if (!strncmp (p, arc_reg_names[i].name, l) && !ISALNUM (*(p + l))) - { - input_line_pointer += l + 1; - expressionP->X_op = O_register; - expressionP->X_add_number = (offsetT) &arc_reg_names[i]; - break; - } - } + if (found_something) + { + if (cpumatch) + as_bad (_("inappropriate arguments for opcode '%s'"), opname); + else + as_bad (_("opcode '%s' not supported for target %s"), opname, + arc_target_name); } + else + as_bad (_("unknown opcode '%s'"), opname); } -/* We have no need to default values of symbols. - We could catch register names here, but that is handled by inserting - them all in the symbol table to begin with. */ +/* Used to find special case opcode. */ -symbolS * -md_undefined_symbol (char *name ATTRIBUTE_UNUSED) +static const struct arc_opcode * +find_special_case (const char *opname, + int *nflgs, + struct arc_flags *pflags, + expressionS *tok, + int *ntok) { - return 0; -} - -/* Functions concerning expressions. */ + const struct arc_opcode *opcode; -/* Parse a .byte, .word, etc. expression. + opcode = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags); - Values for the status register are specified with %st(label). - `label' will be right shifted by 2. */ + if (opcode == NULL) + opcode = find_special_case_flag (opname, nflgs, pflags); -bfd_reloc_code_real_type -arc_parse_cons_expression (expressionS *exp, - unsigned int nbytes ATTRIBUTE_UNUSED) + return opcode; +} + +/* Swap operand tokens. */ + +static void +swap_operand (expressionS *operand_array, + unsigned source, + unsigned destination) { - char *p = input_line_pointer; - int code_symbol_fix = 0; + expressionS cpy_operand; + expressionS *src_operand; + expressionS *dst_operand; + size_t size; - for (; ! is_end_of_line[(unsigned char) *p]; p++) - if (*p == '@' && !strncmp (p, "@h30", 4)) - { - code_symbol_fix = 1; - strcpy (p, "; "); - } - expression_and_evaluate (exp); - if (code_symbol_fix) - { - arc_code_symbol (exp); - input_line_pointer = p; - } - return BFD_RELOC_NONE; + if (source == destination) + return; + + src_operand = &operand_array[source]; + dst_operand = &operand_array[destination]; + size = sizeof (expressionS); + + /* Make copy of operand to swap with and swap. */ + memcpy (&cpy_operand, dst_operand, size); + memcpy (dst_operand, src_operand, size); + memcpy (src_operand, &cpy_operand, size); } -/* Record a fixup for a cons expression. */ +/* Check if *op matches *tok type. + Returns FALSE if they don't match, TRUE if they match. */ -void -arc_cons_fix_new (fragS *frag, - int where, - int nbytes, - expressionS *exp, - bfd_reloc_code_real_type r ATTRIBUTE_UNUSED) +static bfd_boolean +pseudo_operand_match (const expressionS *tok, + const struct arc_operand_operation *op) { - if (nbytes == 4) - { - int reloc_type; - expressionS exptmp; + offsetT min, max, val; + bfd_boolean ret; + const struct arc_operand *operand_real = &arc_operands[op->operand_idx]; - /* This may be a special ARC reloc (eg: %st()). */ - reloc_type = get_arc_exp_reloc_type (1, BFD_RELOC_32, exp, &exptmp); - fix_new_exp (frag, where, nbytes, &exptmp, 0, - (enum bfd_reloc_code_real) reloc_type); - } - else + ret = FALSE; + switch (tok->X_op) { - fix_new_exp (frag, where, nbytes, exp, 0, - nbytes == 2 ? BFD_RELOC_16 - : nbytes == 8 ? BFD_RELOC_64 - : BFD_RELOC_32); + case O_constant: + if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM)) + ret = 1; + else if (!(operand_real->flags & ARC_OPERAND_IR)) + { + val = tok->X_add_number; + if (operand_real->flags & ARC_OPERAND_SIGNED) + { + max = (1 << (operand_real->bits - 1)) - 1; + min = -(1 << (operand_real->bits - 1)); + } + else + { + max = (1 << operand_real->bits) - 1; + min = 0; + } + if (min <= val && val <= max) + ret = TRUE; + } + break; + + case O_symbol: + /* Handle all symbols as long immediates or signed 9. */ + if (operand_real->flags & ARC_OPERAND_LIMM || + ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9)) + ret = TRUE; + break; + + case O_register: + if (operand_real->flags & ARC_OPERAND_IR) + ret = TRUE; + break; + + case O_bracket: + if (operand_real->flags & ARC_OPERAND_BRAKET) + ret = TRUE; + break; + + default: + /* Unknown. */ + break; } + return ret; } - -/* Functions concerning relocs. */ -/* The location from which a PC relative jump should be calculated, - given a PC relative reloc. */ +/* Find pseudo instruction in array. */ -long -md_pcrel_from (fixS *fixP) +static const struct arc_pseudo_insn * +find_pseudo_insn (const char *opname, + int ntok, + const expressionS *tok) { - /* Return the address of the delay slot. */ - return fixP->fx_frag->fr_address + fixP->fx_where + fixP->fx_size; + const struct arc_pseudo_insn *pseudo_insn = NULL; + const struct arc_operand_operation *op; + unsigned int i; + int j; + + for (i = 0; i < arc_num_pseudo_insn; ++i) + { + pseudo_insn = &arc_pseudo_insns[i]; + if (strcmp (pseudo_insn->mnemonic_p, opname) == 0) + { + op = pseudo_insn->operand; + for (j = 0; j < ntok; ++j) + if (!pseudo_operand_match (&tok[j], &op[j])) + break; + + /* Found the right instruction. */ + if (j == ntok) + return pseudo_insn; + } + } + return NULL; } -/* Apply a fixup to the object code. This is called for all the - fixups we generated by the call to fix_new_exp, above. In the call - above we used a reloc code which was the largest legal reloc code - plus the operand index. Here we undo that to recover the operand - index. At this point all symbol values should be fully resolved, - and we attempt to completely resolve the reloc. If we can not do - that, we determine the correct reloc code and put it back in the fixup. */ +/* Assumes the expressionS *tok is of sufficient size. */ -void -md_apply_fix (fixS *fixP, valueT * valP, segT seg) +static const struct arc_opcode * +find_special_case_pseudo (const char *opname, + int *ntok, + expressionS *tok, + int *nflgs, + struct arc_flags *pflags) { - valueT value = * valP; + const struct arc_pseudo_insn *pseudo_insn = NULL; + const struct arc_operand_operation *operand_pseudo; + const struct arc_operand *operand_real; + unsigned i; + char construct_operand[MAX_CONSTR_STR]; - if (fixP->fx_addsy == (symbolS *) NULL) - fixP->fx_done = 1; + /* Find whether opname is in pseudo instruction array. */ + pseudo_insn = find_pseudo_insn (opname, *ntok, tok); - else if (fixP->fx_pcrel) - { - /* Hack around bfd_install_relocation brain damage. */ - if (S_GET_SEGMENT (fixP->fx_addsy) != seg) - value += md_pcrel_from (fixP); - } + if (pseudo_insn == NULL) + return NULL; - /* We can't actually support subtracting a symbol. */ - if (fixP->fx_subsy != NULL) - as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); + /* Handle flag, Limited to one flag at the moment. */ + if (pseudo_insn->flag_r != NULL) + *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs], + MAX_INSN_FLGS - *nflgs); - if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) + /* Handle operand operations. */ + for (i = 0; i < pseudo_insn->operand_cnt; ++i) { - int opindex; - const struct arc_operand *operand; - char *where; - arc_insn insn; + operand_pseudo = &pseudo_insn->operand[i]; + operand_real = &arc_operands[operand_pseudo->operand_idx]; - opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; - - operand = &arc_operands[opindex]; + if (operand_real->flags & ARC_OPERAND_BRAKET && + !operand_pseudo->needs_insert) + continue; - /* Fetch the instruction, insert the fully resolved operand - value, and stuff the instruction back again. */ - where = fixP->fx_frag->fr_literal + fixP->fx_where; - if (target_big_endian) - insn = bfd_getb32 ((unsigned char *) where); - else - insn = bfd_getl32 ((unsigned char *) where); - insn = arc_insert_operand (insn, operand, -1, NULL, (offsetT) value, - fixP->fx_file, fixP->fx_line); - if (target_big_endian) - bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); - else - bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); + /* Has to be inserted (i.e. this token does not exist yet). */ + if (operand_pseudo->needs_insert) + { + if (operand_real->flags & ARC_OPERAND_BRAKET) + { + tok[i].X_op = O_bracket; + ++(*ntok); + continue; + } - if (fixP->fx_done) - /* Nothing else to do here. */ - return; + /* Check if operand is a register or constant and handle it + by type. */ + if (operand_real->flags & ARC_OPERAND_IR) + snprintf (construct_operand, MAX_CONSTR_STR, "r%d", + operand_pseudo->count); + else + snprintf (construct_operand, MAX_CONSTR_STR, "%d", + operand_pseudo->count); - /* Determine a BFD reloc value based on the operand information. - We are only prepared to turn a few of the operands into relocs. - !!! Note that we can't handle limm values here. Since we're using - implicit addends the addend must be inserted into the instruction, - however, the opcode insertion routines currently do nothing with - limm values. */ - if (operand->fmt == 'B') - { - gas_assert ((operand->flags & ARC_OPERAND_RELATIVE_BRANCH) != 0 - && operand->bits == 20 - && operand->shift == 7); - fixP->fx_r_type = BFD_RELOC_ARC_B22_PCREL; - } - else if (operand->fmt == 'J') - { - gas_assert ((operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH) != 0 - && operand->bits == 24 - && operand->shift == 32); - fixP->fx_r_type = BFD_RELOC_ARC_B26; - } - else if (operand->fmt == 'L') - { - gas_assert ((operand->flags & ARC_OPERAND_LIMM) != 0 - && operand->bits == 32 - && operand->shift == 32); - fixP->fx_r_type = BFD_RELOC_32; + tokenize_arguments (construct_operand, &tok[i], 1); + ++(*ntok); } - else + + else if (operand_pseudo->count) { - as_bad_where (fixP->fx_file, fixP->fx_line, - _("unresolved expression that must be resolved")); - fixP->fx_done = 1; - return; + /* Operand number has to be adjusted accordingly (by operand + type). */ + switch (tok[i].X_op) + { + case O_constant: + tok[i].X_add_number += operand_pseudo->count; + break; + + case O_symbol: + break; + + default: + /* Ignored. */ + break; + } } } - else + + /* Swap operands if necessary. Only supports one swap at the + moment. */ + for (i = 0; i < pseudo_insn->operand_cnt; ++i) { - switch (fixP->fx_r_type) + operand_pseudo = &pseudo_insn->operand[i]; + + if (operand_pseudo->swap_operand_idx == i) + continue; + + swap_operand (tok, i, operand_pseudo->swap_operand_idx); + + /* Prevent a swap back later by breaking out. */ + break; + } + + return (const struct arc_opcode *) + hash_find (arc_opcode_hash, pseudo_insn->mnemonic_r); +} + +static const struct arc_opcode * +find_special_case_flag (const char *opname, + int *nflgs, + struct arc_flags *pflags) +{ + unsigned int i; + const char *flagnm; + unsigned flag_idx, flag_arr_idx; + size_t flaglen, oplen; + const struct arc_flag_special *arc_flag_special_opcode; + const struct arc_opcode *opcode; + + /* Search for special case instruction. */ + for (i = 0; i < arc_num_flag_special; i++) + { + arc_flag_special_opcode = &arc_flag_special_cases[i]; + oplen = strlen (arc_flag_special_opcode->name); + + if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0) + continue; + + /* Found a potential special case instruction, now test for + flags. */ + for (flag_arr_idx = 0;; ++flag_arr_idx) { - case BFD_RELOC_8: - md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, - value, 1); - break; - case BFD_RELOC_16: - md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, - value, 2); - break; - case BFD_RELOC_32: - md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, - value, 4); - break; - case BFD_RELOC_ARC_B26: - /* If !fixP->fx_done then `value' is an implicit addend. - We must shift it right by 2 in this case as well because the - linker performs the relocation and then adds this in (as opposed - to adding this in and then shifting right by 2). */ - value >>= 2; - md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, - value, 4); - break; - default: - abort (); + flag_idx = arc_flag_special_opcode->flags[flag_arr_idx]; + if (flag_idx == 0) + break; /* End of array, nothing found. */ + + flagnm = arc_flag_operands[flag_idx].name; + flaglen = strlen (flagnm); + if (strcmp (opname + oplen, flagnm) == 0) + { + opcode = (const struct arc_opcode *) + hash_find (arc_opcode_hash, + arc_flag_special_opcode->name); + + if (*nflgs + 1 > MAX_INSN_FLGS) + break; + memcpy (pflags[*nflgs].name, flagnm, flaglen); + pflags[*nflgs].name[flaglen] = '\0'; + (*nflgs)++; + return opcode; + } } } + return NULL; } -/* Translate internal representation of relocation info to BFD target - format. */ +/* Check whether a symbol involves a register. */ -arelent * -tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, - fixS *fixP) +static int +contains_register (symbolS *sym) { - arelent *reloc; + if (sym) + { + expressionS *ex = symbol_get_value_expression (sym); + return ((O_register == ex->X_op) + && !contains_register (ex->X_add_symbol) + && !contains_register (ex->X_op_symbol)); + } + else + return 0; +} - reloc = (arelent *) xmalloc (sizeof (arelent)); - reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); +/* Returns the register number within a symbol. */ - *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); - reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; - reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); - if (reloc->howto == (reloc_howto_type *) NULL) - { - as_bad_where (fixP->fx_file, fixP->fx_line, - _("internal error: can't export reloc type %d (`%s')"), - fixP->fx_r_type, - bfd_get_reloc_code_name (fixP->fx_r_type)); - return NULL; - } +static int +get_register (symbolS *sym) +{ + if (!contains_register (sym)) + return -1; - gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); + expressionS *ex = symbol_get_value_expression (sym); + return regno (ex->X_add_number); +} - /* Set addend to account for PC being advanced one insn before the - target address is computed. */ +/* Allocates a tok entry. */ - reloc->addend = (fixP->fx_pcrel ? -4 : 0); +static int +allocate_tok (expressionS *tok, int ntok, int cidx) +{ + if (ntok > MAX_INSN_ARGS - 2) + return 0; /* No space left. */ - return reloc; + if (cidx > ntok) + return 0; /* Incorect args. */ + + memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok)); + + if (cidx == ntok) + return 1; /* Success. */ + return allocate_tok (tok, ntok - 1, cidx); } -const pseudo_typeS md_pseudo_table[] = +/* Return true if a RELOC is generic. A generic reloc is PC-rel of a + simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */ + +static bfd_boolean +generic_reloc_p (extended_bfd_reloc_code_real_type reloc) { - { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ - { "comm", arc_common, 0 }, - { "common", arc_common, 0 }, - { "lcomm", arc_common, 1 }, - { "lcommon", arc_common, 1 }, - { "2byte", cons, 2 }, - { "half", cons, 2 }, - { "short", cons, 2 }, - { "3byte", cons, 3 }, - { "4byte", cons, 4 }, - { "word", cons, 4 }, - { "option", arc_option, 0 }, - { "cpu", arc_option, 0 }, - { "block", s_space, 0 }, - { "extcondcode", arc_extoper, 0 }, - { "extcoreregister", arc_extoper, 1 }, - { "extauxregister", arc_extoper, 2 }, - { "extinstruction", arc_extinst, 0 }, - { NULL, 0, 0 }, -}; + if (!reloc) + return FALSE; -/* This routine is called for each instruction to be assembled. */ + switch (reloc) + { + case BFD_RELOC_ARC_SDA_LDST: + case BFD_RELOC_ARC_SDA_LDST1: + case BFD_RELOC_ARC_SDA_LDST2: + case BFD_RELOC_ARC_SDA16_LD: + case BFD_RELOC_ARC_SDA16_LD1: + case BFD_RELOC_ARC_SDA16_LD2: + case BFD_RELOC_ARC_SDA16_ST2: + case BFD_RELOC_ARC_SDA32_ME: + return FALSE; + default: + break; + } + return TRUE; +} -void -md_assemble (char *str) +/* Search forward through all variants of an opcode looking for a + syntax match. */ + +static const struct arc_opcode * +find_opcode_match (const struct arc_opcode *first_opcode, + expressionS *tok, + int *pntok, + struct arc_flags *first_pflag, + int nflgs, + int *pcpumatch) { - const struct arc_opcode *opcode; - const struct arc_opcode *std_opcode; - struct arc_opcode *ext_opcode; - char *start; - const char *last_errmsg = 0; - arc_insn insn; - static int init_tables_p = 0; - - /* Opcode table initialization is deferred until here because we have to - wait for a possible .option command. */ - if (!init_tables_p) + const struct arc_opcode *opcode = first_opcode; + int ntok = *pntok; + int got_cpu_match = 0; + expressionS bktok[MAX_INSN_ARGS]; + int bkntok; + expressionS emptyE; + + memset (&emptyE, 0, sizeof (emptyE)); + memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok)); + bkntok = ntok; + + do { - init_opcode_tables (arc_mach_type); - init_tables_p = 1; - } + const unsigned char *opidx; + const unsigned char *flgidx; + int tokidx = 0; + const expressionS *t = &emptyE; - /* Skip leading white space. */ - while (ISSPACE (*str)) - str++; + pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ", + frag_now->fr_file, frag_now->fr_line, opcode->opcode); - /* The instructions are stored in lists hashed by the first letter (though - we needn't care how they're hashed). Get the first in the list. */ + /* Don't match opcodes that don't exist on this + architecture. */ + if (!(opcode->cpu & arc_target)) + goto match_failed; - ext_opcode = arc_ext_opcodes; - std_opcode = arc_opcode_lookup_asm (str); + if (is_code_density_p (opcode) && !(arc_features & ARC_CD)) + goto match_failed; - /* Keep looking until we find a match. */ - start = str; - for (opcode = (ext_opcode ? ext_opcode : std_opcode); - opcode != NULL; - opcode = (ARC_OPCODE_NEXT_ASM (opcode) - ? ARC_OPCODE_NEXT_ASM (opcode) - : (ext_opcode ? ext_opcode = NULL, std_opcode : NULL))) - { - int past_opcode_p, fc, num_suffixes; - int fix_up_at = 0; - char *syn; - struct arc_fixup fixups[MAX_FIXUPS]; - /* Used as a sanity check. If we need a limm reloc, make sure we ask - for an extra 4 bytes from frag_more. */ - int limm_reloc_p; - int ext_suffix_p; - const struct arc_operand_value *insn_suffixes[MAX_SUFFIXES]; - - /* Is this opcode supported by the selected cpu? */ - if (! arc_opcode_supported (opcode)) - continue; + got_cpu_match = 1; + pr_debug ("cpu "); - /* Scan the syntax string. If it doesn't match, try the next one. */ - arc_opcode_init_insert (); - insn = opcode->value; - fc = 0; - past_opcode_p = 0; - num_suffixes = 0; - limm_reloc_p = 0; - ext_suffix_p = 0; - - /* We don't check for (*str != '\0') here because we want to parse - any trailing fake arguments in the syntax string. */ - for (str = start, syn = opcode->syntax; *syn != '\0';) + /* Check the operands. */ + for (opidx = opcode->operands; *opidx; ++opidx) { - int mods; - const struct arc_operand *operand; + const struct arc_operand *operand = &arc_operands[*opidx]; - /* Non operand chars must match exactly. */ - if (*syn != '%' || *++syn == '%') + /* Only take input from real operands. */ + if ((operand->flags & ARC_OPERAND_FAKE) + && !(operand->flags & ARC_OPERAND_BRAKET)) + continue; + + /* When we expect input, make sure we have it. */ + if (tokidx >= ntok) + goto match_failed; + + /* Match operand type with expression type. */ + switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK) { - if (*str == *syn) + case ARC_OPERAND_IR: + /* Check to be a register. */ + if ((tok[tokidx].X_op != O_register + || !is_ir_num (tok[tokidx].X_add_number)) + && !(operand->flags & ARC_OPERAND_IGNORE)) + goto match_failed; + + /* If expect duplicate, make sure it is duplicate. */ + if (operand->flags & ARC_OPERAND_DUPLICATE) { - if (*syn == ' ') - past_opcode_p = 1; - ++syn; - ++str; + /* Check for duplicate. */ + if (t->X_op != O_register + || !is_ir_num (t->X_add_number) + || (regno (t->X_add_number) != + regno (tok[tokidx].X_add_number))) + goto match_failed; } - else - break; - continue; - } - /* We have an operand. Pick out any modifiers. */ - mods = 0; - while (ARC_MOD_P (arc_operands[arc_operand_map[(int) *syn]].flags)) - { - mods |= arc_operands[arc_operand_map[(int) *syn]].flags & ARC_MOD_BITS; - ++syn; - } - operand = arc_operands + arc_operand_map[(int) *syn]; - if (operand->fmt == 0) - as_fatal (_("unknown syntax format character `%c'"), *syn); - - if (operand->flags & ARC_OPERAND_FAKE) - { - const char *errmsg = NULL; + /* Special handling? */ if (operand->insert) { - insn = (*operand->insert) (insn, operand, mods, NULL, 0, &errmsg); - if (errmsg != (const char *) NULL) + const char *errmsg = NULL; + (*operand->insert)(0, + regno (tok[tokidx].X_add_number), + &errmsg); + if (errmsg) { - last_errmsg = errmsg; - if (operand->flags & ARC_OPERAND_ERROR) + if (operand->flags & ARC_OPERAND_IGNORE) { - as_bad ("%s", errmsg); - return; + /* Missing argument, create one. */ + if (!allocate_tok (tok, ntok - 1, tokidx)) + goto match_failed; + + tok[tokidx].X_op = O_absent; + ++ntok; } - else if (operand->flags & ARC_OPERAND_WARN) - as_warn ("%s", errmsg); - break; + else + goto match_failed; } - if (limm_reloc_p - && (operand->flags && operand->flags & ARC_OPERAND_LIMM) - && (operand->flags & - (ARC_OPERAND_ABSOLUTE_BRANCH | ARC_OPERAND_ADDRESS))) - { - fixups[fix_up_at].opindex = arc_operand_map[operand->fmt]; - } - } - ++syn; - } - /* Are we finished with suffixes? */ - else if (!past_opcode_p) - { - int found; - char c; - char *s, *t; - const struct arc_operand_value *suf, *suffix_end; - const struct arc_operand_value *suffix = NULL; - - if (!(operand->flags & ARC_OPERAND_SUFFIX)) - abort (); - - /* If we're at a space in the input string, we want to skip the - remaining suffixes. There may be some fake ones though, so - just go on to try the next one. */ - if (*str == ' ') - { - ++syn; - continue; } - s = str; - if (mods & ARC_MOD_DOT) - { - if (*s != '.') - break; - ++s; - } - else - { - /* This can happen in "b.nd foo" and we're currently looking - for "%q" (ie: a condition code suffix). */ - if (*s == '.') - { - ++syn; - continue; - } - } + t = &tok[tokidx]; + break; - /* Pick the suffix out and look it up via the hash table. */ - for (t = s; *t && ISALNUM (*t); ++t) - continue; - c = *t; - *t = '\0'; - if ((suf = get_ext_suffix (s))) - ext_suffix_p = 1; - else - suf = (const struct arc_operand_value *) - hash_find (arc_suffix_hash, s); - if (!suf) + case ARC_OPERAND_BRAKET: + /* Check if bracket is also in opcode table as + operand. */ + if (tok[tokidx].X_op != O_bracket) + goto match_failed; + break; + + case ARC_OPERAND_LIMM: + case ARC_OPERAND_SIGNED: + case ARC_OPERAND_UNSIGNED: + switch (tok[tokidx].X_op) { - /* This can happen in "blle foo" and we're currently using - the template "b%q%.n %j". The "bl" insn occurs later in - the table so "lle" isn't an illegal suffix. */ - *t = c; + case O_illegal: + case O_absent: + case O_register: + goto match_failed; + + case O_bracket: + /* Got an (too) early bracket, check if it is an + ignored operand. N.B. This procedure works only + when bracket is the last operand! */ + if (!(operand->flags & ARC_OPERAND_IGNORE)) + goto match_failed; + /* Insert the missing operand. */ + if (!allocate_tok (tok, ntok - 1, tokidx)) + goto match_failed; + + tok[tokidx].X_op = O_absent; + ++ntok; break; - } - /* Is it the right type? Note that the same character is used - several times, so we have to examine all of them. This is - relatively efficient as equivalent entries are kept - together. If it's not the right type, don't increment `str' - so we try the next one in the series. */ - found = 0; - if (ext_suffix_p && arc_operands[suf->type].fmt == *syn) - { - /* Insert the suffix's value into the insn. */ - *t = c; - if (operand->insert) - insn = (*operand->insert) (insn, operand, - mods, NULL, suf->value, - NULL); - else - insn |= suf->value << operand->shift; - suffix = suf; - str = t; - found = 1; - } - else - { - *t = c; - suffix_end = arc_suffixes + arc_suffixes_count; - for (suffix = suf; - suffix < suffix_end && strcmp (suffix->name, suf->name) == 0; - ++suffix) + case O_constant: + /* Check the range. */ + if (operand->bits != 32 + && !(operand->flags & ARC_OPERAND_NCHK)) { - if (arc_operands[suffix->type].fmt == *syn) + offsetT min, max, val; + val = tok[tokidx].X_add_number; + + if (operand->flags & ARC_OPERAND_SIGNED) { - /* Insert the suffix's value into the insn. */ - if (operand->insert) - insn = (*operand->insert) (insn, operand, - mods, NULL, suffix->value, - NULL); - else - insn |= suffix->value << operand->shift; - - str = t; - found = 1; - break; + max = (1 << (operand->bits - 1)) - 1; + min = -(1 << (operand->bits - 1)); + } + else + { + max = (1 << operand->bits) - 1; + min = 0; } - } - } - ++syn; - if (!found) - /* Wrong type. Just go on to try next insn entry. */ - ; - else - { - if (num_suffixes == MAX_SUFFIXES) - as_bad (_("too many suffixes")); - else - insn_suffixes[num_suffixes++] = suffix; - } - } - else - /* This is either a register or an expression of some kind. */ - { - char *hold; - const struct arc_operand_value *reg = NULL; - long value = 0; - expressionS exp; - - if (operand->flags & ARC_OPERAND_SUFFIX) - abort (); - - /* Is there anything left to parse? - We don't check for this at the top because we want to parse - any trailing fake arguments in the syntax string. */ - if (is_end_of_line[(unsigned char) *str]) - break; - /* Parse the operand. */ - hold = input_line_pointer; - input_line_pointer = str; - expression (&exp); - str = input_line_pointer; - input_line_pointer = hold; - - if (exp.X_op == O_illegal) - as_bad (_("illegal operand")); - else if (exp.X_op == O_absent) - as_bad (_("missing operand")); - else if (exp.X_op == O_constant) - value = exp.X_add_number; - else if (exp.X_op == O_register) - reg = (struct arc_operand_value *) exp.X_add_number; -#define IS_REG_DEST_OPERAND(o) ((o) == 'a') - else if (IS_REG_DEST_OPERAND (*syn)) - as_bad (_("symbol as destination register")); - else - { - if (!strncmp (str, "@h30", 4)) - { - arc_code_symbol (&exp); - str += 4; + if (val < min || val > max) + goto match_failed; + + /* Check alignmets. */ + if ((operand->flags & ARC_OPERAND_ALIGNED32) + && (val & 0x03)) + goto match_failed; + + if ((operand->flags & ARC_OPERAND_ALIGNED16) + && (val & 0x01)) + goto match_failed; } - /* We need to generate a fixup for this expression. */ - if (fc >= MAX_FIXUPS) - as_fatal (_("too many fixups")); - fixups[fc].exp = exp; - /* We don't support shimm relocs. break here to force - the assembler to output a limm. */ -#define IS_REG_SHIMM_OFFSET(o) ((o) == 'd') - if (IS_REG_SHIMM_OFFSET (*syn)) - break; - /* If this is a register constant (IE: one whose - register value gets stored as 61-63) then this - must be a limm. */ - /* ??? This bit could use some cleaning up. - Referencing the format chars like this goes - against style. */ - if (IS_SYMBOL_OPERAND (*syn)) + else if (operand->flags & ARC_OPERAND_NCHK) { - const char *junk; - limm_reloc_p = 1; - /* Save this, we don't yet know what reloc to use. */ - fix_up_at = fc; - /* Tell insert_reg we need a limm. This is - needed because the value at this point is - zero, a shimm. */ - /* ??? We need a cleaner interface than this. */ - (*arc_operands[arc_operand_map['Q']].insert) - (insn, operand, mods, reg, 0L, &junk); + if (operand->insert) + { + const char *errmsg = NULL; + (*operand->insert)(0, + tok[tokidx].X_add_number, + &errmsg); + if (errmsg) + goto match_failed; + } + else + goto match_failed; } - else - fixups[fc].opindex = arc_operand_map[(int) *syn]; - ++fc; - value = 0; - } + break; - /* Insert the register or expression into the instruction. */ - if (operand->insert) - { - const char *errmsg = NULL; - insn = (*operand->insert) (insn, operand, mods, - reg, (long) value, &errmsg); - if (errmsg != (const char *) NULL) + case O_subtract: + /* Check if it is register range. */ + if ((tok[tokidx].X_add_number == 0) + && contains_register (tok[tokidx].X_add_symbol) + && contains_register (tok[tokidx].X_op_symbol)) { - last_errmsg = errmsg; - if (operand->flags & ARC_OPERAND_ERROR) + int regs; + + regs = get_register (tok[tokidx].X_add_symbol); + regs <<= 16; + regs |= get_register (tok[tokidx].X_op_symbol); + if (operand->insert) { - as_bad ("%s", errmsg); - return; + const char *errmsg = NULL; + (*operand->insert)(0, + regs, + &errmsg); + if (errmsg) + goto match_failed; } - else if (operand->flags & ARC_OPERAND_WARN) - as_warn ("%s", errmsg); + else + goto match_failed; break; } + default: + if (operand->default_reloc == 0) + goto match_failed; /* The operand needs relocation. */ + + /* Relocs requiring long immediate. FIXME! make it + generic and move it to a function. */ + switch (tok[tokidx].X_md) + { + case O_gotoff: + case O_gotpc: + case O_pcl: + case O_tpoff: + case O_dtpoff: + case O_tlsgd: + case O_tlsie: + if (!(operand->flags & ARC_OPERAND_LIMM)) + goto match_failed; + case O_absent: + if (!generic_reloc_p (operand->default_reloc)) + goto match_failed; + default: + break; + } + break; } - else - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + /* If expect duplicate, make sure it is duplicate. */ + if (operand->flags & ARC_OPERAND_DUPLICATE) + { + if (t->X_op == O_illegal + || t->X_op == O_absent + || t->X_op == O_register + || (t->X_add_number != tok[tokidx].X_add_number)) + goto match_failed; + } + t = &tok[tokidx]; + break; + + default: + /* Everything else should have been fake. */ + abort (); + } + + ++tokidx; + } + pr_debug ("opr "); + + /* Check the flags. Iterate over the valid flag classes. */ + int lnflg = nflgs; + + for (flgidx = opcode->flags; *flgidx && lnflg; ++flgidx) + { + /* Get a valid flag class. */ + const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; + const unsigned *flgopridx; + + for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) + { + const struct arc_flag_operand *flg_operand; + struct arc_flags *pflag = first_pflag; + int i; - ++syn; + flg_operand = &arc_flag_operands[*flgopridx]; + for (i = 0; i < nflgs; i++, pflag++) + { + /* Match against the parsed flags. */ + if (!strcmp (flg_operand->name, pflag->name)) + { + /*TODO: Check if it is duplicated. */ + pflag->code = *flgopridx; + lnflg--; + break; /* goto next flag class and parsed flag. */ + } + } } } + /* Did I check all the parsed flags? */ + if (lnflg) + goto match_failed; - /* If we're at the end of the syntax string, we're done. */ - /* FIXME: try to move this to a separate function. */ - if (*syn == '\0') + pr_debug ("flg"); + /* Possible match -- did we use all of our input? */ + if (tokidx == ntok) { - int i; - char *f; - long limm, limm_p; + *pntok = ntok; + pr_debug ("\n"); + return opcode; + } - /* For the moment we assume a valid `str' can only contain blanks - now. IE: We needn't try again with a longer version of the - insn and it is assumed that longer versions of insns appear - before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + match_failed:; + pr_debug ("\n"); + /* Restore the original parameters. */ + memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok)); + ntok = bkntok; + } + while (++opcode - arc_opcodes < (int) arc_num_opcodes + && !strcmp (opcode->name, first_opcode->name)); - while (ISSPACE (*str)) - ++str; + if (*pcpumatch) + *pcpumatch = got_cpu_match; - if (!is_end_of_line[(unsigned char) *str]) - as_bad (_("junk at end of line: `%s'"), str); + return NULL; +} - /* Is there a limm value? */ - limm_p = arc_opcode_limm_p (&limm); +/* Find the proper relocation for the given opcode. */ - /* Perform various error and warning tests. */ +static extended_bfd_reloc_code_real_type +find_reloc (const char *name, + const char *opcodename, + const struct arc_flags *pflags, + int nflg, + extended_bfd_reloc_code_real_type reloc) +{ + unsigned int i; + int j; + bfd_boolean found_flag; + extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED; - { - static int in_delay_slot_p = 0; - static int prev_insn_needs_cc_nop_p = 0; - /* delay slot type seen */ - int delay_slot_type = ARC_DELAY_NONE; - /* conditional execution flag seen */ - int conditional = 0; - /* 1 if condition codes are being set */ - int cc_set_p = 0; - /* 1 if conditional branch, including `b' "branch always" */ - int cond_branch_p = opcode->flags & ARC_OPCODE_COND_BRANCH; - - for (i = 0; i < num_suffixes; ++i) + for (i = 0; i < arc_num_equiv_tab; i++) + { + const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i]; + + /* Find the entry. */ + if (strcmp (name, r->name)) + continue; + if (r->mnemonic && (strcmp (r->mnemonic, opcodename))) + continue; + if (r->flagcode) + { + if (!nflg) + continue; + found_flag = FALSE; + for (j = 0; j < nflg; j++) + if (pflags[i].code == r->flagcode) { - switch (arc_operands[insn_suffixes[i]->type].fmt) - { - case 'n': - delay_slot_type = insn_suffixes[i]->value; - break; - case 'q': - conditional = insn_suffixes[i]->value; - break; - case 'f': - cc_set_p = 1; - break; - } + found_flag = TRUE; + break; } + if (!found_flag) + continue; + } - /* Putting an insn with a limm value in a delay slot is supposed to - be legal, but let's warn the user anyway. Ditto for 8 byte - jumps with delay slots. */ - if (in_delay_slot_p && limm_p) - as_warn (_("8 byte instruction in delay slot")); - if (delay_slot_type != ARC_DELAY_NONE - && limm_p && arc_insn_not_jl (insn)) /* except for jl addr */ - as_warn (_("8 byte jump instruction with delay slot")); - in_delay_slot_p = (delay_slot_type != ARC_DELAY_NONE) && !limm_p; - - /* Warn when a conditional branch immediately follows a set of - the condition codes. Note that this needn't be done if the - insn that sets the condition codes uses a limm. */ - if (cond_branch_p && conditional != 0 /* 0 = "always" */ - && prev_insn_needs_cc_nop_p && arc_mach_type == bfd_mach_arc_5) - as_warn (_("conditional branch follows set of flags")); - prev_insn_needs_cc_nop_p = - /* FIXME: ??? not required: - (delay_slot_type != ARC_DELAY_NONE) && */ - cc_set_p && !limm_p; - } + if (reloc != r->oldreloc) + continue; + /* Found it. */ + ret = r->newreloc; + break; + } + + if (ret == BFD_RELOC_UNUSED) + as_bad (_("Unable to find %s relocation for instruction %s"), + name, opcodename); + return ret; +} - /* Write out the instruction. - It is important to fetch enough space in one call to `frag_more'. - We use (f - frag_now->fr_literal) to compute where we are and we - don't want frag_now to change between calls. */ - if (limm_p) +/* Turn an opcode description and a set of arguments into + an instruction and a fixup. */ + +static void +assemble_insn (const struct arc_opcode *opcode, + const expressionS *tok, + int ntok, + const struct arc_flags *pflags, + int nflg, + struct arc_insn *insn) +{ + const expressionS *reloc_exp = NULL; + unsigned image; + const unsigned char *argidx; + int i; + int tokidx = 0; + unsigned char pcrel = 0; + bfd_boolean needGOTSymbol; + bfd_boolean has_delay_slot = FALSE; + extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; + + memset (insn, 0, sizeof (*insn)); + image = opcode->opcode; + + pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n", + frag_now->fr_file, frag_now->fr_line, opcode->name, + opcode->opcode); + + /* Handle operands. */ + for (argidx = opcode->operands; *argidx; ++argidx) + { + const struct arc_operand *operand = &arc_operands[*argidx]; + const expressionS *t = (const expressionS *) 0; + + if ((operand->flags & ARC_OPERAND_FAKE) + && !(operand->flags & ARC_OPERAND_BRAKET)) + continue; + + if (operand->flags & ARC_OPERAND_DUPLICATE) + { + /* Duplicate operand, already inserted. */ + tokidx ++; + continue; + } + + if (tokidx >= ntok) + { + abort (); + } + else + t = &tok[tokidx++]; + + /* Regardless if we have a reloc or not mark the instruction + limm if it is the case. */ + if (operand->flags & ARC_OPERAND_LIMM) + insn->has_limm = TRUE; + + switch (t->X_op) + { + case O_register: + image = insert_operand (image, operand, regno (t->X_add_number), + NULL, 0); + break; + + case O_constant: + image = insert_operand (image, operand, t->X_add_number, NULL, 0); + reloc_exp = t; + if (operand->flags & ARC_OPERAND_LIMM) + insn->limm = t->X_add_number; + break; + + case O_bracket: + /* Ignore brackets. */ + break; + + case O_absent: + gas_assert (operand->flags & ARC_OPERAND_IGNORE); + break; + + case O_subtract: + /* Maybe register range. */ + if ((t->X_add_number == 0) + && contains_register (t->X_add_symbol) + && contains_register (t->X_op_symbol)) { - f = frag_more (8); - md_number_to_chars (f, insn, 4); - md_number_to_chars (f + 4, limm, 4); - dwarf2_emit_insn (8); + int regs; + + regs = get_register (t->X_add_symbol); + regs <<= 16; + regs |= get_register (t->X_op_symbol); + image = insert_operand (image, operand, regs, NULL, 0); + break; } - else if (limm_reloc_p) - /* We need a limm reloc, but the tables think we don't. */ - abort (); - else + + default: + /* This operand needs a relocation. */ + needGOTSymbol = FALSE; + + switch (t->X_md) { - f = frag_more (4); - md_number_to_chars (f, insn, 4); - dwarf2_emit_insn (4); + case O_plt: + needGOTSymbol = TRUE; + reloc = find_reloc ("plt", opcode->name, + pflags, nflg, + operand->default_reloc); + break; + + case O_gotoff: + case O_gotpc: + needGOTSymbol = TRUE; + reloc = ARC_RELOC_TABLE (t->X_md)->reloc; + break; + case O_pcl: + reloc = ARC_RELOC_TABLE (t->X_md)->reloc; + if (ARC_SHORT (opcode->mask)) + as_bad_where (frag_now->fr_file, frag_now->fr_line, + _("Unable to use @pcl relocation for insn %s"), + opcode->name); + break; + case O_sda: + reloc = find_reloc ("sda", opcode->name, + pflags, nflg, + operand->default_reloc); + break; + case O_tlsgd: + case O_tlsie: + needGOTSymbol = TRUE; + /* Fall-through. */ + + case O_tpoff: + case O_dtpoff: + reloc = ARC_RELOC_TABLE (t->X_md)->reloc; + break; + + case O_tpoff9: /*FIXME! Check for the conditionality of + the insn. */ + case O_dtpoff9: /*FIXME! Check for the conditionality of + the insn. */ + as_bad (_("TLS_*_S9 relocs are not supported yet")); + break; + + default: + /* Just consider the default relocation. */ + reloc = operand->default_reloc; + break; } - /* Create any fixups. */ - for (i = 0; i < fc; ++i) + if (needGOTSymbol && (GOT_symbol == NULL)) + GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); + + reloc_exp = t; + +#if 0 + if (reloc > 0) { - int op_type, reloc_type; - expressionS exptmp; - const struct arc_operand *operand; - - /* Create a fixup for this operand. - At this point we do not use a bfd_reloc_code_real_type for - operands residing in the insn, but instead just use the - operand index. This lets us easily handle fixups for any - operand type, although that is admittedly not a very exciting - feature. We pick a BFD reloc type in md_apply_fix. - - Limm values (4 byte immediate "constants") must be treated - normally because they're not part of the actual insn word - and thus the insertion routines don't handle them. */ - - if (arc_operands[fixups[i].opindex].flags & ARC_OPERAND_LIMM) - { - /* Modify the fixup addend as required by the cpu. */ - fixups[i].exp.X_add_number += arc_limm_fixup_adjust (insn); - op_type = fixups[i].opindex; - /* FIXME: can we add this data to the operand table? */ - if (op_type == arc_operand_map['L'] - || op_type == arc_operand_map['s'] - || op_type == arc_operand_map['o'] - || op_type == arc_operand_map['O']) - reloc_type = BFD_RELOC_32; - else if (op_type == arc_operand_map['J']) - reloc_type = BFD_RELOC_ARC_B26; - else - abort (); - reloc_type = get_arc_exp_reloc_type (1, reloc_type, - &fixups[i].exp, - &exptmp); - } - else + /* sanity checks. */ + reloc_howto_type *reloc_howto + = bfd_reloc_type_lookup (stdoutput, + (bfd_reloc_code_real_type) reloc); + unsigned reloc_bitsize = reloc_howto->bitsize; + if (reloc_howto->rightshift) + reloc_bitsize -= reloc_howto->rightshift; + if (reloc_bitsize != operand->bits) { - op_type = get_arc_exp_reloc_type (0, fixups[i].opindex, - &fixups[i].exp, &exptmp); - reloc_type = op_type + (int) BFD_RELOC_UNUSED; + as_bad (_("invalid relocation %s for field"), + bfd_get_reloc_code_name (reloc)); + return; } - operand = &arc_operands[op_type]; - fix_new_exp (frag_now, - ((f - frag_now->fr_literal) - + (operand->flags & ARC_OPERAND_LIMM ? 4 : 0)), 4, - &exptmp, - (operand->flags & ARC_OPERAND_RELATIVE_BRANCH) != 0, - (bfd_reloc_code_real_type) reloc_type); } - return; +#endif + if (insn->nfixups >= MAX_INSN_FIXUPS) + as_fatal (_("too many fixups")); + + struct arc_fixup *fixup; + fixup = &insn->fixups[insn->nfixups++]; + fixup->exp = *t; + fixup->reloc = reloc; + pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0; + fixup->pcrel = pcrel; + fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ? + TRUE : FALSE; + break; } } - if (NULL == last_errmsg) - as_bad (_("bad instruction `%s'"), start); + /* Handle flags. */ + for (i = 0; i < nflg; i++) + { + const struct arc_flag_operand *flg_operand = + &arc_flag_operands[pflags[i].code]; + + /* Check if the instruction has a delay slot. */ + if (!strcmp (flg_operand->name, "d")) + has_delay_slot = TRUE; + + /* There is an exceptional case when we cannot insert a flag + just as it is. The .T flag must be handled in relation with + the relative address. */ + if (!strcmp (flg_operand->name, "t") + || !strcmp (flg_operand->name, "nt")) + { + unsigned bitYoperand = 0; + /* FIXME! move selection bbit/brcc in arc-opc.c. */ + if (!strcmp (flg_operand->name, "t")) + if (!strcmp (opcode->name, "bbit0") + || !strcmp (opcode->name, "bbit1")) + bitYoperand = arc_NToperand; + else + bitYoperand = arc_Toperand; + else + if (!strcmp (opcode->name, "bbit0") + || !strcmp (opcode->name, "bbit1")) + bitYoperand = arc_Toperand; + else + bitYoperand = arc_NToperand; + + gas_assert (reloc_exp != NULL); + if (reloc_exp->X_op == O_constant) + { + /* Check if we have a constant and solved it + immediately. */ + offsetT val = reloc_exp->X_add_number; + image |= insert_operand (image, &arc_operands[bitYoperand], + val, NULL, 0); + } + else + { + struct arc_fixup *fixup; + + if (insn->nfixups >= MAX_INSN_FIXUPS) + as_fatal (_("too many fixups")); + + fixup = &insn->fixups[insn->nfixups++]; + fixup->exp = *reloc_exp; + fixup->reloc = -bitYoperand; + fixup->pcrel = pcrel; + fixup->islong = FALSE; + } + } + else + image |= (flg_operand->code & ((1 << flg_operand->bits) - 1)) + << flg_operand->shift; + } + + /* Short instruction? */ + insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE; + + insn->insn = image; + + /* Update last insn status. */ + arc_last_insns[1] = arc_last_insns[0]; + arc_last_insns[0].opcode = opcode; + arc_last_insns[0].has_limm = insn->has_limm; + arc_last_insns[0].has_delay_slot = has_delay_slot; + + /* Check if the current instruction is legally used. */ + if (arc_last_insns[1].has_delay_slot + && is_br_jmp_insn_p (arc_last_insns[0].opcode)) + as_bad_where (frag_now->fr_file, frag_now->fr_line, + _("A jump/branch instruction in delay slot.")); +} + +/* Actually output an instruction with its fixup. */ + +static void +emit_insn (struct arc_insn *insn) +{ + char *f; + int i; + + pr_debug ("Emit insn : 0x%x\n", insn->insn); + pr_debug ("\tShort : 0x%d\n", insn->short_insn); + pr_debug ("\tLong imm: 0x%lx\n", insn->limm); + + /* Write out the instruction. */ + if (insn->short_insn) + { + if (insn->has_limm) + { + f = frag_more (6); + md_number_to_chars (f, insn->insn, 2); + md_number_to_chars_midend (f + 2, insn->limm, 4); + dwarf2_emit_insn (6); + } + else + { + f = frag_more (2); + md_number_to_chars (f, insn->insn, 2); + dwarf2_emit_insn (2); + } + } else - as_bad ("%s", last_errmsg); + { + if (insn->has_limm) + { + f = frag_more (8); + md_number_to_chars_midend (f, insn->insn, 4); + md_number_to_chars_midend (f + 4, insn->limm, 4); + dwarf2_emit_insn (8); + } + else + { + f = frag_more (4); + md_number_to_chars_midend (f, insn->insn, 4); + dwarf2_emit_insn (4); + } + } + + /* Apply the fixups in order. */ + for (i = 0; i < insn->nfixups; i++) + { + struct arc_fixup *fixup = &insn->fixups[i]; + int size, pcrel, offset = 0; + + /*FIXME! the reloc size is wrong in the BFD file. When it will + be fixed please delete me. */ + size = (insn->short_insn && !fixup->islong) ? 2 : 4; + + if (fixup->islong) + offset = (insn->short_insn) ? 2 : 4; + + /* Some fixups are only used internally, thus no howto. */ + if ((int) fixup->reloc < 0) + { + /*FIXME! the reloc size is wrong in the BFD file. When it + will be fixed please enable me. + size = (insn->short_insn && !fixup->islong) ? 2 : 4; */ + pcrel = fixup->pcrel; + } + else + { + reloc_howto_type *reloc_howto = + bfd_reloc_type_lookup (stdoutput, + (bfd_reloc_code_real_type) fixup->reloc); + gas_assert (reloc_howto); + /*FIXME! the reloc size is wrong in the BFD file. When it + will be fixed please enable me. + size = bfd_get_reloc_size (reloc_howto); */ + pcrel = reloc_howto->pc_relative; + } + + pr_debug ("%s:%d: emit_insn: new %s fixup (PCrel:%s) of size %d @ offset %d\n", + frag_now->fr_file, frag_now->fr_line, + (fixup->reloc < 0) ? "Internal" : + bfd_get_reloc_code_name (fixup->reloc), + pcrel ? "Y" : "N", + size, offset); + fix_new_exp (frag_now, f - frag_now->fr_literal + offset, + size, &fixup->exp, pcrel, fixup->reloc); + + /* Check for ZOLs, and update symbol info if any. */ + if (LP_INSN (insn->insn)) + { + gas_assert (fixup->exp.X_add_symbol); + ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL); + } + } +} + +/* Insert an operand value into an instruction. */ + +static unsigned +insert_operand (unsigned insn, + const struct arc_operand *operand, + offsetT val, + char *file, + unsigned line) +{ + offsetT min = 0, max = 0; + + if (operand->bits != 32 + && !(operand->flags & ARC_OPERAND_NCHK) + && !(operand->flags & ARC_OPERAND_FAKE)) + { + if (operand->flags & ARC_OPERAND_SIGNED) + { + max = (1 << (operand->bits - 1)) - 1; + min = -(1 << (operand->bits - 1)); + } + else + { + max = (1 << operand->bits) - 1; + min = 0; + } + + if (val < min || val > max) + as_bad_value_out_of_range (_("operand"), + val, min, max, file, line); + } + + pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n", + min, val, max, insn); + + if ((operand->flags & ARC_OPERAND_ALIGNED32) + && (val & 0x03)) + as_bad_where (file, line, + _("Unaligned operand. Needs to be 32bit aligned")); + + if ((operand->flags & ARC_OPERAND_ALIGNED16) + && (val & 0x01)) + as_bad_where (file, line, + _("Unaligned operand. Needs to be 16bit aligned")); + + if (operand->insert) + { + const char *errmsg = NULL; + + insn = (*operand->insert) (insn, val, &errmsg); + if (errmsg) + as_warn_where (file, line, "%s", errmsg); + } + else + { + if (operand->flags & ARC_OPERAND_TRUNCATE) + { + if (operand->flags & ARC_OPERAND_ALIGNED32) + val >>= 2; + if (operand->flags & ARC_OPERAND_ALIGNED16) + val >>= 1; + } + insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift); + } + return insn; +} + +void +arc_handle_align (fragS* fragP) +{ + if ((fragP)->fr_type == rs_align_code) + { + char *dest = (fragP)->fr_literal + (fragP)->fr_fix; + valueT count = ((fragP)->fr_next->fr_address + - (fragP)->fr_address - (fragP)->fr_fix); + + (fragP)->fr_var = 2; + + if (count & 1)/* Padding in the gap till the next 2-byte + boundary with 0s. */ + { + (fragP)->fr_fix++; + *dest++ = 0; + } + /* Writing nop_s. */ + md_number_to_chars (dest, NOP_OPCODE_S, 2); + } +} + +/* Here we decide which fixups can be adjusted to make them relative + to the beginning of the section instead of the symbol. Basically + we need to make sure that the dynamic relocations are done + correctly, so in some cases we force the original symbol to be + used. */ + +int +tc_arc_fix_adjustable (fixS *fixP) +{ + + /* Prevent all adjustments to global symbols. */ + if (S_IS_EXTERNAL (fixP->fx_addsy)) + return 0; + if (S_IS_WEAK (fixP->fx_addsy)) + return 0; + + /* Adjust_reloc_syms doesn't know about the GOT. */ + switch (fixP->fx_r_type) + { + case BFD_RELOC_ARC_GOTPC32: + case BFD_RELOC_ARC_PLT32: + case BFD_RELOC_ARC_S25H_PCREL_PLT: + case BFD_RELOC_ARC_S21H_PCREL_PLT: + case BFD_RELOC_ARC_S25W_PCREL_PLT: + case BFD_RELOC_ARC_S21W_PCREL_PLT: + return 0; + + default: + break; + } + + return 0; /* FIXME! return 1, fix it in the linker. */ +} + +/* Compute the reloc type of an expression EXP. */ + +static void +arc_check_reloc (expressionS *exp, + bfd_reloc_code_real_type *r_type_p) +{ + if (*r_type_p == BFD_RELOC_32 + && exp->X_op == O_subtract + && exp->X_op_symbol != NULL + && exp->X_op_symbol->bsym->section == now_seg) + *r_type_p = BFD_RELOC_ARC_PC32; +} + + +/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */ + +void +arc_cons_fix_new (fragS *frag, + int off, + int size, + expressionS *exp, + bfd_reloc_code_real_type r_type) +{ + r_type = BFD_RELOC_UNUSED; + + switch (size) + { + case 1: + r_type = BFD_RELOC_8; + break; + + case 2: + r_type = BFD_RELOC_16; + break; + + case 3: + r_type = BFD_RELOC_24; + break; + + case 4: + r_type = BFD_RELOC_32; + arc_check_reloc (exp, &r_type); + break; + + case 8: + r_type = BFD_RELOC_64; + break; + + default: + as_bad (_("unsupported BFD relocation size %u"), size); + r_type = BFD_RELOC_UNUSED; + } + + fix_new_exp (frag, off, size, exp, 0, r_type); +} + +/* The actual routine that checks the ZOL conditions. */ + +static void +check_zol (symbolS *s) +{ + switch (arc_mach_type) + { + case bfd_mach_arc_arcv2: + if (arc_target & ARC_OPCODE_ARCv2EM) + return; + + if (is_br_jmp_insn_p (arc_last_insns[0].opcode) + || arc_last_insns[1].has_delay_slot) + as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"), + S_GET_NAME (s)); + + break; + case bfd_mach_arc_arc600: + + if (is_kernel_insn_p (arc_last_insns[0].opcode)) + as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"), + S_GET_NAME (s)); + + if (arc_last_insns[0].has_limm + && is_br_jmp_insn_p (arc_last_insns[0].opcode)) + as_bad (_("A jump instruction with long immediate detected at the \ +end of the ZOL label @%s"), S_GET_NAME (s)); + + /* Fall through. */ + case bfd_mach_arc_arc700: + if (arc_last_insns[0].has_delay_slot) + as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"), + S_GET_NAME (s)); + + break; + default: + break; + } +} + +/* If ZOL end check the last two instruction for illegals. */ +void +arc_frob_label (symbolS * sym) +{ + if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL) + check_zol (sym); + + dwarf2_emit_label (sym); } diff --git a/gas/config/tc-arc.h b/gas/config/tc-arc.h index 8eda165709..8fff7677b8 100644 --- a/gas/config/tc-arc.h +++ b/gas/config/tc-arc.h @@ -1,6 +1,7 @@ /* tc-arc.h - Macros and type defines for the ARC. - Copyright (C) 1994-2015 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). + Copyright 2014 Free Software Foundation, Inc. + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) This file is part of GAS, the GNU Assembler. @@ -19,56 +20,170 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -#define TC_ARC 1 -#define TARGET_BYTES_BIG_ENDIAN 0 +/* By convention, you should define this macro in the `.h' file. For + example, `tc-m68k.h' defines `TC_M68K'. You might have to use this + if it is necessary to add CPU specific code to the object format + file. */ +#define TC_ARC +/* We want local label support. */ #define LOCAL_LABELS_FB 1 +/* This macro is the BFD architecture to pass to + `bfd_set_arch_mach'. */ #define TARGET_ARCH bfd_arch_arc +/* The `extsym - .' expressions can be emitted using PC-relative + relocs. */ #define DIFF_EXPR_OK -#define REGISTER_PREFIX '%' - -#ifdef LITTLE_ENDIAN -#undef LITTLE_ENDIAN -#endif -#ifdef BIG_ENDIAN -#undef BIG_ENDIAN -#endif +#define REGISTER_PREFIX '%' +#undef LITTLE_ENDIAN #define LITTLE_ENDIAN 1234 +#undef BIG_ENDIAN #define BIG_ENDIAN 4321 +#ifdef TARGET_BYTES_BIG_ENDIAN + +# define DEFAULT_TARGET_FORMAT "elf32-bigarc" +# define DEFAULT_BYTE_ORDER BIG_ENDIAN + +#else +/* You should define this macro to be non-zero if the target is big + endian, and zero if the target is little endian. */ +# define TARGET_BYTES_BIG_ENDIAN 0 + +# define DEFAULT_TARGET_FORMAT "elf32-littlearc" +# define DEFAULT_BYTE_ORDER LITTLE_ENDIAN + +#endif /* TARGET_BYTES_BIG_ENDIAN. */ + /* The endianness of the target format may change based on command line arguments. */ -extern const char * arc_target_format; - -#define DEFAULT_TARGET_FORMAT "elf32-littlearc" -#define TARGET_FORMAT arc_target_format -#define DEFAULT_BYTE_ORDER LITTLE_ENDIAN +extern const char *arc_target_format; + +/* This macro is the BFD target name to use when creating the output + file. This will normally depend upon the `OBJ_FMT' macro. */ +#define TARGET_FORMAT arc_target_format + +/* `md_short_jump_size' + `md_long_jump_size' + `md_create_short_jump' + `md_create_long_jump' + + If `WORKING_DOT_WORD' is defined, GAS will not do broken word + processing (*note Broken words::.). Otherwise, you should set + `md_short_jump_size' to the size of a short jump (a jump that is + just long enough to jump around a long jmp) and `md_long_jump_size' + to the size of a long jump (a jump that can go anywhere in the + function). You should define `md_create_short_jump' to create a + short jump around a long jump, and define `md_create_long_jump' to + create a long jump. */ #define WORKING_DOT_WORD -#define LISTING_HEADER "ARC GAS " -/* The ARC needs to parse reloc specifiers in .word. */ +#define LISTING_HEADER "ARC GAS " -extern bfd_reloc_code_real_type arc_parse_cons_expression (struct expressionS *, - unsigned); -#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \ - arc_parse_cons_expression (EXP, NBYTES) +/* The number of bytes to put into a word in a listing. This affects + the way the bytes are clumped together in the listing. For + example, a value of 2 might print `1234 5678' where a value of 1 + would print `12 34 56 78'. The default value is 4. */ +#define LISTING_WORD_SIZE 2 -extern void arc_cons_fix_new (struct frag *, int, int, struct expressionS *, - bfd_reloc_code_real_type); -#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC) \ - arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP, RELOC) +/* If you define this macro, it should return the position from which + the PC relative adjustment for a PC relative fixup should be made. + On many processors, the base of a PC relative instruction is the + next instruction, so this macro would return the length of an + instruction, plus the address of the PC relative fixup. The latter + can be calculated as fixp->fx_where + + fixp->fx_frag->fr_address. */ +extern long md_pcrel_from_section (struct fix *, segT); +#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC) + +/* [ ] is index operator. */ +#define NEED_INDEX_OPERATOR -#define DWARF2_LINE_MIN_INSN_LENGTH 4 +#define MAX_MEM_FOR_RS_ALIGN_CODE (1+2) -/* Values passed to md_apply_fix don't include the symbol value. */ +/* HANDLE_ALIGN called after all the assembly has been done, + so we can fill in all the rs_align_code type frags with + nop instructions. */ +#define HANDLE_ALIGN(FRAGP) arc_handle_align (FRAGP) + +/* Values passed to md_apply_fix3 don't include the symbol value. */ #define MD_APPLY_SYM_VALUE(FIX) 0 /* No shared lib support, so we don't need to ensure externally visible symbols can be overridden. */ #define EXTERN_FORCE_RELOC 0 + +/* You may define this macro to generate a fixup for a data allocation + pseudo-op. */ +#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \ + arc_cons_fix_new ((FRAG), (OFF), (LEN), (EXP), (RELOC)) + +/* We don't want gas to fixup the following program memory related + relocations. */ +#define TC_VALIDATE_FIX(FIXP,SEG,SKIP) \ + if ((FIXP->fx_r_type == BFD_RELOC_ARC_GOTPC32) \ + && FIXP->fx_addsy != NULL \ + && FIXP->fx_subsy == NULL) \ + { \ + symbol_mark_used_in_reloc (FIXP->fx_addsy); \ + goto SKIP; \ + } + +/* BFD_RELOC_ARC_TLS_GD_LD may use fx_subsy to store a label that is + later turned into fx_offset. */ +#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ + ((FIX)->fx_r_type == BFD_RELOC_ARC_TLS_GD_LD) + +#define TC_VALIDATE_FIX_SUB(FIX, SEG) \ + ((md_register_arithmetic || (SEG) != reg_section) \ + && ((FIX)->fx_r_type == BFD_RELOC_GPREL32 \ + || (FIX)->fx_r_type == BFD_RELOC_GPREL16 \ + || (FIX)->fx_r_type == BFD_RELOC_ARC_TLS_DTPOFF \ + || (FIX)->fx_r_type == BFD_RELOC_ARC_TLS_DTPOFF_S9 \ + || TC_FORCE_RELOCATION_SUB_LOCAL (FIX, SEG))) + +/* We use this to mark the end-loop label. We use this mark for ZOL + validity checks. */ +#define TC_SYMFIELD_TYPE unsigned int +#define ARC_GET_FLAG(s) (*symbol_get_tc (s)) +#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v)) + +/* The symbol is a ZOL's end loop label. */ +#define ARC_FLAG_ZOL (1 << 0) + +/* We use this hook to check the validity of the last to instructions + of a ZOL. */ +#define tc_frob_label(S) arc_frob_label (S) + +#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" +#define DYNAMIC_STRUCT_NAME "_DYNAMIC" + +/* We need to take care of not having section relative fixups for the + fixups with respect to Position Independent Code. */ +#define tc_fix_adjustable(FIX) tc_arc_fix_adjustable(FIX) + +/* This hook is required to parse register names as operands. */ +#define md_parse_name(name, exp, m, c) arc_parse_name (name, exp) + +extern bfd_boolean arc_parse_name (const char *, struct expressionS *); +extern int tc_arc_fix_adjustable (struct fix *); +extern void arc_handle_align (fragS *); +extern void arc_cons_fix_new (fragS *, int, int, expressionS *, + bfd_reloc_code_real_type); +extern void arc_frob_label (symbolS *); + +/* The blink register is r31. */ +#define DWARF2_DEFAULT_RETURN_COLUMN 31 +/* Registers are generally saved at negative offsets to the CFA. */ +#define DWARF2_CIE_DATA_ALIGNMENT (-4) + +/* Define the NOPs. */ +#define NOP_OPCODE_S 0x000078E0 +#define NOP_OPCODE_L 0x264A7000 /* mov 0,0. */ + diff --git a/gas/configure.tgt b/gas/configure.tgt index 00fa10474a..0b490d4624 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -6,12 +6,12 @@ # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 3 of the License, or # (at your option) any later version. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; see the file COPYING3. If not see # <http://www.gnu.org/licenses/>. @@ -50,6 +50,7 @@ case ${cpu} in aarch64_be) cpu_type=aarch64 endian=big ;; alpha*) cpu_type=alpha ;; am33_2.0) cpu_type=mn10300 endian=little ;; + arc*eb) cpu_type=arc endian=big ;; arm*be|arm*b) cpu_type=arm endian=big ;; arm*) cpu_type=arm endian=little ;; bfin*) cpu_type=bfin endian=little ;; @@ -130,6 +131,7 @@ case ${generic_target} in alpha-*-openbsd*) fmt=elf em=obsd ;; arc-*-elf*) fmt=elf ;; + arc*-*-linux-uclibc*) fmt=elf bfd_gas=yes ;; arm-*-aout) fmt=aout ;; arm-*-coff) fmt=coff ;; @@ -352,7 +354,7 @@ case ${generic_target} in moxie-*-uclinux) fmt=elf em=linux ;; moxie-*-moxiebox*) fmt=elf endian=little ;; moxie-*-*) fmt=elf ;; - + mt-*-elf) fmt=elf bfd_gas=yes ;; msp430-*-*) fmt=elf ;; @@ -461,7 +463,7 @@ case ${generic_target} in visium-*-elf) fmt=elf ;; xstormy16-*-*) fmt=elf ;; - + xgate-*-*) fmt=elf ;; xtensa*-*-*) fmt=elf ;; diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index fa3221e20b..4ed29d1425 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -265,7 +265,9 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @ifset ARC @emph{Target ARC options:} - [@b{-marc[5|6|7|8]}] + [@b{-mcpu=@var{cpu}}] + [@b{-mA6}|@b{-mARC600}|@b{-mARC601}|@b{-mA7}|@b{-mARC700}|@b{-mEM}|@b{-mHS}] + [@b{-mcode-density}] [@b{-EB}|@b{-EL}] @end ifset @ifset ARM @@ -860,14 +862,16 @@ processor. @c man begin OPTIONS @ifset ARC -The following options are available when @value{AS} is configured for -an ARC processor. +The following options are available when @value{AS} is configured for an ARC +processor. @table @gcctabopt -@item -marc[5|6|7|8] +@item -mcpu=@var{cpu} This option selects the core processor variant. @item -EB | -EL Select either big-endian (-EB) or little-endian (-EL) output. +@item -mcode-density +Enable Code Density extenssion instructions. @end table @end ifset diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi index 9fa28e5fe2..f72ecae44b 100644 --- a/gas/doc/c-arc.texi +++ b/gas/doc/c-arc.texi @@ -19,52 +19,54 @@ @menu * ARC Options:: Options * ARC Syntax:: Syntax -* ARC Floating Point:: Floating Point * ARC Directives:: ARC Machine Directives +* ARC Modifiers:: ARC Assembler Modifiers +* ARC Symbols:: ARC Pre-defined Symbols * ARC Opcodes:: Opcodes @end menu - @node ARC Options @section Options -@cindex ARC options (none) -@cindex options for ARC (none) +@cindex ARC options +@cindex options for ARC + +The following options control the type of CPU for which code is +assembled, and generic constraints on the code generated: @table @code -@cindex @code{-marc[5|6|7|8]} command line option, ARC -@item -marc[5|6|7|8] -This option selects the core processor variant. Using -@code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which -is also the default. +@item -mcpu=@var{cpu} +@cindex @code{-mcpu=@var{cpu}} command line option, ARC +Set architecture type and register usage for @var{cpu}. There are +also shortcut alias options available for backward compatibility and +convenience. Supported values for @var{cpu} are @table @code +@cindex @code{mA6} command line option, ARC +@cindex @code{marc600} command line option, ARC +@item arc600 +Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}. -@cindex @code{arc5} arc5, ARC -@item arc5 -Base instruction set. +@item arc601 +@cindex @code{mARC601} command line option, ARC +Assemble for ARC 601. Alias: @code{-mARC601}. -@cindex @code{arc6} arc6, ARC -@item arc6 -Jump-and-link (jl) instruction. No requirement of an instruction between -setting flags and conditional jump. For example: +@item arc700 +@cindex @code{mA7} command line option, ARC +@cindex @code{mARC700} command line option, ARC +Assemble for ARC 700. Aliases: @code{-mA7}, @code{-mARC700}. -@smallexample - mov.f r0,r1 - beq foo -@end smallexample +@item arcem +@cindex @code{mEM} command line option, ARC +Assemble for ARC EM. Aliases: @code{-mEM} -@cindex @code{arc7} arc7, ARC -@item arc7 -Break (brk) and sleep (sleep) instructions. - -@cindex @code{arc8} arc8, ARC -@item arc8 -Software interrupt (swi) instruction. +@item archs +@cindex @code{mHS} command line option, ARC +Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}. @end table -Note: the @code{.option} directive can to be used to select a core +Note: the @code{.cpu} directive can to be used to select a core variant from within assembly code. @cindex @code{-EB} command line option, ARC @@ -78,6 +80,11 @@ This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor - this is the default. +@cindex @code{-mcode-density} command line option, ARC +@item -mcode-density +This option turns on Code Density instructions. Only valid for ARC EM +processors. + @end table @node ARC Syntax @@ -90,36 +97,211 @@ default. @node ARC-Chars @subsection Special Characters +@table @code +@item % +@cindex register name prefix character, ARC +@cindex ARC register name prefix character +A register name can optionally be prefixed by a @samp{%} character. So +register @code{%r0} is equivalent to @code{r0} in the assembly code. + +@item # @cindex line comment character, ARC @cindex ARC line comment character -The presence of a @samp{#} on a line indicates the start of a comment -that extends to the end of the current line. Note that if a line -starts with a @samp{#} character then it can also be a logical line -number directive (@pxref{Comments}) or a preprocessor -control command (@pxref{Preprocessing}). - +The presence of a @samp{#} character within a line (but not at the +start of a line) indicates the start of a comment that extends to the +end of the current line. + +@emph{Note:} if a line starts with a @samp{#} character then it can +also be a logical line number directive (@pxref{Comments}) or a +preprocessor control command (@pxref{Preprocessing}). + +@item @@ +@cindex symbol prefix character, ARC +@cindex ARC symbol prefix character +Prefixing an operand with an @samp{@@} specifies that the operand is a +symbol and not a register. This is how the assembler disambiguates +the use of an ARC register name as a symbol. So the instruction +@example +mov r0, @@r0 +@end example +moves the address of symbol @code{r0} into register @code{r0}. + +@item ` @cindex line separator, ARC @cindex statement separator, ARC @cindex ARC line separator -The ARC assembler does not support a line separator character. +The @samp{`} (backtick) character is used to separate statements on a +single line. + +@cindex line +@item - +@cindex C preprocessor macro separator, ARC +@cindex ARC C preprocessor macro separator +Used as a separator to obtain a sequence of commands from a C +preprocessor macro. + +@end table @node ARC-Regs @subsection Register Names @cindex ARC register names @cindex register names, ARC -*TODO* +The ARC assembler uses the following register names for its core +registers: + +@table @code +@item r0-r31 +@cindex core general registers, ARC +@cindex ARC core general registers +The core general registers. Registers @code{r26} through @code{r31} +have special functions, and are usually referred to by those synonyms. + +@item gp +@cindex global pointer, ARC +@cindex ARC global pointer +The global pointer and a synonym for @code{r26}. + +@item fp +@cindex frame pointer, ARC +@cindex ARC frame pointer +The frame pointer and a synonym for @code{r27}. + +@item sp +@cindex stack pointer, ARC +@cindex ARC stack pointer +The stack pointer and a synonym for @code{r28}. + +@item ilink1 +@cindex level 1 interrupt link register, ARC +@cindex ARC level 1 interrupt link register +For ARC 600 and ARC 700, the level 1 interrupt link register and a +synonym for @code{r29}. Not supported for ARCv2. + +@item ilink +@cindex interrupt link register, ARC +@cindex ARC interrupt link register +For ARCv2, the interrupt link register and a synonym for @code{r29}. +Not supported for ARC 600 and ARC 700. + +@item ilink2 +@cindex level 2 interrupt link register, ARC +@cindex ARC level 2 interrupt link register +For ARC 600 and ARC 700, the level 2 interrupt link register and a +synonym for @code{r30}. Not supported for ARC v2. + +@item blink +@cindex link register, ARC +@cindex ARC link register +The link register and a synonym for @code{r31}. + +@item r32-r59 +@cindex extension core registers, ARC +@cindex ARC extension core registers +The extension core registers. + +@item lp_count +@cindex loop counter, ARC +@cindex ARC loop counter +The loop count register. + +@item pcl +@cindex word aligned program counter, ARC +@cindex ARC word aligned program counter +The word aligned program counter. + +@end table +In addition the ARC processor has a large number of @emph{auxiliary +registers}. The precise set depends on the extensions being +supported, but the following baseline set are always defined: -@node ARC Floating Point -@section Floating Point +@table @code +@item identity +@cindex Processor Identification register, ARC +@cindex ARC Processor Identification register +Processor Identification register. Auxiliary register address 0x4. + +@item pc +@cindex Program Counter, ARC +@cindex ARC Program Counter +Program Counter. Auxiliary register address 0x6. + +@item status32 +@cindex Status register, ARC +@cindex ARC Status register +Status register. Auxiliary register address 0x0a. + +@item bta +@cindex Branch Target Address, ARC +@cindex ARC Branch Target Address +Branch Target Address. Auxiliary register address 0x412. + +@item ecr +@cindex Exception Cause Register, ARC +@cindex ARC Exception Cause Register +Exception Cause Register. Auxiliary register address 0x403. + +@item int_vector_base +@cindex Interrupt Vector Base address, ARC +@cindex ARC Interrupt Vector Base address +Interrupt Vector Base address. Auxiliary register address 0x25. + +@item status32_p0 +@cindex Stored STATUS32 register on entry to level P0 interrupts, ARC +@cindex ARC Stored STATUS32 register on entry to level P0 interrupts +Stored STATUS32 register on entry to level P0 interrupts. Auxiliary +register address 0xb. + +@item aux_user_sp +@cindex Saved User Stack Pointer, ARC +@cindex ARC Saved User Stack Pointer +Saved User Stack Pointer. Auxiliary register address 0xd. + +@item eret +@cindex Exception Return Address, ARC +@cindex ARC Exception Return Address +Exception Return Address. Auxiliary register address 0x400. + +@item erbta +@cindex BTA saved on exception entry, ARC +@cindex ARC BTA saved on exception entry +BTA saved on exception entry. Auxiliary register address 0x401. + +@item erstatus +@cindex STATUS32 saved on exception, ARC +@cindex ARC STATUS32 saved on exception +STATUS32 saved on exception. Auxiliary register address 0x402. + +@item bcr_ver +@cindex Build Configuration Registers Version, ARC +@cindex ARC Build Configuration Registers Version +Build Configuration Registers Version. Auxiliary register address 0x60. + +@item bta_link_build +@cindex Build configuration for: BTA Registers, ARC +@cindex ARC Build configuration for: BTA Registers +Build configuration for: BTA Registers. Auxiliary register address 0x63. + +@item vecbase_ac_build +@cindex Build configuration for: Interrupts, ARC +@cindex ARC Build configuration for: Interrupts +Build configuration for: Interrupts. Auxiliary register address 0x68. + +@item rf_build +@cindex Build configuration for: Core Registers, ARC +@cindex ARC Build configuration for: Core Registers +Build configuration for: Core Registers. Auxiliary register address 0x6e. + +@item dccm_build +@cindex DCCM RAM Configuration Register, ARC +@cindex ARC DCCM RAM Configuration Register +DCCM RAM Configuration Register. Auxiliary register address 0xc1. -@cindex floating point, ARC (@sc{ieee}) -@cindex ARC floating point (@sc{ieee}) -The ARC core does not currently have hardware floating point -support. Software floating point support is provided by @code{GCC} -and uses @sc{ieee} floating-point numbers. +@end table +Additional auxiliary register names are defined according to the +processor architecture version and extensions selected by the options. @node ARC Directives @section ARC Machine Directives @@ -131,205 +313,106 @@ machine directives: @table @code -@cindex @code{2byte} directive, ARC -@item .2byte @var{expressions} -*TODO* - -@cindex @code{3byte} directive, ARC -@item .3byte @var{expressions} -*TODO* - -@cindex @code{4byte} directive, ARC -@item .4byte @var{expressions} -*TODO* - -@cindex @code{extAuxRegister} directive, ARC -@item .extAuxRegister @var{name},@var{address},@var{mode} -The ARCtangent A4 has extensible auxiliary register space. The -auxiliary registers can be defined in the assembler source code by -using this directive. The first parameter is the @var{name} of the -new auxiallry register. The second parameter is the @var{address} of -the register in the auxiliary register memory map for the variant of -the ARC. The third parameter specifies the @var{mode} in which the -register can be operated is and it can be one of: - +@cindex @code{lcomm} directive +@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] +Reserve @var{length} (an absolute expression) bytes for a local common +denoted by @var{symbol}. The section and value of @var{symbol} are +those of the new local common. The addresses are allocated in the bss +section, so that at run-time the bytes start off zeroed. Since +@var{symbol} is not declared global, it is normally not visible to +@code{@value{LD}}. The optional third parameter, @var{alignment}, +specifies the desired alignment of the symbol in the bss section, +specified as a byte boundary (for example, an alignment of 16 means +that the least significant 4 bits of the address should be zero). The +alignment must be an absolute expression, and it must be a power of +two. If no alignment is specified, as will set the alignment to the +largest power of two less than or equal to the size of the symbol, up +to a maximum of 16. + +@cindex @code{lcommon} directive +@item .lcommon @var{symbol} , @var{length}[, @var{alignment}] +The same as @code{lcomm} directive. + +@cindex @code{cpu} directive, ARC +@cindex @code{cpu} directive, ARC +The @code{.cpu} directive must be followed by the desired core +version. Permitted values for CPU are: @table @code -@item r (readonly) -@item w (write only) -@item r|w (read or write) -@end table - -For example: - -@smallexample - .extAuxRegister mulhi,0x12,w -@end smallexample +@item ARC600 +Assemble for the ARC600 instruction set. -This specifies an extension auxiliary register called @emph{mulhi} -which is at address 0x12 in the memory space and which is only -writable. +@item ARC700 +Assemble for the ARC700 instruction set. -@cindex @code{extCondCode} directive, ARC -@item .extCondCode @var{suffix},@var{value} -The condition codes on the ARCtangent A4 are extensible and can be -specified by means of this assembler directive. They are specified -by the suffix and the value for the condition code. They can be used to -specify extra condition codes with any values. For example: +@item EM +Assemble for the ARC EM instruction set. -@smallexample - .extCondCode is_busy,0x14 +@item HS +Assemble for the ARC HS instruction set. - add.is_busy r1,r2,r3 - bis_busy _main -@end smallexample - -@cindex @code{extCoreRegister} directive, ARC -@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut} -Specifies an extension core register @var{name} for the application. -This allows a register @var{name} with a valid @var{regnum} between 0 -and 60, with the following as valid values for @var{mode} - -@table @samp -@item @emph{r} (readonly) -@item @emph{w} (write only) -@item @emph{r|w} (read or write) @end table - -The other parameter gives a description of the register having a -@var{shortcut} in the pipeline. The valid values are: - -@table @code -@item can_shortcut -@item cannot_shortcut +Note: the @code{.cpu} directive overrides the command line option +@code{-mcpu=@var{cpu}}; a warning is emitted when the version is not +consistent between the two. @end table -For example: - -@smallexample - .extCoreRegister mlo,57,r,can_shortcut -@end smallexample - -This defines an extension core register mlo with the value 57 which -can shortcut the pipeline. - -@cindex @code{extInstruction} directive, ARC -@item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass} -The ARCtangent A4 allows the user to specify extension instructions. -The extension instructions are not macros. The assembler creates -encodings for use of these instructions according to the specification -by the user. The parameters are: - -@itemize @bullet -@item @var{name} -Name of the extension instruction - -@item @var{opcode} -Opcode to be used. (Bits 27:31 in the encoding). Valid values -0x10-0x1f or 0x03 +@node ARC Modifiers +@section ARC Assembler Modifiers -@item @var{subopcode} -Subopcode to be used. Valid values are from 0x09-0x3f. However the -correct value also depends on @var{syntaxclass} - -@item @var{suffixclass} -Determines the kinds of suffixes to be allowed. Valid values are -@code{SUFFIX_NONE}, @code{SUFFIX_COND}, -@code{SUFFIX_FLAG} which indicates the absence or presence of -conditional suffixes and flag setting by the extension instruction. -It is also possible to specify that an instruction sets the flags and -is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}. - -@item @var{syntaxclass} -Determines the syntax class for the instruction. It can have the -following values: +The following additional assembler modifiers have been added for +position-independent code. These modifiers are available only with +the ARC 700 and above processors and generate relocation entries, +which are interpreted by the linker as follows: @table @code -@item @code{SYNTAX_2OP}: -2 Operand Instruction -@item @code{SYNTAX_3OP}: -3 Operand Instruction -@end table - -In addition there could be modifiers for the syntax class as described -below: - -@itemize @minus -Syntax Class Modifiers are: - -@item @code{OP1_MUST_BE_IMM}: -Modifies syntax class SYNTAX_3OP, specifying that the first operand -of a three-operand instruction must be an immediate (i.e., the result -is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with -SYNTAX_3OP as given in the example below. This could usually be used -to set the flags using specific instructions and not retain results. +@item @@pcl(@var{symbol}) +@cindex @@pcl(@var{symbol}), ARC modifier +Relative distance of @var{symbol}'s from the current program counter +location. + +@item @@gotpc(@var{symbol}) +@cindex @@gotpc(@var{symbol}), ARC modifier +Relative distance of @var{symbol}'s Global Offset Table entry from the +current program counter location. + +@item @@gotoff(@var{symbol}) +@cindex @@gotoff(@var{symbol}), ARC modifier +Distance of @var{symbol} from the base of the Global Offset Table. + +@item @@plt(@var{symbol}) +@cindex @@plt(@var{symbol}), ARC modifier +Distance of @var{symbol}'s Procedure Linkage Table entry from the +current program counter. This is valid only with branch and link +instructions and PC-relative calls. + +@item @@sda(@var{symbol}) +@cindex @@sda(@var{symbol}), ARC modifier +Relative distance of @var{symbol} from the base of the Small Data +Pointer. -@item @code{OP1_IMM_IMPLIED}: -Modifies syntax class SYNTAX_20P, it specifies that there is an -implied immediate destination operand which does not appear in the -syntax. For example, if the source code contains an instruction like: - -@smallexample -inst r1,r2 -@end smallexample - -it really means that the first argument is an implied immediate (that -is, the result is discarded). This is the same as though the source -code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it -with SYNTAX_20P. - -@end itemize -@end itemize - -For example, defining 64-bit multiplier with immediate operands: - -@smallexample -.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , - SYNTAX_3OP|OP1_MUST_BE_IMM -@end smallexample - -The above specifies an extension instruction called mp64 which has 3 operands, -sets the flags, can be used with a condition code, for which the -first operand is an immediate. (Equivalent to discarding the result -of the operation). - -@smallexample - .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED -@end smallexample - -This describes a 2 operand instruction with an implicit first -immediate operand. The result of this operation would be discarded. - -@cindex @code{half} directive, ARC -@item .half @var{expressions} -*TODO* - -@cindex @code{long} directive, ARC -@item .long @var{expressions} -*TODO* +@end table -@cindex @code{option} directive, ARC -@item .option @var{arc|arc5|arc6|arc7|arc8} -The @code{.option} directive must be followed by the desired core -version. Again @code{arc} is an alias for -@code{arc@value{ARC_CORE_DEFAULT}}. +@node ARC Symbols +@section ARC Pre-defined Symbols -Note: the @code{.option} directive overrides the command line option -@code{-marc}; a warning is emitted when the version is not consistent -between the two - even for the implicit default core version -(arc@value{ARC_CORE_DEFAULT}). +The following assembler symbols will prove useful when developing +position-independent code. These symbols are available only with the +ARC 700 and above processors. -@cindex @code{short} directive, ARC -@item .short @var{expressions} -*TODO* +@table @code +@item __GLOBAL_OFFSET_TABLE__ +@cindex __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol +Symbol referring to the base of the Global Offset Table. -@cindex @code{word} directive, ARC -@item .word @var{expressions} -*TODO* +@item __DYNAMIC__ +@cindex __DYNAMIC__, ARC pre-defined symbol +An alias for the Global Offset Table +@code{Base__GLOBAL_OFFSET_TABLE__}. It can be used only with +@code{@@gotpc} modifiers. @end table - @node ARC Opcodes @section Opcodes @@ -337,4 +420,4 @@ between the two - even for the implicit default core version @cindex opcodes for ARC For information on the ARC instruction set, see @cite{ARC Programmers -Reference Manual}, ARC International (www.arc.com) +Reference Manual}, available where you download the processor IP library. diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index ba63994539..814d0a68a3 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,80 @@ +2015-10-07 Claudiu Zissulescu <claziss@synopsys.com> + + * gas/arc/adc.s: Update test for ARCv1/ARCv2. + * gas/arc/adc.d: Expected output. + * gas/arc/add.s: Update test for ARCv1/ARCv2. + * gas/arc/add.d: Expected output. + * gas/arc/and.s: Update test for ARCv1/ARCv2. + * gas/arc/and.d: Expected output. + * gas/arc/arc.exp: Cleanup. + * gas/arc/asl.s: Update test for ARCv1/ARCv2. + * gas/arc/asl.d: Expected output. + * gas/arc/asr.s: Update test for ARCv1/ARCv2. + * gas/arc/asr.d: Expected output. + * gas/arc/b.s: Update test for ARCv1/ARCv2. + * gas/arc/b.d: Expected output. + * gas/arc/bic.s: Update test for ARCv1/ARCv2. + * gas/arc/bic.d: Expected output. + * gas/arc/bl.s: Update test for ARCv1/ARCv2. + * gas/arc/bl.d: Expected output. + * gas/arc/brk.s: Update test for ARCv1/ARCv2. + * gas/arc/brk.d: Expected output. + * gas/arc/extb.s: Update test for ARCv1/ARCv2. + * gas/arc/extb.d: Expected output. + * gas/arc/extw.s: Update test for ARCv1/ARCv2. + * gas/arc/extw.d: Expected output. + * gas/arc/flag.d: Update output for ARCv1/ARCv2. + * gas/arc/j.s: Update test for ARCv1/ARCv2. + * gas/arc/j.d: Expected output. + * gas/arc/jl.s: Update test for ARCv1/ARCv2. + * gas/arc/jl.d: Expected output. + * gas/arc/ld.s: Update test for ARCv1/ARCv2. + * gas/arc/ld.d: Expected output. + * gas/arc/ld2.s: Update test for ARCv1/ARCv2. + * gas/arc/ld2.d: Expected output. + * gas/arc/lp.s: Update test for ARCv1/ARCv2. + * gas/arc/lp.d: Expected output. + * gas/arc/lsr.s: Update test for ARCv1/ARCv2. + * gas/arc/lsr.d: Expected output. + * gas/arc/mov.s: Update test for ARCv1/ARCv2. + * gas/arc/mov.d: Expected output. + * gas/arc/nop.s: Update test for ARCv1/ARCv2. + * gas/arc/nop.d: Expected output. + * gas/arc/or.s: Update test for ARCv1/ARCv2. + * gas/arc/or.d: Expected output. + * gas/arc/rlc.s: Update test for ARCv1/ARCv2. + * gas/arc/rlc.d: Expected output. + * gas/arc/ror.s: Update test for ARCv1/ARCv2. + * gas/arc/ror.d: Expected output. + * gas/arc/rrc.s: Update test for ARCv1/ARCv2. + * gas/arc/rrc.d: Expected output. + * gas/arc/sbc.s: Update test for ARCv1/ARCv2. + * gas/arc/sbc.d: Expected output. + * gas/arc/sexb.s: Update test for ARCv1/ARCv2. + * gas/arc/sexb.d: Expected output. + * gas/arc/sexw.s: Update test for ARCv1/ARCv2. + * gas/arc/sexw.d: Expected output. + * gas/arc/sleep.s: Update test for ARCv1/ARCv2. + * gas/arc/sleep.d: Expected output. + * gas/arc/st.s: Update test for ARCv1/ARCv2. + * gas/arc/st.d: Expected output. + * gas/arc/sub.s: Update test for ARCv1/ARCv2. + * gas/arc/sub.d: Expected output. + * gas/arc/swi.d: Update expected output for ARCv1/ARCv2. + * gas/arc/warn.exp: Cleanup + * gas/arc/xor.s: Update test for ARCv1/ARCv2. + * gas/arc/xor.d: Expected output. + * gas/arc/alias.d: Removed. + * gas/arc/alias.s: Likewise. + * gas/arc/branch.d: Likewise. + * gas/arc/branch.s: Likewise. + * gas/arc/insn3.d: Likewise. + * gas/arc/insn3.s: Likewise. + * gas/arc/math.d: Likewise. + * gas/arc/math.s: Likewise. + * gas/arc/sshift.d: Likewise. + * gas/arc/sshift.s: Likewise. + 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-tlsdesc_off_g0_nc.d: New. diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index 0af9bd03fb..6aaf4b8ab1 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -152,7 +152,7 @@ case $target_triplet in { run_dump_test redef # These targets fail redef2 because they disallow redefined # symbols on relocs. - setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" + setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "arc-*-*" setup_xfail "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" run_dump_test redef2 setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" diff --git a/gas/testsuite/gas/arc/adc.d b/gas/testsuite/gas/arc/adc.d index 7cb8523e8f..b6cf253692 100644 --- a/gas/testsuite/gas/arc/adc.d +++ b/gas/testsuite/gas/arc/adc.d @@ -1,85 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 84 00 48 48008400 adc r0,r1,r2 - 4: 00 b8 4d 4b 4b4db800 adc gp,fp,sp - 8: 00 3e af 4b 4baf3e00 adc ilink1,ilink2,blink - c: 00 f8 1d 4f 4f1df800 adc r56,r59,lp_count - 10: 00 fe 00 48 4800fe00 adc r0,r1,0 - 14: 00 84 1f 48 481f8400 adc r0,0,r2 - 18: 00 84 e0 4f 4fe08400 adc 0,r1,r2 - 1c: ff ff 00 48 4800ffff adc r0,r1,-1 - 20: ff 85 1f 48 481f85ff adc r0,-1,r2 - 24: 00 84 e0 4f 4fe08400 adc 0,r1,r2 - 28: ff fe 00 48 4800feff adc r0,r1,255 - 2c: ff 84 1f 48 481f84ff adc r0,255,r2 - 30: 00 84 e0 4f 4fe08400 adc 0,r1,r2 - 34: 00 ff 00 48 4800ff00 adc r0,r1,-256 - 38: 00 85 1f 48 481f8500 adc r0,-256,r2 - 3c: 00 84 e0 4f 4fe08400 adc 0,r1,r2 - 40: 00 fc 00 48 4800fc00 adc r0,r1,0x100 - 44: 00 01 00 00 - 48: 00 04 1f 48 481f0400 adc r0,0xffff_feff,r2 - 4c: ff fe ff ff - 50: ff fc 1f 48 481ffcff adc r0,255,0x100 - 54: 00 01 00 00 - 58: ff 7e 1f 48 481f7eff adc r0,0x100,255 - 5c: 00 01 00 00 - 60: 00 fc 00 48 4800fc00 adc r0,r1,0 - 64: 00 00 00 00 - 64: R_ARC_32 foo - 68: 00 84 00 48 48008400 adc r0,r1,r2 - 6c: 00 0a 62 48 48620a00 adc r3,r4,r5 - 70: 01 90 c3 48 48c39001 adc.z r6,r7,r8 - 74: 01 16 25 49 49251601 adc.z r9,r10,r11 - 78: 02 9c 86 49 49869c02 adc.nz r12,r13,r14 - 7c: 02 22 e8 49 49e82202 adc.nz r15,r16,r17 - 80: 03 a8 49 4a 4a49a803 adc.p r18,r19,r20 - 84: 03 2e ab 4a 4aab2e03 adc.p r21,r22,r23 - 88: 04 b4 0c 4b 4b0cb404 adc.n r24,r25,gp - 8c: 04 3a 6e 4b 4b6e3a04 adc.n fp,sp,ilink1 - 90: 05 c0 cf 4b 4bcfc005 adc.c ilink2,blink,r32 - 94: 05 46 31 4c 4c314605 adc.c r33,r34,r35 - 98: 05 cc 92 4c 4c92cc05 adc.c r36,r37,r38 - 9c: 06 52 f4 4c 4cf45206 adc.nc r39,r40,r41 - a0: 06 d8 55 4d 4d55d806 adc.nc r42,r43,r44 - a4: 06 5e b7 4d 4db75e06 adc.nc r45,r46,r47 - a8: 07 e4 18 4e 4e18e407 adc.v r48,r49,r50 - ac: 07 6a 1a 4f 4f1a6a07 adc.v r56,r52,r53 - b0: 08 f0 1b 4f 4f1bf008 adc.nv r56,r55,r56 - b4: 08 76 1d 4f 4f1d7608 adc.nv r56,r58,r59 - b8: 09 00 9e 4f 4f9e0009 adc.gt lp_count,lp_count,r0 - bc: 0a 7c 00 48 48007c0a adc.ge r0,r0,0 - c0: 00 00 00 00 - c4: 0b 02 3f 48 483f020b adc.lt r1,1,r1 - c8: 01 00 00 00 - cc: 0d 06 7f 48 487f060d adc.hi r3,3,r3 - d0: 03 00 00 00 - d4: 0e 08 df 4f 4fdf080e adc.ls 0,4,r4 - d8: 04 00 00 00 - dc: 0f fc c2 4f 4fc2fc0f adc.pnz 0,r5,5 - e0: 05 00 00 00 - e4: 00 85 00 48 48008500 adc.f r0,r1,r2 - e8: 01 fa 00 48 4800fa01 adc.f r0,r1,1 - ec: 01 84 1e 48 481e8401 adc.f r0,1,r2 - f0: 00 85 e0 4f 4fe08500 adc.f 0,r1,r2 - f4: 00 fd 00 48 4800fd00 adc.f r0,r1,0x200 - f8: 00 02 00 00 - fc: 00 05 1f 48 481f0500 adc.f r0,0x200,r2 - 100: 00 02 00 00 - 104: 01 85 00 48 48008501 adc.z.f r0,r1,r2 - 108: 02 fd 00 48 4800fd02 adc.nz.f r0,r1,0 - 10c: 00 00 00 00 - 110: 0b 05 1f 48 481f050b adc.lt.f r0,0,r2 - 114: 00 00 00 00 - 118: 09 85 c0 4f 4fc08509 adc.gt.f 0,r1,r2 - 11c: 00 00 00 00 00000000 - 120: 0c fd 00 48 4800fd0c adc.le.f r0,r1,0x200 - 124: 00 02 00 00 - 128: 0a 05 1f 48 481f050a adc.ge.f r0,0x200,r2 - 12c: 00 02 00 00 +0x[0-9a-f]+ 2101 0080 adc r0,r1,r2 +0x[0-9a-f]+ 2301 371a adc gp,fp,sp +0x[0-9a-f]+ 2601 37dd adc ilink,r30,blink +0x[0-9a-f]+ 2141 0000 adc r0,r1,0 +0x[0-9a-f]+ 2601 7080 0000 0000 adc r0,0,r2 +0x[0-9a-f]+ 2101 00be adc 0,r1,r2 +0x[0-9a-f]+ 2101 0f80 ffff ffff adc r0,r1,0xffffffff +0x[0-9a-f]+ 2601 7080 ffff ffff adc r0,0xffffffff,r2 +0x[0-9a-f]+ 2101 0f80 0000 00ff adc r0,r1,0xff +0x[0-9a-f]+ 2601 7080 0000 00ff adc r0,0xff,r2 +0x[0-9a-f]+ 2101 0f80 ffff ff00 adc r0,r1,0xffffff00 +0x[0-9a-f]+ 2601 7080 ffff ff00 adc r0,0xffffff00,r2 +0x[0-9a-f]+ 2101 0f80 0000 0100 adc r0,r1,0x100 +0x[0-9a-f]+ 2601 7080 ffff feff adc r0,0xfffffeff,r2 +0x[0-9a-f]+ 2601 7f80 0000 0100 adc r0,0x100,0x100 +0x[0-9a-f]+ 2101 0f80 0000 0000 adc r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 20c1 0080 adc r0,r0,r2 +0x[0-9a-f]+ 23c1 0140 adc r3,r3,r5 +0x[0-9a-f]+ 26c1 0201 adc.eq r6,r6,r8 +0x[0-9a-f]+ 21c1 12c1 adc.eq r9,r9,r11 +0x[0-9a-f]+ 24c1 1382 adc.ne r12,r12,r14 +0x[0-9a-f]+ 27c1 1442 adc.ne r15,r15,r17 +0x[0-9a-f]+ 22c1 2503 adc.p r18,r18,r20 +0x[0-9a-f]+ 25c1 25c3 adc.p r21,r21,r23 +0x[0-9a-f]+ 20c1 3684 adc.n r24,r24,gp +0x[0-9a-f]+ 23c1 3744 adc.n fp,fp,ilink +0x[0-9a-f]+ 26c1 37c5 adc.c r30,r30,blink +0x[0-9a-f]+ 23c1 00c5 adc.c r3,r3,r3 +0x[0-9a-f]+ 23c1 0205 adc.c r3,r3,r8 +0x[0-9a-f]+ 23c1 0106 adc.nc r3,r3,r4 +0x[0-9a-f]+ 24c1 0106 adc.nc r4,r4,r4 +0x[0-9a-f]+ 24c1 01c6 adc.nc r4,r4,r7 +0x[0-9a-f]+ 24c1 0147 adc.v r4,r4,r5 +0x[0-9a-f]+ 25c1 0147 adc.v r5,r5,r5 +0x[0-9a-f]+ 25c1 0148 adc.nv r5,r5,r5 +0x[0-9a-f]+ 25c1 0148 adc.nv r5,r5,r5 +0x[0-9a-f]+ 26c1 0009 adc.gt r6,r6,r0 +0x[0-9a-f]+ 20c1 002a adc.ge r0,r0,0 +0x[0-9a-f]+ 21c1 006b adc.lt r1,r1,0x1 +0x[0-9a-f]+ 23c1 00ed adc.hi r3,r3,0x3 +0x[0-9a-f]+ 24c1 012e adc.ls r4,r4,0x4 +0x[0-9a-f]+ 25c1 016f adc.pnz r5,r5,0x5 +0x[0-9a-f]+ 2101 8080 adc.f r0,r1,r2 +0x[0-9a-f]+ 2141 8040 adc.f r0,r1,0x1 +0x[0-9a-f]+ 2601 f080 0000 0001 adc.f r0,0x1,r2 +0x[0-9a-f]+ 2101 80be adc.f 0,r1,r2 +0x[0-9a-f]+ 2101 8f80 0000 0200 adc.f r0,r1,0x200 +0x[0-9a-f]+ 2601 f080 0000 0200 adc.f r0,0x200,r2 +0x[0-9a-f]+ 21c1 8081 adc.f.eq r1,r1,r2 +0x[0-9a-f]+ 20c1 8022 adc.f.ne r0,r0,0 +0x[0-9a-f]+ 22c1 808b adc.f.lt r2,r2,r2 +0x[0-9a-f]+ 26c1 f0a9 0000 0001 adc.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 26c1 ff8c 0000 0200 adc.f.le 0,0x200,0x200 +0x[0-9a-f]+ 26c1 f0aa 0000 0200 adc.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/adc.s b/gas/testsuite/gas/arc/adc.s index 162f6b8290..213f0005f6 100644 --- a/gas/testsuite/gas/arc/adc.s +++ b/gas/testsuite/gas/arc/adc.s @@ -3,55 +3,50 @@ adc r0,r1,r2 adc r26,fp,sp adc ilink1,ilink2,blink - adc r56,r59,lp_count adc r0,r1,0 adc r0,0,r2 adc 0,r1,r2 adc r0,r1,-1 adc r0,-1,r2 - adc -1,r1,r2 adc r0,r1,255 adc r0,255,r2 - adc 255,r1,r2 adc r0,r1,-256 adc r0,-256,r2 - adc -256,r1,r2 adc r0,r1,256 adc r0,-257,r2 - adc r0,255,256 - adc r0,256,255 + adc r0,256,256 adc r0,r1,foo - adc.al r0,r1,r2 - adc.ra r3,r4,r5 - adc.eq r6,r7,r8 - adc.z r9,r10,r11 - adc.ne r12,r13,r14 - adc.nz r15,r16,r17 - adc.pl r18,r19,r20 - adc.p r21,r22,r23 - adc.mi r24,r25,r26 - adc.n r27,r28,r29 - adc.cs r30,r31,r32 - adc.c r33,r34,r35 - adc.lo r36,r37,r38 - adc.cc r39,r40,r41 - adc.nc r42,r43,r44 - adc.hs r45,r46,r47 - adc.vs r48,r49,r50 - adc.v r56,r52,r53 - adc.vc r56,r55,r56 - adc.nv r56,r58,r59 - adc.gt r60,r60,r0 + adc.al r0,r0,r2 + adc.ra r3,r3,r5 + adc.eq r6,r6,r8 + adc.z r9,r9,r11 + adc.ne r12,r12,r14 + adc.nz r15,r15,r17 + adc.pl r18,r18,r20 + adc.p r21,r21,r23 + adc.mi r24,r24,r26 + adc.n r27,r27,r29 + adc.cs r30,r30,r31 + adc.c r3,r3,r3 + adc.lo r3,r3,r8 + adc.cc r3,r3,r4 + adc.nc r4,r4,r4 + adc.hs r4,r4,r7 + adc.vs r4,r4,r5 + adc.v r5,r5,r5 + adc.vc r5,r5,r5 + adc.nv r5,r5,r5 + adc.gt r6,r6,r0 adc.ge r0,r0,0 - adc.lt r1,1,r1 - adc.hi r3,3,r3 - adc.ls 4,4,r4 - adc.pnz 5,r5,5 + adc.lt r1,r1,1 + adc.hi r3,r3,3 + adc.ls r4,r4,4 + adc.pnz r5,r5,5 adc.f r0,r1,r2 adc.f r0,r1,1 @@ -60,9 +55,9 @@ adc.f r0,r1,512 adc.f r0,512,r2 - adc.eq.f r0,r1,r2 - adc.ne.f r0,r1,0 - adc.lt.f r0,0,r2 - adc.gt.f 0,r1,r2 - adc.le.f r0,r1,512 - adc.ge.f r0,512,r2 + adc.eq.f r1,r1,r2 + adc.ne.f r0,r0,0 + adc.lt.f r2,r2,r2 + adc.gt.f 0,1,2 + adc.le.f 0,512,512 + adc.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/add.d b/gas/testsuite/gas/arc/add.d index 864bc4dcb3..e1cdc5c670 100644 --- a/gas/testsuite/gas/arc/add.d +++ b/gas/testsuite/gas/arc/add.d @@ -1,85 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 84 00 40 40008400 add r0,r1,r2 - 4: 00 b8 4d 43 434db800 add gp,fp,sp - 8: 00 3e af 43 43af3e00 add ilink1,ilink2,blink - c: 00 f8 1d 47 471df800 add r56,r59,lp_count - 10: 00 fe 00 40 4000fe00 add r0,r1,0 - 14: 00 84 1f 40 401f8400 add r0,0,r2 - 18: 00 84 e0 47 47e08400 add 0,r1,r2 - 1c: ff ff 00 40 4000ffff add r0,r1,-1 - 20: ff 85 1f 40 401f85ff add r0,-1,r2 - 24: 00 84 e0 47 47e08400 add 0,r1,r2 - 28: ff fe 00 40 4000feff add r0,r1,255 - 2c: ff 84 1f 40 401f84ff add r0,255,r2 - 30: 00 84 e0 47 47e08400 add 0,r1,r2 - 34: 00 ff 00 40 4000ff00 add r0,r1,-256 - 38: 00 85 1f 40 401f8500 add r0,-256,r2 - 3c: 00 84 e0 47 47e08400 add 0,r1,r2 - 40: 00 fc 00 40 4000fc00 add r0,r1,0x100 - 44: 00 01 00 00 - 48: 00 04 1f 40 401f0400 add r0,0xffff_feff,r2 - 4c: ff fe ff ff - 50: ff fc 1f 40 401ffcff add r0,255,0x100 - 54: 00 01 00 00 - 58: ff 7e 1f 40 401f7eff add r0,0x100,255 - 5c: 00 01 00 00 - 60: 00 fc 00 40 4000fc00 add r0,r1,0 - 64: 00 00 00 00 - 64: R_ARC_32 foo - 68: 00 84 00 40 40008400 add r0,r1,r2 - 6c: 00 0a 62 40 40620a00 add r3,r4,r5 - 70: 01 90 c3 40 40c39001 add.z r6,r7,r8 - 74: 01 16 25 41 41251601 add.z r9,r10,r11 - 78: 02 9c 86 41 41869c02 add.nz r12,r13,r14 - 7c: 02 22 e8 41 41e82202 add.nz r15,r16,r17 - 80: 03 a8 49 42 4249a803 add.p r18,r19,r20 - 84: 03 2e ab 42 42ab2e03 add.p r21,r22,r23 - 88: 04 b4 0c 43 430cb404 add.n r24,r25,gp - 8c: 04 3a 6e 43 436e3a04 add.n fp,sp,ilink1 - 90: 05 c0 cf 43 43cfc005 add.c ilink2,blink,r32 - 94: 05 46 31 44 44314605 add.c r33,r34,r35 - 98: 05 cc 92 44 4492cc05 add.c r36,r37,r38 - 9c: 06 52 f4 44 44f45206 add.nc r39,r40,r41 - a0: 06 d8 55 45 4555d806 add.nc r42,r43,r44 - a4: 06 5e b7 45 45b75e06 add.nc r45,r46,r47 - a8: 07 e4 18 46 4618e407 add.v r48,r49,r50 - ac: 07 6a 1a 47 471a6a07 add.v r56,r52,r53 - b0: 08 f0 1b 47 471bf008 add.nv r56,r55,r56 - b4: 08 76 1d 47 471d7608 add.nv r56,r58,r59 - b8: 09 00 9e 47 479e0009 add.gt lp_count,lp_count,r0 - bc: 0a 7c 00 40 40007c0a add.ge r0,r0,0 - c0: 00 00 00 00 - c4: 0b 02 3f 40 403f020b add.lt r1,1,r1 - c8: 01 00 00 00 - cc: 0d 06 7f 40 407f060d add.hi r3,3,r3 - d0: 03 00 00 00 - d4: 0e 08 df 47 47df080e add.ls 0,4,r4 - d8: 04 00 00 00 - dc: 0f fc c2 47 47c2fc0f add.pnz 0,r5,5 - e0: 05 00 00 00 - e4: 00 85 00 40 40008500 add.f r0,r1,r2 - e8: 01 fa 00 40 4000fa01 add.f r0,r1,1 - ec: 01 84 1e 40 401e8401 add.f r0,1,r2 - f0: 00 85 e0 47 47e08500 add.f 0,r1,r2 - f4: 00 fd 00 40 4000fd00 add.f r0,r1,0x200 - f8: 00 02 00 00 - fc: 00 05 1f 40 401f0500 add.f r0,0x200,r2 - 100: 00 02 00 00 - 104: 01 85 00 40 40008501 add.z.f r0,r1,r2 - 108: 02 fd 00 40 4000fd02 add.nz.f r0,r1,0 - 10c: 00 00 00 00 - 110: 0b 05 1f 40 401f050b add.lt.f r0,0,r2 - 114: 00 00 00 00 - 118: 09 85 c0 47 47c08509 add.gt.f 0,r1,r2 - 11c: 00 00 00 00 00000000 - 120: 0c fd 00 40 4000fd0c add.le.f r0,r1,0x200 - 124: 00 02 00 00 - 128: 0a 05 1f 40 401f050a add.ge.f r0,0x200,r2 - 12c: 00 02 00 00 +0x[0-9a-f]+ 2100 0080 add r0,r1,r2 +0x[0-9a-f]+ 2300 371a add gp,fp,sp +0x[0-9a-f]+ 2600 37dd add ilink,r30,blink +0x[0-9a-f]+ 2140 0000 add r0,r1,0 +0x[0-9a-f]+ 2600 7080 0000 0000 add r0,0,r2 +0x[0-9a-f]+ 2100 00be add 0,r1,r2 +0x[0-9a-f]+ 2100 0f80 ffff ffff add r0,r1,0xffffffff +0x[0-9a-f]+ 2600 7080 ffff ffff add r0,0xffffffff,r2 +0x[0-9a-f]+ 2100 0f80 0000 00ff add r0,r1,0xff +0x[0-9a-f]+ 2600 7080 0000 00ff add r0,0xff,r2 +0x[0-9a-f]+ 2100 0f80 ffff ff00 add r0,r1,0xffffff00 +0x[0-9a-f]+ 2600 7080 ffff ff00 add r0,0xffffff00,r2 +0x[0-9a-f]+ 2100 0f80 0000 0100 add r0,r1,0x100 +0x[0-9a-f]+ 2600 7080 ffff feff add r0,0xfffffeff,r2 +0x[0-9a-f]+ 2600 7f80 0000 0100 add r0,0x100,0x100 +0x[0-9a-f]+ 2100 0f80 0000 0000 add r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 20c0 0080 add r0,r0,r2 +0x[0-9a-f]+ 23c0 0140 add r3,r3,r5 +0x[0-9a-f]+ 26c0 0201 add.eq r6,r6,r8 +0x[0-9a-f]+ 21c0 12c1 add.eq r9,r9,r11 +0x[0-9a-f]+ 24c0 1382 add.ne r12,r12,r14 +0x[0-9a-f]+ 27c0 1442 add.ne r15,r15,r17 +0x[0-9a-f]+ 22c0 2503 add.p r18,r18,r20 +0x[0-9a-f]+ 25c0 25c3 add.p r21,r21,r23 +0x[0-9a-f]+ 20c0 3684 add.n r24,r24,gp +0x[0-9a-f]+ 23c0 3744 add.n fp,fp,ilink +0x[0-9a-f]+ 26c0 37c5 add.c r30,r30,blink +0x[0-9a-f]+ 23c0 00c5 add.c r3,r3,r3 +0x[0-9a-f]+ 23c0 0205 add.c r3,r3,r8 +0x[0-9a-f]+ 23c0 0106 add.nc r3,r3,r4 +0x[0-9a-f]+ 24c0 0106 add.nc r4,r4,r4 +0x[0-9a-f]+ 24c0 01c6 add.nc r4,r4,r7 +0x[0-9a-f]+ 24c0 0147 add.v r4,r4,r5 +0x[0-9a-f]+ 25c0 0147 add.v r5,r5,r5 +0x[0-9a-f]+ 25c0 0148 add.nv r5,r5,r5 +0x[0-9a-f]+ 25c0 0148 add.nv r5,r5,r5 +0x[0-9a-f]+ 26c0 0009 add.gt r6,r6,r0 +0x[0-9a-f]+ 20c0 002a add.ge r0,r0,0 +0x[0-9a-f]+ 21c0 006b add.lt r1,r1,0x1 +0x[0-9a-f]+ 23c0 00ed add.hi r3,r3,0x3 +0x[0-9a-f]+ 24c0 012e add.ls r4,r4,0x4 +0x[0-9a-f]+ 25c0 016f add.pnz r5,r5,0x5 +0x[0-9a-f]+ 2100 8080 add.f r0,r1,r2 +0x[0-9a-f]+ 2140 8040 add.f r0,r1,0x1 +0x[0-9a-f]+ 2600 f080 0000 0001 add.f r0,0x1,r2 +0x[0-9a-f]+ 2100 80be add.f 0,r1,r2 +0x[0-9a-f]+ 2100 8f80 0000 0200 add.f r0,r1,0x200 +0x[0-9a-f]+ 2600 f080 0000 0200 add.f r0,0x200,r2 +0x[0-9a-f]+ 21c0 8081 add.f.eq r1,r1,r2 +0x[0-9a-f]+ 20c0 8022 add.f.ne r0,r0,0 +0x[0-9a-f]+ 22c0 808b add.f.lt r2,r2,r2 +0x[0-9a-f]+ 26c0 f0a9 0000 0001 add.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 26c0 ff8c 0000 0200 add.f.le 0,0x200,0x200 +0x[0-9a-f]+ 26c0 f0aa 0000 0200 add.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/add.s b/gas/testsuite/gas/arc/add.s index 8e74971bd9..ffa747ee01 100644 --- a/gas/testsuite/gas/arc/add.s +++ b/gas/testsuite/gas/arc/add.s @@ -3,55 +3,50 @@ add r0,r1,r2 add r26,fp,sp add ilink1,ilink2,blink - add r56,r59,lp_count add r0,r1,0 add r0,0,r2 add 0,r1,r2 add r0,r1,-1 add r0,-1,r2 - add -1,r1,r2 add r0,r1,255 add r0,255,r2 - add 255,r1,r2 add r0,r1,-256 add r0,-256,r2 - add -256,r1,r2 add r0,r1,256 add r0,-257,r2 - add r0,255,256 - add r0,256,255 + add r0,256,256 add r0,r1,foo - add.al r0,r1,r2 - add.ra r3,r4,r5 - add.eq r6,r7,r8 - add.z r9,r10,r11 - add.ne r12,r13,r14 - add.nz r15,r16,r17 - add.pl r18,r19,r20 - add.p r21,r22,r23 - add.mi r24,r25,r26 - add.n r27,r28,r29 - add.cs r30,r31,r32 - add.c r33,r34,r35 - add.lo r36,r37,r38 - add.cc r39,r40,r41 - add.nc r42,r43,r44 - add.hs r45,r46,r47 - add.vs r48,r49,r50 - add.v r56,r52,r53 - add.vc r56,r55,r56 - add.nv r56,r58,r59 - add.gt r60,r60,r0 + add.al r0,r0,r2 + add.ra r3,r3,r5 + add.eq r6,r6,r8 + add.z r9,r9,r11 + add.ne r12,r12,r14 + add.nz r15,r15,r17 + add.pl r18,r18,r20 + add.p r21,r21,r23 + add.mi r24,r24,r26 + add.n r27,r27,r29 + add.cs r30,r30,r31 + add.c r3,r3,r3 + add.lo r3,r3,r8 + add.cc r3,r3,r4 + add.nc r4,r4,r4 + add.hs r4,r4,r7 + add.vs r4,r4,r5 + add.v r5,r5,r5 + add.vc r5,r5,r5 + add.nv r5,r5,r5 + add.gt r6,r6,r0 add.ge r0,r0,0 - add.lt r1,1,r1 - add.hi r3,3,r3 - add.ls 4,4,r4 - add.pnz 5,r5,5 + add.lt r1,r1,1 + add.hi r3,r3,3 + add.ls r4,r4,4 + add.pnz r5,r5,5 add.f r0,r1,r2 add.f r0,r1,1 @@ -60,9 +55,9 @@ add.f r0,r1,512 add.f r0,512,r2 - add.eq.f r0,r1,r2 - add.ne.f r0,r1,0 - add.lt.f r0,0,r2 - add.gt.f 0,r1,r2 - add.le.f r0,r1,512 - add.ge.f r0,512,r2 + add.eq.f r1,r1,r2 + add.ne.f r0,r0,0 + add.lt.f r2,r2,r2 + add.gt.f 0,1,2 + add.le.f 0,512,512 + add.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/alias.d b/gas/testsuite/gas/arc/alias.d deleted file mode 100644 index b51acf63e9..0000000000 --- a/gas/testsuite/gas/arc/alias.d +++ /dev/null @@ -1,68 +0,0 @@ -#objdump: -dr -#name: @OC@ - -# Test the @OC@ insn. - -.*: +file format elf32-.*arc - -Disassembly of section .text: -00000000 @IC+0@008200 @OC@ r0,r1 -00000004 @IC+3@6e3800 @OC@ fp,sp -00000008 @IC+0@1ffe00 @OC@ r0,0 -0000000c @IC+0@3fffff @OC@ r1,-1 -00000010 @IC+7@e10400 @OC@ 0,r2 -00000014 @IC+7@e187ff @OC@ -1,r3 -00000018 @IC+0@9ffeff @OC@ r4,255 -0000001c @IC+7@e28aff @OC@ 255,r5 -00000020 @IC+0@dfff00 @OC@ r6,-256 -00000024 @IC+7@e38f00 @OC@ -256,r7 -00000028 @IC+1@1f7c00 @OC@ r8,256 -00000030 @IC+1@3f7c00 @OC@ r9,-257 -00000038 @IC+7@c51400 @OC@ 511,r10 -00000040 @IC+1@7f7c00 @OC@ r11,1111638594 -00000048 @IC+7@c61800 @OC@ 305419896,r12 -00000050 @IC+7@ff7cff @OC@ 255,256 -00000058 @IC+7@dffeff @OC@ 256,255 -00000060 @IC+0@1f7c00 @OC@ r0,0 - RELOC: 00000064 R_ARC_32 foo -00000068 @IC+0@008200 @OC@ r0,r1 -0000006c @IC+0@620800 @OC@ r3,r4 -00000070 @IC+0@c38e01 @OC@.eq r6,r7 -00000074 @IC+1@251401 @OC@.eq r9,r10 -00000078 @IC+1@869a02 @OC@.ne r12,r13 -0000007c @IC+1@e82002 @OC@.ne r15,r16 -00000080 @IC+2@49a603 @OC@.p r18,r19 -00000084 @IC+2@ab2c03 @OC@.p r21,r22 -00000088 @IC+3@0cb204 @OC@.n r24,r25 -0000008c @IC+3@6e3804 @OC@.n fp,sp -00000090 @IC+3@cfbe05 @OC@.c ilink2,blink -00000094 @IC+4@314405 @OC@.c r33,r34 -00000098 @IC+4@92ca05 @OC@.c r36,r37 -0000009c @IC+4@f45006 @OC@.nc r39,r40 -000000a0 @IC+5@55d606 @OC@.nc r42,r43 -000000a4 @IC+5@b75c06 @OC@.nc r45,r46 -000000a8 @IC+6@18e207 @OC@.v r48,r49 -000000ac @IC+6@7a6807 @OC@.v r51,r52 -000000b0 @IC+6@dbee08 @OC@.nv r54,r55 -000000b4 @IC+7@3d7408 @OC@.nv r57,r58 -000000b8 @IC+7@9e7809 @OC@.gt lp_count,lp_count -000000bc @IC+0@1f7c0a @OC@.ge r0,0 -000000c4 @IC+7@c0820b @OC@.lt 1,r1 -000000cc @IC+7@df7c0c @OC@.le 2,2 -000000d4 @IC+0@61860d @OC@.hi r3,r3 -000000d8 @IC+0@82080e @OC@.ls r4,r4 -000000dc @IC+0@a28a0f @OC@.pnz r5,r5 -000000e0 @IC+0@008300 @OC@.f r0,r1 -000000e4 @IC+0@5efa01 @OC@.f r2,1 -000000e8 @IC+7@a18601 @OC@.f 1,r3 -000000ec @IC+7@a20800 @OC@.f 0,r4 -000000f0 @IC+0@bf7d00 @OC@.f r5,512 -000000f8 @IC+7@c30d00 @OC@.f 512,r6 -00000100 @IC+7@df7d00 @OC@.f 512,512 -00000108 @IC+0@008301 @OC@.eq.f r0,r1 -0000010c @IC+0@3f7d02 @OC@.ne.f r1,0 -00000114 @IC+7@c1050b @OC@.lt.f 0,r2 -0000011c @IC+7@c10509 @OC@.gt.f 1,r2 -00000124 @IC+0@1f7d0c @OC@.le.f r0,512 -0000012c @IC+7@c1050a @OC@.ge.f 512,r2 -00000134 @IC+7@df7d04 @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/alias.s b/gas/testsuite/gas/arc/alias.s deleted file mode 100644 index d524440f98..0000000000 --- a/gas/testsuite/gas/arc/alias.s +++ /dev/null @@ -1,76 +0,0 @@ -# @OC@ test - -# reg,reg - @OC@ r0,r1 - @OC@ fp,sp - -# shimm values - @OC@ r0,0 - @OC@ r1,-1 - @OC@ 0,r2 - @OC@ -1,r3 - @OC@ r4,255 - @OC@ 255,r5 - @OC@ r6,-256 - @OC@ -256,r7 - -# limm values - @OC@ r8,256 - @OC@ r9,-257 - @OC@ 511,r10 - @OC@ r11,0x42424242 - @OC@ 0x12345678,r12 - -# shimm and limm - @OC@ 255,256 - @OC@ 256,255 - -# symbols - @OC@ r0,foo - -# conditional execution - @OC@.al r0,r1 - @OC@.ra r3,r4 - @OC@.eq r6,r7 - @OC@.z r9,r10 - @OC@.ne r12,r13 - @OC@.nz r15,r16 - @OC@.pl r18,r19 - @OC@.p r21,r22 - @OC@.mi r24,r25 - @OC@.n r27,r28 - @OC@.cs r30,r31 - @OC@.c r33,r34 - @OC@.lo r36,r37 - @OC@.cc r39,r40 - @OC@.nc r42,r43 - @OC@.hs r45,r46 - @OC@.vs r48,r49 - @OC@.v r51,r52 - @OC@.vc r54,r55 - @OC@.nv r57,r58 - @OC@.gt r60,r60 - @OC@.ge r0,0 - @OC@.lt 1,r1 - @OC@.le 2,2 - @OC@.hi r3,r3 - @OC@.ls r4,r4 - @OC@.pnz r5,r5 - -# flag setting - @OC@.f r0,r1 - @OC@.f r2,1 - @OC@.f 1,r3 - @OC@.f 0,r4 - @OC@.f r5,512 - @OC@.f 512,r6 - @OC@.f 512,512 - -# conditional execution + flag setting - @OC@.eq.f r0,r1 - @OC@.ne.f r1,0 - @OC@.lt.f 0,r2 - @OC@.gt.f 1,r2 - @OC@.le.f r0,512 - @OC@.ge.f 512,r2 - @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/and.d b/gas/testsuite/gas/arc/and.d index 5fca082a16..94b3c4d8e1 100644 --- a/gas/testsuite/gas/arc/and.d +++ b/gas/testsuite/gas/arc/and.d @@ -1,85 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 84 00 60 60008400 and r0,r1,r2 - 4: 00 b8 4d 63 634db800 and gp,fp,sp - 8: 00 3e af 63 63af3e00 and ilink1,ilink2,blink - c: 00 f8 1d 67 671df800 and r56,r59,lp_count - 10: 00 fe 00 60 6000fe00 and r0,r1,0 - 14: 00 84 1f 60 601f8400 and r0,0,r2 - 18: 00 84 e0 67 67e08400 and 0,r1,r2 - 1c: ff ff 00 60 6000ffff and r0,r1,-1 - 20: ff 85 1f 60 601f85ff and r0,-1,r2 - 24: 00 84 e0 67 67e08400 and 0,r1,r2 - 28: ff fe 00 60 6000feff and r0,r1,255 - 2c: ff 84 1f 60 601f84ff and r0,255,r2 - 30: 00 84 e0 67 67e08400 and 0,r1,r2 - 34: 00 ff 00 60 6000ff00 and r0,r1,-256 - 38: 00 85 1f 60 601f8500 and r0,-256,r2 - 3c: 00 84 e0 67 67e08400 and 0,r1,r2 - 40: 00 fc 00 60 6000fc00 and r0,r1,0x100 - 44: 00 01 00 00 - 48: 00 04 1f 60 601f0400 and r0,0xffff_feff,r2 - 4c: ff fe ff ff - 50: ff fc 1f 60 601ffcff and r0,255,0x100 - 54: 00 01 00 00 - 58: ff 7e 1f 60 601f7eff and r0,0x100,255 - 5c: 00 01 00 00 - 60: 00 fc 00 60 6000fc00 and r0,r1,0 - 64: 00 00 00 00 - 64: R_ARC_32 foo - 68: 00 84 00 60 60008400 and r0,r1,r2 - 6c: 00 0a 62 60 60620a00 and r3,r4,r5 - 70: 01 90 c3 60 60c39001 and.z r6,r7,r8 - 74: 01 16 25 61 61251601 and.z r9,r10,r11 - 78: 02 9c 86 61 61869c02 and.nz r12,r13,r14 - 7c: 02 22 e8 61 61e82202 and.nz r15,r16,r17 - 80: 03 a8 49 62 6249a803 and.p r18,r19,r20 - 84: 03 2e ab 62 62ab2e03 and.p r21,r22,r23 - 88: 04 b4 0c 63 630cb404 and.n r24,r25,gp - 8c: 04 3a 6e 63 636e3a04 and.n fp,sp,ilink1 - 90: 05 c0 cf 63 63cfc005 and.c ilink2,blink,r32 - 94: 05 46 31 64 64314605 and.c r33,r34,r35 - 98: 05 cc 92 64 6492cc05 and.c r36,r37,r38 - 9c: 06 52 f4 64 64f45206 and.nc r39,r40,r41 - a0: 06 d8 55 65 6555d806 and.nc r42,r43,r44 - a4: 06 5e b7 65 65b75e06 and.nc r45,r46,r47 - a8: 07 e4 18 66 6618e407 and.v r48,r49,r50 - ac: 07 6a 1a 67 671a6a07 and.v r56,r52,r53 - b0: 08 f0 1b 67 671bf008 and.nv r56,r55,r56 - b4: 08 76 1d 67 671d7608 and.nv r56,r58,r59 - b8: 09 00 9e 67 679e0009 and.gt lp_count,lp_count,r0 - bc: 0a 7c 00 60 60007c0a and.ge r0,r0,0 - c0: 00 00 00 00 - c4: 0b 02 3f 60 603f020b and.lt r1,1,r1 - c8: 01 00 00 00 - cc: 0d 06 7f 60 607f060d and.hi r3,3,r3 - d0: 03 00 00 00 - d4: 0e 08 df 67 67df080e and.ls 0,4,r4 - d8: 04 00 00 00 - dc: 0f fc c2 67 67c2fc0f and.pnz 0,r5,5 - e0: 05 00 00 00 - e4: 00 85 00 60 60008500 and.f r0,r1,r2 - e8: 01 fa 00 60 6000fa01 and.f r0,r1,1 - ec: 01 84 1e 60 601e8401 and.f r0,1,r2 - f0: 00 85 e0 67 67e08500 and.f 0,r1,r2 - f4: 00 fd 00 60 6000fd00 and.f r0,r1,0x200 - f8: 00 02 00 00 - fc: 00 05 1f 60 601f0500 and.f r0,0x200,r2 - 100: 00 02 00 00 - 104: 01 85 00 60 60008501 and.z.f r0,r1,r2 - 108: 02 fd 00 60 6000fd02 and.nz.f r0,r1,0 - 10c: 00 00 00 00 - 110: 0b 05 1f 60 601f050b and.lt.f r0,0,r2 - 114: 00 00 00 00 - 118: 09 85 c0 67 67c08509 and.gt.f 0,r1,r2 - 11c: 00 00 00 00 00000000 - 120: 0c fd 00 60 6000fd0c and.le.f r0,r1,0x200 - 124: 00 02 00 00 - 128: 0a 05 1f 60 601f050a and.ge.f r0,0x200,r2 - 12c: 00 02 00 00 +0x[0-9a-f]+ 2104 0080 and r0,r1,r2 +0x[0-9a-f]+ 2304 371a and gp,fp,sp +0x[0-9a-f]+ 2604 37dd and ilink,r30,blink +0x[0-9a-f]+ 2144 0000 and r0,r1,0 +0x[0-9a-f]+ 2604 7080 0000 0000 and r0,0,r2 +0x[0-9a-f]+ 2104 00be and 0,r1,r2 +0x[0-9a-f]+ 2104 0f80 ffff ffff and r0,r1,0xffffffff +0x[0-9a-f]+ 2604 7080 ffff ffff and r0,0xffffffff,r2 +0x[0-9a-f]+ 2104 0f80 0000 00ff and r0,r1,0xff +0x[0-9a-f]+ 2604 7080 0000 00ff and r0,0xff,r2 +0x[0-9a-f]+ 2104 0f80 ffff ff00 and r0,r1,0xffffff00 +0x[0-9a-f]+ 2604 7080 ffff ff00 and r0,0xffffff00,r2 +0x[0-9a-f]+ 2104 0f80 0000 0100 and r0,r1,0x100 +0x[0-9a-f]+ 2604 7080 ffff feff and r0,0xfffffeff,r2 +0x[0-9a-f]+ 2604 7f80 0000 0100 and r0,0x100,0x100 +0x[0-9a-f]+ 2104 0f80 0000 0000 and r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 20c4 0080 and r0,r0,r2 +0x[0-9a-f]+ 23c4 0140 and r3,r3,r5 +0x[0-9a-f]+ 26c4 0201 and.eq r6,r6,r8 +0x[0-9a-f]+ 21c4 12c1 and.eq r9,r9,r11 +0x[0-9a-f]+ 24c4 1382 and.ne r12,r12,r14 +0x[0-9a-f]+ 27c4 1442 and.ne r15,r15,r17 +0x[0-9a-f]+ 22c4 2503 and.p r18,r18,r20 +0x[0-9a-f]+ 25c4 25c3 and.p r21,r21,r23 +0x[0-9a-f]+ 20c4 3684 and.n r24,r24,gp +0x[0-9a-f]+ 23c4 3744 and.n fp,fp,ilink +0x[0-9a-f]+ 26c4 37c5 and.c r30,r30,blink +0x[0-9a-f]+ 23c4 00c5 and.c r3,r3,r3 +0x[0-9a-f]+ 23c4 0205 and.c r3,r3,r8 +0x[0-9a-f]+ 23c4 0106 and.nc r3,r3,r4 +0x[0-9a-f]+ 24c4 0106 and.nc r4,r4,r4 +0x[0-9a-f]+ 24c4 01c6 and.nc r4,r4,r7 +0x[0-9a-f]+ 24c4 0147 and.v r4,r4,r5 +0x[0-9a-f]+ 25c4 0147 and.v r5,r5,r5 +0x[0-9a-f]+ 25c4 0148 and.nv r5,r5,r5 +0x[0-9a-f]+ 25c4 0148 and.nv r5,r5,r5 +0x[0-9a-f]+ 26c4 0009 and.gt r6,r6,r0 +0x[0-9a-f]+ 20c4 002a and.ge r0,r0,0 +0x[0-9a-f]+ 21c4 006b and.lt r1,r1,0x1 +0x[0-9a-f]+ 23c4 00ed and.hi r3,r3,0x3 +0x[0-9a-f]+ 24c4 012e and.ls r4,r4,0x4 +0x[0-9a-f]+ 25c4 016f and.pnz r5,r5,0x5 +0x[0-9a-f]+ 2104 8080 and.f r0,r1,r2 +0x[0-9a-f]+ 2144 8040 and.f r0,r1,0x1 +0x[0-9a-f]+ 2604 f080 0000 0001 and.f r0,0x1,r2 +0x[0-9a-f]+ 2104 80be and.f 0,r1,r2 +0x[0-9a-f]+ 2104 8f80 0000 0200 and.f r0,r1,0x200 +0x[0-9a-f]+ 2604 f080 0000 0200 and.f r0,0x200,r2 +0x[0-9a-f]+ 21c4 8081 and.f.eq r1,r1,r2 +0x[0-9a-f]+ 20c4 8022 and.f.ne r0,r0,0 +0x[0-9a-f]+ 22c4 808b and.f.lt r2,r2,r2 +0x[0-9a-f]+ 26c4 f0a9 0000 0001 and.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 26c4 ff8c 0000 0200 and.f.le 0,0x200,0x200 +0x[0-9a-f]+ 26c4 f0aa 0000 0200 and.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/and.s b/gas/testsuite/gas/arc/and.s index ddd786566e..ecd11d514b 100644 --- a/gas/testsuite/gas/arc/and.s +++ b/gas/testsuite/gas/arc/and.s @@ -3,55 +3,50 @@ and r0,r1,r2 and r26,fp,sp and ilink1,ilink2,blink - and r56,r59,lp_count and r0,r1,0 and r0,0,r2 and 0,r1,r2 and r0,r1,-1 and r0,-1,r2 - and -1,r1,r2 and r0,r1,255 and r0,255,r2 - and 255,r1,r2 and r0,r1,-256 and r0,-256,r2 - and -256,r1,r2 and r0,r1,256 and r0,-257,r2 - and r0,255,256 - and r0,256,255 + and r0,256,256 and r0,r1,foo - and.al r0,r1,r2 - and.ra r3,r4,r5 - and.eq r6,r7,r8 - and.z r9,r10,r11 - and.ne r12,r13,r14 - and.nz r15,r16,r17 - and.pl r18,r19,r20 - and.p r21,r22,r23 - and.mi r24,r25,r26 - and.n r27,r28,r29 - and.cs r30,r31,r32 - and.c r33,r34,r35 - and.lo r36,r37,r38 - and.cc r39,r40,r41 - and.nc r42,r43,r44 - and.hs r45,r46,r47 - and.vs r48,r49,r50 - and.v r56,r52,r53 - and.vc r56,r55,r56 - and.nv r56,r58,r59 - and.gt r60,r60,r0 + and.al r0,r0,r2 + and.ra r3,r3,r5 + and.eq r6,r6,r8 + and.z r9,r9,r11 + and.ne r12,r12,r14 + and.nz r15,r15,r17 + and.pl r18,r18,r20 + and.p r21,r21,r23 + and.mi r24,r24,r26 + and.n r27,r27,r29 + and.cs r30,r30,r31 + and.c r3,r3,r3 + and.lo r3,r3,r8 + and.cc r3,r3,r4 + and.nc r4,r4,r4 + and.hs r4,r4,r7 + and.vs r4,r4,r5 + and.v r5,r5,r5 + and.vc r5,r5,r5 + and.nv r5,r5,r5 + and.gt r6,r6,r0 and.ge r0,r0,0 - and.lt r1,1,r1 - and.hi r3,3,r3 - and.ls 4,4,r4 - and.pnz 5,r5,5 + and.lt r1,r1,1 + and.hi r3,r3,3 + and.ls r4,r4,4 + and.pnz r5,r5,5 and.f r0,r1,r2 and.f r0,r1,1 @@ -60,9 +55,9 @@ and.f r0,r1,512 and.f r0,512,r2 - and.eq.f r0,r1,r2 - and.ne.f r0,r1,0 - and.lt.f r0,0,r2 - and.gt.f 0,r1,r2 - and.le.f r0,r1,512 - and.ge.f r0,512,r2 + and.eq.f r1,r1,r2 + and.ne.f r0,r0,0 + and.lt.f r2,r2,r2 + and.gt.f 0,1,2 + and.le.f 0,512,512 + and.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/arc.exp b/gas/testsuite/gas/arc/arc.exp index 44d82d435d..7951744960 100644 --- a/gas/testsuite/gas/arc/arc.exp +++ b/gas/testsuite/gas/arc/arc.exp @@ -4,59 +4,19 @@ # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 3 of the License, or # (at your option) any later version. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. -# ARC base instruction set (to arc8) -if [istarget arc*-*-*] then { - run_dump_test ld - run_dump_test ld2 - run_dump_test st - - # Specially encoded/single operand instructions - run_dump_test flag - run_dump_test brk - run_dump_test sleep - run_dump_test swi - run_dump_test asr - run_dump_test lsr - run_dump_test ror - run_dump_test rrc - run_dump_test sexb - run_dump_test sexw - run_dump_test extb - run_dump_test extw - - run_dump_test b - run_dump_test bl - run_dump_test lp - run_dump_test j - run_dump_test jl - run_dump_test add - run_dump_test asl - # FIXME: ??? `lsl' gets dumped as `asl' - # run_dump_test lsl - run_dump_test adc - run_dump_test rlc - run_dump_test sub - run_dump_test sbc - run_dump_test and - run_dump_test mov - run_dump_test or - run_dump_test bic - run_dump_test xor - run_dump_test nop - run_dump_test extensions -} +# ARC base instruction set # ARC library extensions if [istarget arc*-*-*] then { - # *TODO* + run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]] } diff --git a/gas/testsuite/gas/arc/asl.d b/gas/testsuite/gas/arc/asl.d index 89aea0e4f2..f27a671076 100644 --- a/gas/testsuite/gas/arc/asl.d +++ b/gas/testsuite/gas/arc/asl.d @@ -1,68 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 82 00 40 40008200 asl r0,r1 - 4: 00 38 6e 43 436e3800 asl fp,sp - 8: 00 fe 1f 40 401ffe00 asl r0,0 - c: ff ff 3f 40 403fffff asl r1,-1 - 10: 00 04 e1 47 47e10400 asl 0,r2 - 14: 00 86 e1 47 47e18600 asl 0,r3 - 18: ff fe 9f 40 409ffeff asl r4,255 - 1c: 00 8a e2 47 47e28a00 asl 0,r5 - 20: 00 ff df 40 40dfff00 asl r6,-256 - 24: 00 8e e3 47 47e38e00 asl 0,r7 - 28: 00 7c 1f 41 411f7c00 asl r8,0x100 - 2c: 00 01 00 00 - 30: 00 7c 3f 41 413f7c00 asl r9,0xffff_feff - 34: ff fe ff ff - 38: 00 7c 7f 41 417f7c00 asl r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 7c ff 47 47ff7c00 asl 0,0x100 - 44: 00 01 00 00 - 48: 00 7c 1f 40 401f7c00 asl r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 00 82 00 40 40008200 asl r0,r1 - 54: 00 08 62 40 40620800 asl r3,r4 - 58: 01 8e c3 40 40c38e01 asl.z r6,r7 - 5c: 01 14 25 41 41251401 asl.z r9,r10 - 60: 02 9a 86 41 41869a02 asl.nz r12,r13 - 64: 02 20 e8 41 41e82002 asl.nz r15,r16 - 68: 03 a6 49 42 4249a603 asl.p r18,r19 - 6c: 03 2c ab 42 42ab2c03 asl.p r21,r22 - 70: 04 b2 0c 43 430cb204 asl.n r24,r25 - 74: 04 38 6e 43 436e3804 asl.n fp,sp - 78: 05 be cf 43 43cfbe05 asl.c ilink2,blink - 7c: 05 44 31 44 44314405 asl.c r33,r34 - 80: 05 ca 92 44 4492ca05 asl.c r36,r37 - 84: 06 50 f4 44 44f45006 asl.nc r39,r40 - 88: 06 d6 55 45 4555d606 asl.nc r42,r43 - 8c: 06 5c b7 45 45b75c06 asl.nc r45,r46 - 90: 07 e2 18 46 4618e207 asl.v r48,r49 - 94: 07 64 39 46 46396407 asl.v r49,r50 - 98: 08 ee 3b 46 463bee08 asl.nv r49,r55 - 9c: 08 74 3d 46 463d7408 asl.nv r49,r58 - a0: 09 78 9e 47 479e7809 asl.gt lp_count,lp_count - a4: 0a 7c 1f 40 401f7c0a asl.ge r0,0 - a8: 00 00 00 00 - ac: 0c 7c df 47 47df7c0c asl.le 0,2 - b0: 02 00 00 00 - b4: 0d 86 61 40 4061860d asl.hi r3,r3 - b8: 0e 08 82 40 4082080e asl.ls r4,r4 - bc: 0f 8a a2 40 40a28a0f asl.pnz r5,r5 - c0: 00 83 00 40 40008300 asl.f r0,r1 - c4: 01 fa 5e 40 405efa01 asl.f r2,1 - c8: 00 87 e1 47 47e18700 asl.f 0,r3 - cc: 00 09 e2 47 47e20900 asl.f 0,r4 - d0: 00 7d bf 40 40bf7d00 asl.f r5,0x200 - d4: 00 02 00 00 - d8: 00 7d df 47 47df7d00 asl.f 0,0x200 - dc: 00 02 00 00 - e0: 01 83 00 40 40008301 asl.z.f r0,r1 - e4: 02 7d 3f 40 403f7d02 asl.nz.f r1,0 - e8: 00 00 00 00 +0x[0-9a-f]+ 2900 0080 asl r0,r1,r2 +0x[0-9a-f]+ 2b00 371a asl gp,fp,sp +0x[0-9a-f]+ 2e00 37dd asl ilink,r30,blink +0x[0-9a-f]+ 2940 0000 asl r0,r1,0 +0x[0-9a-f]+ 2e00 7080 0000 0000 asl r0,0,r2 +0x[0-9a-f]+ 2900 00be asl 0,r1,r2 +0x[0-9a-f]+ 2900 0f80 ffff ffff asl r0,r1,0xffffffff +0x[0-9a-f]+ 2e00 7080 ffff ffff asl r0,0xffffffff,r2 +0x[0-9a-f]+ 2900 0f80 0000 00ff asl r0,r1,0xff +0x[0-9a-f]+ 2e00 7080 0000 00ff asl r0,0xff,r2 +0x[0-9a-f]+ 2900 0f80 ffff ff00 asl r0,r1,0xffffff00 +0x[0-9a-f]+ 2e00 7080 ffff ff00 asl r0,0xffffff00,r2 +0x[0-9a-f]+ 2900 0f80 0000 0100 asl r0,r1,0x100 +0x[0-9a-f]+ 2e00 7080 ffff feff asl r0,0xfffffeff,r2 +0x[0-9a-f]+ 2e00 7f80 0000 0100 asl r0,0x100,0x100 +0x[0-9a-f]+ 2900 0f80 0000 0000 asl r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 28c0 0080 asl r0,r0,r2 +0x[0-9a-f]+ 2bc0 0140 asl r3,r3,r5 +0x[0-9a-f]+ 2ec0 0201 asl.eq r6,r6,r8 +0x[0-9a-f]+ 29c0 12c1 asl.eq r9,r9,r11 +0x[0-9a-f]+ 2cc0 1382 asl.ne r12,r12,r14 +0x[0-9a-f]+ 2fc0 1442 asl.ne r15,r15,r17 +0x[0-9a-f]+ 2ac0 2503 asl.p r18,r18,r20 +0x[0-9a-f]+ 2dc0 25c3 asl.p r21,r21,r23 +0x[0-9a-f]+ 28c0 3684 asl.n r24,r24,gp +0x[0-9a-f]+ 2bc0 3744 asl.n fp,fp,ilink +0x[0-9a-f]+ 2ec0 37c5 asl.c r30,r30,blink +0x[0-9a-f]+ 2bc0 00c5 asl.c r3,r3,r3 +0x[0-9a-f]+ 2bc0 0205 asl.c r3,r3,r8 +0x[0-9a-f]+ 2bc0 0106 asl.nc r3,r3,r4 +0x[0-9a-f]+ 2cc0 0106 asl.nc r4,r4,r4 +0x[0-9a-f]+ 2cc0 01c6 asl.nc r4,r4,r7 +0x[0-9a-f]+ 2cc0 0147 asl.v r4,r4,r5 +0x[0-9a-f]+ 2dc0 0147 asl.v r5,r5,r5 +0x[0-9a-f]+ 2dc0 0148 asl.nv r5,r5,r5 +0x[0-9a-f]+ 2dc0 0148 asl.nv r5,r5,r5 +0x[0-9a-f]+ 2ec0 0009 asl.gt r6,r6,r0 +0x[0-9a-f]+ 28c0 002a asl.ge r0,r0,0 +0x[0-9a-f]+ 29c0 006b asl.lt r1,r1,0x1 +0x[0-9a-f]+ 2bc0 00ed asl.hi r3,r3,0x3 +0x[0-9a-f]+ 2cc0 012e asl.ls r4,r4,0x4 +0x[0-9a-f]+ 2dc0 016f asl.pnz r5,r5,0x5 +0x[0-9a-f]+ 2900 8080 asl.f r0,r1,r2 +0x[0-9a-f]+ 2940 8040 asl.f r0,r1,0x1 +0x[0-9a-f]+ 2e00 f080 0000 0001 asl.f r0,0x1,r2 +0x[0-9a-f]+ 2900 80be asl.f 0,r1,r2 +0x[0-9a-f]+ 2900 8f80 0000 0200 asl.f r0,r1,0x200 +0x[0-9a-f]+ 2e00 f080 0000 0200 asl.f r0,0x200,r2 +0x[0-9a-f]+ 29c0 8081 asl.f.eq r1,r1,r2 +0x[0-9a-f]+ 28c0 8022 asl.f.ne r0,r0,0 +0x[0-9a-f]+ 2ac0 808b asl.f.lt r2,r2,r2 +0x[0-9a-f]+ 2ec0 f0a9 0000 0001 asl.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 2ec0 ff8c 0000 0200 asl.f.le 0,0x200,0x200 +0x[0-9a-f]+ 2ec0 f0aa 0000 0200 asl.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/asl.s b/gas/testsuite/gas/arc/asl.s index f931458477..39c7e12402 100644 --- a/gas/testsuite/gas/arc/asl.s +++ b/gas/testsuite/gas/arc/asl.s @@ -1,58 +1,63 @@ # asl test - asl r0,r1 - asl fp,sp - - asl r0,0 - asl r1,-1 - asl 0,r2 - asl -1,r3 - asl r4,255 - asl 255,r5 - asl r6,-256 - asl -256,r7 - - asl r8,256 - asl r9,-257 - asl r11,0x42424242 - - asl 255,256 - - asl r0,foo - - asl.al r0,r1 - asl.ra r3,r4 - asl.eq r6,r7 - asl.z r9,r10 - asl.ne r12,r13 - asl.nz r15,r16 - asl.pl r18,r19 - asl.p r21,r22 - asl.mi r24,r25 - asl.n r27,r28 - asl.cs r30,r31 - asl.c r33,r34 - asl.lo r36,r37 - asl.cc r39,r40 - asl.nc r42,r43 - asl.hs r45,r46 - asl.vs r48,r49 - asl.v r49,r50 - asl.vc r49,r55 - asl.nv r49,r58 - asl.gt r60,r60 - asl.ge r0,0 - asl.le 2,2 - asl.hi r3,r3 - asl.ls r4,r4 - asl.pnz r5,r5 - - asl.f r0,r1 - asl.f r2,1 - asl.f 1,r3 - asl.f 0,r4 - asl.f r5,512 - asl.f 512,512 - - asl.eq.f r0,r1 - asl.ne.f r1,0 + asl r0,r1,r2 + asl r26,fp,sp + asl ilink1,ilink2,blink + + asl r0,r1,0 + asl r0,0,r2 + asl 0,r1,r2 + asl r0,r1,-1 + asl r0,-1,r2 + asl r0,r1,255 + asl r0,255,r2 + asl r0,r1,-256 + asl r0,-256,r2 + + asl r0,r1,256 + asl r0,-257,r2 + + asl r0,256,256 + + asl r0,r1,foo + + asl.al r0,r0,r2 + asl.ra r3,r3,r5 + asl.eq r6,r6,r8 + asl.z r9,r9,r11 + asl.ne r12,r12,r14 + asl.nz r15,r15,r17 + asl.pl r18,r18,r20 + asl.p r21,r21,r23 + asl.mi r24,r24,r26 + asl.n r27,r27,r29 + asl.cs r30,r30,r31 + asl.c r3,r3,r3 + asl.lo r3,r3,r8 + asl.cc r3,r3,r4 + asl.nc r4,r4,r4 + asl.hs r4,r4,r7 + asl.vs r4,r4,r5 + asl.v r5,r5,r5 + asl.vc r5,r5,r5 + asl.nv r5,r5,r5 + asl.gt r6,r6,r0 + asl.ge r0,r0,0 + asl.lt r1,r1,1 + asl.hi r3,r3,3 + asl.ls r4,r4,4 + asl.pnz r5,r5,5 + + asl.f r0,r1,r2 + asl.f r0,r1,1 + asl.f r0,1,r2 + asl.f 0,r1,r2 + asl.f r0,r1,512 + asl.f r0,512,r2 + + asl.eq.f r1,r1,r2 + asl.ne.f r0,r0,0 + asl.lt.f r2,r2,r2 + asl.gt.f 0,1,2 + asl.le.f 0,512,512 + asl.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/asr.d b/gas/testsuite/gas/arc/asr.d index bb4c96ef95..c94736e15a 100644 --- a/gas/testsuite/gas/arc/asr.d +++ b/gas/testsuite/gas/arc/asr.d @@ -1,51 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 82 00 18 18008200 asr r0,r1 - 4: 00 02 6e 1b 1b6e0200 asr fp,sp - 8: 00 82 1f 18 181f8200 asr r0,0 - c: ff 83 3f 18 183f83ff asr r1,-1 - 10: 00 02 e1 1f 1fe10200 asr 0,r2 - 14: 00 82 e1 1f 1fe18200 asr 0,r3 - 18: ff 82 9f 18 189f82ff asr r4,255 - 1c: 00 82 e2 1f 1fe28200 asr 0,r5 - 20: 00 83 df 18 18df8300 asr r6,-256 - 24: 00 82 e3 1f 1fe38200 asr 0,r7 - 28: 00 02 1f 19 191f0200 asr r8,0x100 - 2c: 00 01 00 00 - 30: 00 02 3f 19 193f0200 asr r9,0xffff_feff - 34: ff fe ff ff - 38: 00 02 7f 19 197f0200 asr r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 02 ff 1f 1fff0200 asr 0,0x100 - 44: 00 01 00 00 - 48: 00 02 1f 18 181f0200 asr r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 01 82 45 19 19458201 asr.z r10,r11 - 54: 02 82 86 19 19868202 asr.nz r12,r13 - 58: 0b 02 df 19 19df020b asr.lt r14,0 - 5c: 00 00 00 00 - 60: 09 02 ff 19 19ff0209 asr.gt r15,0x200 - 64: 00 02 00 00 - 68: 00 83 00 18 18008300 asr.f r0,r1 - 6c: 01 82 5e 18 185e8201 asr.f r2,1 - 70: 00 03 e2 1f 1fe20300 asr.f 0,r4 - 74: 00 03 bf 18 18bf0300 asr.f r5,0x200 - 78: 00 02 00 00 - 7c: 00 03 df 1f 1fdf0300 asr.f 0,0x200 - 80: 00 02 00 00 - 84: 01 83 00 18 18008301 asr.z.f r0,r1 - 88: 02 03 3f 18 183f0302 asr.nz.f r1,0 - 8c: 00 00 00 00 - 90: 0b 03 c1 1f 1fc1030b asr.lt.f 0,r2 - 94: 00 00 00 00 00000000 - 98: 0c 03 1f 18 181f030c asr.le.f r0,0x200 - 9c: 00 02 00 00 - a0: 04 03 df 1f 1fdf0304 asr.n.f 0,0x200 - a4: 00 02 00 00 +0x[0-9a-f]+ 2902 0080 asr r0,r1,r2 +0x[0-9a-f]+ 2b02 371a asr gp,fp,sp +0x[0-9a-f]+ 2e02 37dd asr ilink,r30,blink +0x[0-9a-f]+ 2942 0000 asr r0,r1,0 +0x[0-9a-f]+ 2e02 7080 0000 0000 asr r0,0,r2 +0x[0-9a-f]+ 2902 00be asr 0,r1,r2 +0x[0-9a-f]+ 2902 0f80 ffff ffff asr r0,r1,0xffffffff +0x[0-9a-f]+ 2e02 7080 ffff ffff asr r0,0xffffffff,r2 +0x[0-9a-f]+ 2902 0f80 0000 00ff asr r0,r1,0xff +0x[0-9a-f]+ 2e02 7080 0000 00ff asr r0,0xff,r2 +0x[0-9a-f]+ 2902 0f80 ffff ff00 asr r0,r1,0xffffff00 +0x[0-9a-f]+ 2e02 7080 ffff ff00 asr r0,0xffffff00,r2 +0x[0-9a-f]+ 2902 0f80 0000 0100 asr r0,r1,0x100 +0x[0-9a-f]+ 2e02 7080 ffff feff asr r0,0xfffffeff,r2 +0x[0-9a-f]+ 2e02 7f80 0000 0100 asr r0,0x100,0x100 +0x[0-9a-f]+ 2902 0f80 0000 0000 asr r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 28c2 0080 asr r0,r0,r2 +0x[0-9a-f]+ 2bc2 0140 asr r3,r3,r5 +0x[0-9a-f]+ 2ec2 0201 asr.eq r6,r6,r8 +0x[0-9a-f]+ 29c2 12c1 asr.eq r9,r9,r11 +0x[0-9a-f]+ 2cc2 1382 asr.ne r12,r12,r14 +0x[0-9a-f]+ 2fc2 1442 asr.ne r15,r15,r17 +0x[0-9a-f]+ 2ac2 2503 asr.p r18,r18,r20 +0x[0-9a-f]+ 2dc2 25c3 asr.p r21,r21,r23 +0x[0-9a-f]+ 28c2 3684 asr.n r24,r24,gp +0x[0-9a-f]+ 2bc2 3744 asr.n fp,fp,ilink +0x[0-9a-f]+ 2ec2 37c5 asr.c r30,r30,blink +0x[0-9a-f]+ 2bc2 00c5 asr.c r3,r3,r3 +0x[0-9a-f]+ 2bc2 0205 asr.c r3,r3,r8 +0x[0-9a-f]+ 2bc2 0106 asr.nc r3,r3,r4 +0x[0-9a-f]+ 2cc2 0106 asr.nc r4,r4,r4 +0x[0-9a-f]+ 2cc2 01c6 asr.nc r4,r4,r7 +0x[0-9a-f]+ 2cc2 0147 asr.v r4,r4,r5 +0x[0-9a-f]+ 2dc2 0147 asr.v r5,r5,r5 +0x[0-9a-f]+ 2dc2 0148 asr.nv r5,r5,r5 +0x[0-9a-f]+ 2dc2 0148 asr.nv r5,r5,r5 +0x[0-9a-f]+ 2ec2 0009 asr.gt r6,r6,r0 +0x[0-9a-f]+ 28c2 002a asr.ge r0,r0,0 +0x[0-9a-f]+ 29c2 006b asr.lt r1,r1,0x1 +0x[0-9a-f]+ 2bc2 00ed asr.hi r3,r3,0x3 +0x[0-9a-f]+ 2cc2 012e asr.ls r4,r4,0x4 +0x[0-9a-f]+ 2dc2 016f asr.pnz r5,r5,0x5 +0x[0-9a-f]+ 2902 8080 asr.f r0,r1,r2 +0x[0-9a-f]+ 2942 8040 asr.f r0,r1,0x1 +0x[0-9a-f]+ 2e02 f080 0000 0001 asr.f r0,0x1,r2 +0x[0-9a-f]+ 2902 80be asr.f 0,r1,r2 +0x[0-9a-f]+ 2902 8f80 0000 0200 asr.f r0,r1,0x200 +0x[0-9a-f]+ 2e02 f080 0000 0200 asr.f r0,0x200,r2 +0x[0-9a-f]+ 29c2 8081 asr.f.eq r1,r1,r2 +0x[0-9a-f]+ 28c2 8022 asr.f.ne r0,r0,0 +0x[0-9a-f]+ 2ac2 808b asr.f.lt r2,r2,r2 +0x[0-9a-f]+ 2ec2 f0a9 0000 0001 asr.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 2ec2 ff8c 0000 0200 asr.f.le 0,0x200,0x200 +0x[0-9a-f]+ 2ec2 f0aa 0000 0200 asr.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/asr.s b/gas/testsuite/gas/arc/asr.s index 9998b3498c..999706f0b6 100644 --- a/gas/testsuite/gas/arc/asr.s +++ b/gas/testsuite/gas/arc/asr.s @@ -1,38 +1,63 @@ # asr test - asr r0,r1 - asr fp,sp - - asr r0,0 - asr r1,-1 - asr 0,r2 - asr -1,r3 - asr r4,255 - asr 255,r5 - asr r6,-256 - asr -256,r7 - - asr r8,256 - asr r9,-257 - asr r11,0x42424242 - - asr 255,256 - - asr r0,foo - - asr.eq r10,r11 - asr.ne r12,r13 - asr.lt r14,0 - asr.gt r15,512 - - asr.f r0,r1 - asr.f r2,1 - asr.f 0,r4 - asr.f r5,512 - asr.f 512,512 - - asr.eq.f r0,r1 - asr.ne.f r1,0 - asr.lt.f 0,r2 - asr.le.f r0,512 - asr.n.f 512,512 + asr r0,r1,r2 + asr r26,fp,sp + asr ilink1,ilink2,blink + + asr r0,r1,0 + asr r0,0,r2 + asr 0,r1,r2 + asr r0,r1,-1 + asr r0,-1,r2 + asr r0,r1,255 + asr r0,255,r2 + asr r0,r1,-256 + asr r0,-256,r2 + + asr r0,r1,256 + asr r0,-257,r2 + + asr r0,256,256 + + asr r0,r1,foo + + asr.al r0,r0,r2 + asr.ra r3,r3,r5 + asr.eq r6,r6,r8 + asr.z r9,r9,r11 + asr.ne r12,r12,r14 + asr.nz r15,r15,r17 + asr.pl r18,r18,r20 + asr.p r21,r21,r23 + asr.mi r24,r24,r26 + asr.n r27,r27,r29 + asr.cs r30,r30,r31 + asr.c r3,r3,r3 + asr.lo r3,r3,r8 + asr.cc r3,r3,r4 + asr.nc r4,r4,r4 + asr.hs r4,r4,r7 + asr.vs r4,r4,r5 + asr.v r5,r5,r5 + asr.vc r5,r5,r5 + asr.nv r5,r5,r5 + asr.gt r6,r6,r0 + asr.ge r0,r0,0 + asr.lt r1,r1,1 + asr.hi r3,r3,3 + asr.ls r4,r4,4 + asr.pnz r5,r5,5 + + asr.f r0,r1,r2 + asr.f r0,r1,1 + asr.f r0,1,r2 + asr.f 0,r1,r2 + asr.f r0,r1,512 + asr.f r0,512,r2 + + asr.eq.f r1,r1,r2 + asr.ne.f r0,r0,0 + asr.lt.f r2,r2,r2 + asr.gt.f 0,1,2 + asr.le.f 0,512,512 + asr.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/b.d b/gas/testsuite/gas/arc/b.d index 8c2eb01cc7..87afdc043e 100644 --- a/gas/testsuite/gas/arc/b.d +++ b/gas/testsuite/gas/arc/b.d @@ -1,76 +1,46 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: 00000000 <text_label>: - 0: 80 ff ff 27 27ffff80 b 0 <text_label> - - 4: 00 ff ff 27 27ffff00 b 0 <text_label> - - 8: 80 fe ff 27 27fffe80 b 0 <text_label> - - c: 01 fe ff 27 27fffe01 bz 0 <text_label> - - 10: 81 fd ff 27 27fffd81 bz 0 <text_label> - - 14: 02 fd ff 27 27fffd02 bnz 0 <text_label> - - 18: 82 fc ff 27 27fffc82 bnz 0 <text_label> - - 1c: 03 fc ff 27 27fffc03 bp 0 <text_label> - - 20: 83 fb ff 27 27fffb83 bp 0 <text_label> - - 24: 04 fb ff 27 27fffb04 bn 0 <text_label> - - 28: 84 fa ff 27 27fffa84 bn 0 <text_label> - - 2c: 05 fa ff 27 27fffa05 bc 0 <text_label> - - 30: 85 f9 ff 27 27fff985 bc 0 <text_label> - - 34: 05 f9 ff 27 27fff905 bc 0 <text_label> - - 38: 86 f8 ff 27 27fff886 bnc 0 <text_label> - - 3c: 06 f8 ff 27 27fff806 bnc 0 <text_label> - - 40: 86 f7 ff 27 27fff786 bnc 0 <text_label> - - 44: 07 f7 ff 27 27fff707 bv 0 <text_label> - - 48: 87 f6 ff 27 27fff687 bv 0 <text_label> - - 4c: 08 f6 ff 27 27fff608 bnv 0 <text_label> - - 50: 88 f5 ff 27 27fff588 bnv 0 <text_label> - - 54: 09 f5 ff 27 27fff509 bgt 0 <text_label> - - 58: 8a f4 ff 27 27fff48a bge 0 <text_label> - - 5c: 0b f4 ff 27 27fff40b blt 0 <text_label> - - 60: 8c f3 ff 27 27fff38c ble 0 <text_label> - - 64: 0d f3 ff 27 27fff30d bhi 0 <text_label> - - 68: 8e f2 ff 27 27fff28e bls 0 <text_label> - - 6c: 0f f2 ff 27 27fff20f bpnz 0 <text_label> - - 70: a0 f1 ff 27 27fff1a0 b.d 0 <text_label> - - 74: 00 f1 ff 27 27fff100 b 0 <text_label> - - 78: c0 f0 ff 27 27fff0c0 b.jd 0 <text_label> - - 7c: 21 f0 ff 27 27fff021 bz.d 0 <text_label> - - 80: 82 ef ff 27 27ffef82 bnz 0 <text_label> - - 84: 46 ef ff 27 27ffef46 bnc.jd 0 <text_label> - + 0: 0001 0000 b 0 <text_label> + 4: 07fc ffc0 b -4 + 8: 07f8 ffc0 b -8 + c: 07f4 ffc1 beq -12 + 10: 07f0 ffc1 beq -16 + 14: 07ec ffc2 bne -20 + 18: 07e8 ffc2 bne -24 + 1c: 07e4 ffc3 bp -28 + 20: 07e0 ffc3 bp -32 + 24: 07dc ffc4 bn -36 + 28: 07d8 ffc4 bn -40 + 2c: 07d4 ffc5 bc -44 + 30: 07d0 ffc5 bc -48 + 34: 07cc ffc5 bc -52 + 38: 07c8 ffc6 bnc -56 + 3c: 07c4 ffc6 bnc -60 + 40: 07c0 ffc6 bnc -64 + 44: 07bc ffc7 bv -68 + 48: 07b8 ffc7 bv -72 + 4c: 07b4 ffc8 bnv -76 + 50: 07b0 ffc8 bnv -80 + 54: 07ac ffc9 bgt -84 + 58: 07a8 ffca bge -88 + 5c: 07a4 ffcb blt -92 + 60: 07a0 ffcc ble -96 + 64: 079c ffcd bhi -100 + 68: 0798 ffce bls -104 + 6c: 0794 ffcf bpnz -108 + 70: 0791 ffef b.d 0 <text_label> + 74: 264a 7000 mov 0,0 + 78: 0789 ffcf b 0 <text_label> + 7c: 0785 ffef b.d 0 <text_label> + 80: 264a 7000 mov 0,0 + 84: 077c ffe1 b.deq -132 + 88: 264a 7000 mov 0,0 + 8c: 0774 ffc2 bne -140 + 90: 0770 ffe6 b.dnc -144 + 94: 264a 7000 mov 0,0 diff --git a/gas/testsuite/gas/arc/b.s b/gas/testsuite/gas/arc/b.s index a215fe48bd..0cb7783d3e 100644 --- a/gas/testsuite/gas/arc/b.s +++ b/gas/testsuite/gas/arc/b.s @@ -1,5 +1,5 @@ # b test - + text_label: b text_label @@ -32,9 +32,13 @@ text_label: bpnz text_label b.d text_label + nop b.nd text_label - b.jd text_label + b.d text_label + nop beq.d text_label + nop bne.nd text_label - bcc.jd text_label + bcc.d text_label + nop diff --git a/gas/testsuite/gas/arc/bic.d b/gas/testsuite/gas/arc/bic.d index 5b2a2337ba..348a428a55 100644 --- a/gas/testsuite/gas/arc/bic.d +++ b/gas/testsuite/gas/arc/bic.d @@ -1,85 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 84 00 70 70008400 bic r0,r1,r2 - 4: 00 b8 4d 73 734db800 bic gp,fp,sp - 8: 00 3e af 73 73af3e00 bic ilink1,ilink2,blink - c: 00 f8 1d 77 771df800 bic r56,r59,lp_count - 10: 00 fe 00 70 7000fe00 bic r0,r1,0 - 14: 00 84 1f 70 701f8400 bic r0,0,r2 - 18: 00 84 e0 77 77e08400 bic 0,r1,r2 - 1c: ff ff 00 70 7000ffff bic r0,r1,-1 - 20: ff 85 1f 70 701f85ff bic r0,-1,r2 - 24: 00 84 e0 77 77e08400 bic 0,r1,r2 - 28: ff fe 00 70 7000feff bic r0,r1,255 - 2c: ff 84 1f 70 701f84ff bic r0,255,r2 - 30: 00 84 e0 77 77e08400 bic 0,r1,r2 - 34: 00 ff 00 70 7000ff00 bic r0,r1,-256 - 38: 00 85 1f 70 701f8500 bic r0,-256,r2 - 3c: 00 84 e0 77 77e08400 bic 0,r1,r2 - 40: 00 fc 00 70 7000fc00 bic r0,r1,0x100 - 44: 00 01 00 00 - 48: 00 04 1f 70 701f0400 bic r0,0xffff_feff,r2 - 4c: ff fe ff ff - 50: ff fc 1f 70 701ffcff bic r0,255,0x100 - 54: 00 01 00 00 - 58: ff 7e 1f 70 701f7eff bic r0,0x100,255 - 5c: 00 01 00 00 - 60: 00 fc 00 70 7000fc00 bic r0,r1,0 - 64: 00 00 00 00 - 64: R_ARC_32 foo - 68: 00 84 00 70 70008400 bic r0,r1,r2 - 6c: 00 0a 62 70 70620a00 bic r3,r4,r5 - 70: 01 90 c3 70 70c39001 bic.z r6,r7,r8 - 74: 01 16 25 71 71251601 bic.z r9,r10,r11 - 78: 02 9c 86 71 71869c02 bic.nz r12,r13,r14 - 7c: 02 22 e8 71 71e82202 bic.nz r15,r16,r17 - 80: 03 a8 49 72 7249a803 bic.p r18,r19,r20 - 84: 03 2e ab 72 72ab2e03 bic.p r21,r22,r23 - 88: 04 b4 0c 73 730cb404 bic.n r24,r25,gp - 8c: 04 3a 6e 73 736e3a04 bic.n fp,sp,ilink1 - 90: 05 c0 cf 73 73cfc005 bic.c ilink2,blink,r32 - 94: 05 46 31 74 74314605 bic.c r33,r34,r35 - 98: 05 cc 92 74 7492cc05 bic.c r36,r37,r38 - 9c: 06 52 f4 74 74f45206 bic.nc r39,r40,r41 - a0: 06 d8 55 75 7555d806 bic.nc r42,r43,r44 - a4: 06 5e b7 75 75b75e06 bic.nc r45,r46,r47 - a8: 07 e4 18 76 7618e407 bic.v r48,r49,r50 - ac: 07 6a 1a 77 771a6a07 bic.v r56,r52,r53 - b0: 08 f0 1b 77 771bf008 bic.nv r56,r55,r56 - b4: 08 76 1d 77 771d7608 bic.nv r56,r58,r59 - b8: 09 00 9e 77 779e0009 bic.gt lp_count,lp_count,r0 - bc: 0a 7c 00 70 70007c0a bic.ge r0,r0,0 - c0: 00 00 00 00 - c4: 0b 02 3f 70 703f020b bic.lt r1,1,r1 - c8: 01 00 00 00 - cc: 0d 06 7f 70 707f060d bic.hi r3,3,r3 - d0: 03 00 00 00 - d4: 0e 08 df 77 77df080e bic.ls 0,4,r4 - d8: 04 00 00 00 - dc: 0f fc c2 77 77c2fc0f bic.pnz 0,r5,5 - e0: 05 00 00 00 - e4: 00 85 00 70 70008500 bic.f r0,r1,r2 - e8: 01 fa 00 70 7000fa01 bic.f r0,r1,1 - ec: 01 84 1e 70 701e8401 bic.f r0,1,r2 - f0: 00 85 e0 77 77e08500 bic.f 0,r1,r2 - f4: 00 fd 00 70 7000fd00 bic.f r0,r1,0x200 - f8: 00 02 00 00 - fc: 00 05 1f 70 701f0500 bic.f r0,0x200,r2 - 100: 00 02 00 00 - 104: 01 85 00 70 70008501 bic.z.f r0,r1,r2 - 108: 02 fd 00 70 7000fd02 bic.nz.f r0,r1,0 - 10c: 00 00 00 00 - 110: 0b 05 1f 70 701f050b bic.lt.f r0,0,r2 - 114: 00 00 00 00 - 118: 09 85 c0 77 77c08509 bic.gt.f 0,r1,r2 - 11c: 00 00 00 00 00000000 - 120: 0c fd 00 70 7000fd0c bic.le.f r0,r1,0x200 - 124: 00 02 00 00 - 128: 0a 05 1f 70 701f050a bic.ge.f r0,0x200,r2 - 12c: 00 02 00 00 +0x[0-9a-f]+ 2106 0080 bic r0,r1,r2 +0x[0-9a-f]+ 2306 371a bic gp,fp,sp +0x[0-9a-f]+ 2606 37dd bic ilink,r30,blink +0x[0-9a-f]+ 2146 0000 bic r0,r1,0 +0x[0-9a-f]+ 2606 7080 0000 0000 bic r0,0,r2 +0x[0-9a-f]+ 2106 00be bic 0,r1,r2 +0x[0-9a-f]+ 2106 0f80 ffff ffff bic r0,r1,0xffffffff +0x[0-9a-f]+ 2606 7080 ffff ffff bic r0,0xffffffff,r2 +0x[0-9a-f]+ 2106 0f80 0000 00ff bic r0,r1,0xff +0x[0-9a-f]+ 2606 7080 0000 00ff bic r0,0xff,r2 +0x[0-9a-f]+ 2106 0f80 ffff ff00 bic r0,r1,0xffffff00 +0x[0-9a-f]+ 2606 7080 ffff ff00 bic r0,0xffffff00,r2 +0x[0-9a-f]+ 2106 0f80 0000 0100 bic r0,r1,0x100 +0x[0-9a-f]+ 2606 7080 ffff feff bic r0,0xfffffeff,r2 +0x[0-9a-f]+ 2606 7f80 0000 0100 bic r0,0x100,0x100 +0x[0-9a-f]+ 2106 0f80 0000 0000 bic r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 20c6 0080 bic r0,r0,r2 +0x[0-9a-f]+ 23c6 0140 bic r3,r3,r5 +0x[0-9a-f]+ 26c6 0201 biceq r6,r6,r8 +0x[0-9a-f]+ 21c6 12c1 biceq r9,r9,r11 +0x[0-9a-f]+ 24c6 1382 bicne r12,r12,r14 +0x[0-9a-f]+ 27c6 1442 bicne r15,r15,r17 +0x[0-9a-f]+ 22c6 2503 bicp r18,r18,r20 +0x[0-9a-f]+ 25c6 25c3 bicp r21,r21,r23 +0x[0-9a-f]+ 20c6 3684 bicn r24,r24,gp +0x[0-9a-f]+ 23c6 3744 bicn fp,fp,ilink +0x[0-9a-f]+ 26c6 37c5 bicc r30,r30,blink +0x[0-9a-f]+ 23c6 00c5 bicc r3,r3,r3 +0x[0-9a-f]+ 23c6 0205 bicc r3,r3,r8 +0x[0-9a-f]+ 23c6 0106 bicnc r3,r3,r4 +0x[0-9a-f]+ 24c6 0106 bicnc r4,r4,r4 +0x[0-9a-f]+ 24c6 01c6 bicnc r4,r4,r7 +0x[0-9a-f]+ 24c6 0147 bicv r4,r4,r5 +0x[0-9a-f]+ 25c6 0147 bicv r5,r5,r5 +0x[0-9a-f]+ 25c6 0148 bicnv r5,r5,r5 +0x[0-9a-f]+ 25c6 0148 bicnv r5,r5,r5 +0x[0-9a-f]+ 26c6 0009 bicgt r6,r6,r0 +0x[0-9a-f]+ 20c6 002a bicge r0,r0,0 +0x[0-9a-f]+ 21c6 006b biclt r1,r1,0x1 +0x[0-9a-f]+ 23c6 00ed bichi r3,r3,0x3 +0x[0-9a-f]+ 24c6 012e bicls r4,r4,0x4 +0x[0-9a-f]+ 25c6 016f bicpnz r5,r5,0x5 +0x[0-9a-f]+ 2106 8080 bic.f r0,r1,r2 +0x[0-9a-f]+ 2146 8040 bic.f r0,r1,0x1 +0x[0-9a-f]+ 2606 f080 0000 0001 bic.f r0,0x1,r2 +0x[0-9a-f]+ 2106 80be bic.f 0,r1,r2 +0x[0-9a-f]+ 2106 8f80 0000 0200 bic.f r0,r1,0x200 +0x[0-9a-f]+ 2606 f080 0000 0200 bic.f r0,0x200,r2 +0x[0-9a-f]+ 21c6 8081 bic.feq r1,r1,r2 +0x[0-9a-f]+ 20c6 8022 bic.fne r0,r0,0 +0x[0-9a-f]+ 22c6 808b bic.flt r2,r2,r2 +0x[0-9a-f]+ 26c6 f0a9 0000 0001 bic.fgt 0,0x1,0x2 +0x[0-9a-f]+ 26c6 ff8c 0000 0200 bic.fle 0,0x200,0x200 +0x[0-9a-f]+ 26c6 f0aa 0000 0200 bic.fge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/bic.s b/gas/testsuite/gas/arc/bic.s index fc5eb199de..0e10e203fb 100644 --- a/gas/testsuite/gas/arc/bic.s +++ b/gas/testsuite/gas/arc/bic.s @@ -3,55 +3,50 @@ bic r0,r1,r2 bic r26,fp,sp bic ilink1,ilink2,blink - bic r56,r59,lp_count bic r0,r1,0 bic r0,0,r2 bic 0,r1,r2 bic r0,r1,-1 bic r0,-1,r2 - bic -1,r1,r2 bic r0,r1,255 bic r0,255,r2 - bic 255,r1,r2 bic r0,r1,-256 bic r0,-256,r2 - bic -256,r1,r2 bic r0,r1,256 bic r0,-257,r2 - bic r0,255,256 - bic r0,256,255 + bic r0,256,256 bic r0,r1,foo - bic.al r0,r1,r2 - bic.ra r3,r4,r5 - bic.eq r6,r7,r8 - bic.z r9,r10,r11 - bic.ne r12,r13,r14 - bic.nz r15,r16,r17 - bic.pl r18,r19,r20 - bic.p r21,r22,r23 - bic.mi r24,r25,r26 - bic.n r27,r28,r29 - bic.cs r30,r31,r32 - bic.c r33,r34,r35 - bic.lo r36,r37,r38 - bic.cc r39,r40,r41 - bic.nc r42,r43,r44 - bic.hs r45,r46,r47 - bic.vs r48,r49,r50 - bic.v r56,r52,r53 - bic.vc r56,r55,r56 - bic.nv r56,r58,r59 - bic.gt r60,r60,r0 + bic.al r0,r0,r2 + bic.ra r3,r3,r5 + bic.eq r6,r6,r8 + bic.z r9,r9,r11 + bic.ne r12,r12,r14 + bic.nz r15,r15,r17 + bic.pl r18,r18,r20 + bic.p r21,r21,r23 + bic.mi r24,r24,r26 + bic.n r27,r27,r29 + bic.cs r30,r30,r31 + bic.c r3,r3,r3 + bic.lo r3,r3,r8 + bic.cc r3,r3,r4 + bic.nc r4,r4,r4 + bic.hs r4,r4,r7 + bic.vs r4,r4,r5 + bic.v r5,r5,r5 + bic.vc r5,r5,r5 + bic.nv r5,r5,r5 + bic.gt r6,r6,r0 bic.ge r0,r0,0 - bic.lt r1,1,r1 - bic.hi r3,3,r3 - bic.ls 4,4,r4 - bic.pnz 5,r5,5 + bic.lt r1,r1,1 + bic.hi r3,r3,3 + bic.ls r4,r4,4 + bic.pnz r5,r5,5 bic.f r0,r1,r2 bic.f r0,r1,1 @@ -60,9 +55,9 @@ bic.f r0,r1,512 bic.f r0,512,r2 - bic.eq.f r0,r1,r2 - bic.ne.f r0,r1,0 - bic.lt.f r0,0,r2 - bic.gt.f 0,r1,r2 - bic.le.f r0,r1,512 - bic.ge.f r0,512,r2 + bic.eq.f r1,r1,r2 + bic.ne.f r0,r0,0 + bic.lt.f r2,r2,r2 + bic.gt.f 0,1,2 + bic.le.f 0,512,512 + bic.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/bl.d b/gas/testsuite/gas/arc/bl.d index 0cc19db182..3967275047 100644 --- a/gas/testsuite/gas/arc/bl.d +++ b/gas/testsuite/gas/arc/bl.d @@ -1,76 +1,46 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: -00000000 <text_label>: - 0: 80 ff ff 2f 2fffff80 bl 0 <text_label> - - 4: 00 ff ff 2f 2fffff00 bl 0 <text_label> - - 8: 80 fe ff 2f 2ffffe80 bl 0 <text_label> - - c: 01 fe ff 2f 2ffffe01 blz 0 <text_label> - - 10: 81 fd ff 2f 2ffffd81 blz 0 <text_label> - - 14: 02 fd ff 2f 2ffffd02 blnz 0 <text_label> - - 18: 82 fc ff 2f 2ffffc82 blnz 0 <text_label> - - 1c: 03 fc ff 2f 2ffffc03 blp 0 <text_label> - - 20: 83 fb ff 2f 2ffffb83 blp 0 <text_label> - - 24: 04 fb ff 2f 2ffffb04 bln 0 <text_label> - - 28: 84 fa ff 2f 2ffffa84 bln 0 <text_label> - - 2c: 05 fa ff 2f 2ffffa05 blc 0 <text_label> - - 30: 85 f9 ff 2f 2ffff985 blc 0 <text_label> - - 34: 05 f9 ff 2f 2ffff905 blc 0 <text_label> - - 38: 86 f8 ff 2f 2ffff886 blnc 0 <text_label> - - 3c: 06 f8 ff 2f 2ffff806 blnc 0 <text_label> - - 40: 86 f7 ff 2f 2ffff786 blnc 0 <text_label> - - 44: 07 f7 ff 2f 2ffff707 blv 0 <text_label> - - 48: 87 f6 ff 2f 2ffff687 blv 0 <text_label> - - 4c: 08 f6 ff 2f 2ffff608 blnv 0 <text_label> - - 50: 88 f5 ff 2f 2ffff588 blnv 0 <text_label> - - 54: 09 f5 ff 2f 2ffff509 blgt 0 <text_label> - - 58: 8a f4 ff 2f 2ffff48a blge 0 <text_label> - - 5c: 0b f4 ff 2f 2ffff40b bllt 0 <text_label> - - 60: 8c f3 ff 2f 2ffff38c blle 0 <text_label> - - 64: 0d f3 ff 2f 2ffff30d blhi 0 <text_label> - - 68: 8e f2 ff 2f 2ffff28e blls 0 <text_label> - - 6c: 0f f2 ff 2f 2ffff20f blpnz 0 <text_label> - - 70: a0 f1 ff 2f 2ffff1a0 bl.d 0 <text_label> - - 74: 00 f1 ff 2f 2ffff100 bl 0 <text_label> - - 78: c0 f0 ff 2f 2ffff0c0 bl.jd 0 <text_label> - - 7c: 21 f0 ff 2f 2ffff021 blz.d 0 <text_label> - - 80: 82 ef ff 2f 2fffef82 blnz 0 <text_label> - - 84: 46 ef ff 2f 2fffef46 blnc.jd 0 <text_label> - +[0-9a-f]+ <text_label>: + 0: 0802 0000 bl 0 <text_label> + 4: 0ffc ffc0 bl 0 <text_label> + 8: 0ff8 ffc0 bl 0 <text_label> + c: 0ff4 ffc1 bleq 0 <text_label> + 10: 0ff0 ffc1 bleq 0 <text_label> + 14: 0fec ffc2 blne 0 <text_label> + 18: 0fe8 ffc2 blne 0 <text_label> + 1c: 0fe4 ffc3 blp 0 <text_label> + 20: 0fe0 ffc3 blp 0 <text_label> + 24: 0fdc ffc4 bln 0 <text_label> + 28: 0fd8 ffc4 bln 0 <text_label> + 2c: 0fd4 ffc5 blc 0 <text_label> + 30: 0fd0 ffc5 blc 0 <text_label> + 34: 0fcc ffc5 blc 0 <text_label> + 38: 0fc8 ffc6 blnc 0 <text_label> + 3c: 0fc4 ffc6 blnc 0 <text_label> + 40: 0fc0 ffc6 blnc 0 <text_label> + 44: 0fbc ffc7 blv 0 <text_label> + 48: 0fb8 ffc7 blv 0 <text_label> + 4c: 0fb4 ffc8 blnv 0 <text_label> + 50: 0fb0 ffc8 blnv 0 <text_label> + 54: 0fac ffc9 blgt 0 <text_label> + 58: 0fa8 ffca blge 0 <text_label> + 5c: 0fa4 ffcb bllt 0 <text_label> + 60: 0fa0 ffcc blle 0 <text_label> + 64: 0f9c ffcd blhi 0 <text_label> + 68: 0f98 ffce blls 0 <text_label> + 6c: 0f94 ffcf blpnz 0 <text_label> + 70: 0f92 ffef bl.d 0 <text_label> + 74: 78e0 nop_s + 76: 0f8e ffcf bl 0 <text_label> + 7a: 78e0 nop_s + 7c: 0f84 ffe1 bleq.d 0 <text_label> + 80: 78e0 nop_s + 82: 0f80 ffc2 blne 0 <text_label> + 86: 78e0 nop_s + 88: 0f78 ffe6 blnc.d 0 <text_label> + 8c: 78e0 nop_s diff --git a/gas/testsuite/gas/arc/bl.s b/gas/testsuite/gas/arc/bl.s index 8181f39056..b23d65209a 100644 --- a/gas/testsuite/gas/arc/bl.s +++ b/gas/testsuite/gas/arc/bl.s @@ -1,5 +1,5 @@ # bl test - + text_label: bl text_label @@ -32,9 +32,13 @@ text_label: blpnz text_label bl.d text_label + nop_s bl.nd text_label - bl.jd text_label + nop_s bleq.d text_label + nop_s blne.nd text_label - blcc.jd text_label + nop_s + blcc.d text_label + nop_s diff --git a/gas/testsuite/gas/arc/branch.d b/gas/testsuite/gas/arc/branch.d deleted file mode 100644 index 4c9b014b1b..0000000000 --- a/gas/testsuite/gas/arc/branch.d +++ /dev/null @@ -1,45 +0,0 @@ -#objdump: -dr -#name: @OC@ - -# Test the @OC@ insn. - -.*: +file format elf32-.*arc - -Disassembly of section .text: -00000000 <text_label> @IC+7@ffff80 @OC@ 00000000 <text_label> -00000004 <text_label\+4> @IC+7@ffff00 @OC@ 00000000 <text_label> -00000008 <text_label\+8> @IC+7@fffe80 @OC@ 00000000 <text_label> -0000000c <text_label\+c> @IC+7@fffe01 @OC@eq 00000000 <text_label> -00000010 <text_label\+10> @IC+7@fffd81 @OC@eq 00000000 <text_label> -00000014 <text_label\+14> @IC+7@fffd02 @OC@ne 00000000 <text_label> -00000018 <text_label\+18> @IC+7@fffc82 @OC@ne 00000000 <text_label> -0000001c <text_label\+1c> @IC+7@fffc03 @OC@p 00000000 <text_label> -00000020 <text_label\+20> @IC+7@fffb83 @OC@p 00000000 <text_label> -00000024 <text_label\+24> @IC+7@fffb04 @OC@n 00000000 <text_label> -00000028 <text_label\+28> @IC+7@fffa84 @OC@n 00000000 <text_label> -0000002c <text_label\+2c> @IC+7@fffa05 @OC@c 00000000 <text_label> -00000030 <text_label\+30> @IC+7@fff985 @OC@c 00000000 <text_label> -00000034 <text_label\+34> @IC+7@fff905 @OC@c 00000000 <text_label> -00000038 <text_label\+38> @IC+7@fff886 @OC@nc 00000000 <text_label> -0000003c <text_label\+3c> @IC+7@fff806 @OC@nc 00000000 <text_label> -00000040 <text_label\+40> @IC+7@fff786 @OC@nc 00000000 <text_label> -00000044 <text_label\+44> @IC+7@fff707 @OC@v 00000000 <text_label> -00000048 <text_label\+48> @IC+7@fff687 @OC@v 00000000 <text_label> -0000004c <text_label\+4c> @IC+7@fff608 @OC@nv 00000000 <text_label> -00000050 <text_label\+50> @IC+7@fff588 @OC@nv 00000000 <text_label> -00000054 <text_label\+54> @IC+7@fff509 @OC@gt 00000000 <text_label> -00000058 <text_label\+58> @IC+7@fff48a @OC@ge 00000000 <text_label> -0000005c <text_label\+5c> @IC+7@fff40b @OC@lt 00000000 <text_label> -00000060 <text_label\+60> @IC+7@fff38c @OC@le 00000000 <text_label> -00000064 <text_label\+64> @IC+7@fff30d @OC@hi 00000000 <text_label> -00000068 <text_label\+68> @IC+7@fff28e @OC@ls 00000000 <text_label> -0000006c <text_label\+6c> @IC+7@fff20f @OC@pnz 00000000 <text_label> -00000070 <text_label\+70> @IC+7@ffff80 @OC@ 00000070 <text_label\+70> - RELOC: 00000070 R_ARC_B22_PCREL external_text_label -00000074 <text_label\+74> @IC+0@000000 @OC@ 00000078 <text_label\+78> -00000078 <text_label\+78> @IC+7@fff0a0 @OC@.d 00000000 <text_label> -0000007c <text_label\+7c> @IC+7@fff000 @OC@ 00000000 <text_label> -00000080 <text_label\+80> @IC+7@ffefc0 @OC@.jd 00000000 <text_label> -00000084 <text_label\+84> @IC+7@ffef21 @OC@eq.d 00000000 <text_label> -00000088 <text_label\+88> @IC+7@ffee82 @OC@ne 00000000 <text_label> -0000008c <text_label\+8c> @IC+7@ffee46 @OC@nc.jd 00000000 <text_label> diff --git a/gas/testsuite/gas/arc/branch.s b/gas/testsuite/gas/arc/branch.s deleted file mode 100644 index 8bf1618ffc..0000000000 --- a/gas/testsuite/gas/arc/branch.s +++ /dev/null @@ -1,47 +0,0 @@ -# @OC@ test - -text_label: - -# Condition tests - @OC@ text_label - @OC@al text_label - @OC@ra text_label - @OC@eq text_label - @OC@z text_label - @OC@ne text_label - @OC@nz text_label - @OC@pl text_label - @OC@p text_label - @OC@mi text_label - @OC@n text_label - @OC@cs text_label - @OC@c text_label - @OC@lo text_label - @OC@cc text_label - @OC@nc text_label - @OC@hs text_label - @OC@vs text_label - @OC@v text_label - @OC@vc text_label - @OC@nv text_label - @OC@gt text_label - @OC@ge text_label - @OC@lt text_label - @OC@le text_label - @OC@hi text_label - @OC@ls text_label - @OC@pnz text_label - - @OC@ external_text_label - - @OC@ 0 - -# Delay slots - @OC@.d text_label - @OC@.nd text_label - @OC@.jd text_label - -# Condition tests and delay slots - @OC@eq.d text_label - @OC@ne.nd text_label - @OC@cc.jd text_label diff --git a/gas/testsuite/gas/arc/brk.d b/gas/testsuite/gas/arc/brk.d index 70f9e4f265..9a488633e2 100644 --- a/gas/testsuite/gas/arc/brk.d +++ b/gas/testsuite/gas/arc/brk.d @@ -1,11 +1,9 @@ -#as: -EL -marc7 -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <main>: - 0: 00 84 00 40 40008400 add r0,r1,r2 - 4: 00 fe ff 1f 1ffffe00 brk - 8: 00 0a 62 50 50620a00 sub r3,r4,r5 +0x00000000 2100 0080 add r0,r1,r2 +0x00000004 256f 003f brk +0x00000008 2402 0143 sub r3,r4,r5 diff --git a/gas/testsuite/gas/arc/brk.s b/gas/testsuite/gas/arc/brk.s index 00b0761538..cd3202e718 100644 --- a/gas/testsuite/gas/arc/brk.s +++ b/gas/testsuite/gas/arc/brk.s @@ -1,7 +1,5 @@ # brk test -main: - - add r0,r1,r2 + add r0,r1,r2 brk sub r3,r4,r5 diff --git a/gas/testsuite/gas/arc/extb.d b/gas/testsuite/gas/arc/extb.d index 1ceca8a63a..6884d9d73a 100644 --- a/gas/testsuite/gas/arc/extb.d +++ b/gas/testsuite/gas/arc/extb.d @@ -1,51 +1,22 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 8e 00 18 18008e00 extb r0,r1 - 4: 00 0e 6e 1b 1b6e0e00 extb fp,sp - 8: 00 8e 1f 18 181f8e00 extb r0,0 - c: ff 8f 3f 18 183f8fff extb r1,-1 - 10: 00 0e e1 1f 1fe10e00 extb 0,r2 - 14: 00 8e e1 1f 1fe18e00 extb 0,r3 - 18: ff 8e 9f 18 189f8eff extb r4,255 - 1c: 00 8e e2 1f 1fe28e00 extb 0,r5 - 20: 00 8f df 18 18df8f00 extb r6,-256 - 24: 00 8e e3 1f 1fe38e00 extb 0,r7 - 28: 00 0e 1f 19 191f0e00 extb r8,0x100 - 2c: 00 01 00 00 - 30: 00 0e 3f 19 193f0e00 extb r9,0xffff_feff - 34: ff fe ff ff - 38: 00 0e 7f 19 197f0e00 extb r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 0e ff 1f 1fff0e00 extb 0,0x100 - 44: 00 01 00 00 - 48: 00 0e 1f 18 181f0e00 extb r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 01 8e 45 19 19458e01 extb.z r10,r11 - 54: 02 8e 86 19 19868e02 extb.nz r12,r13 - 58: 0b 0e df 19 19df0e0b extb.lt r14,0 - 5c: 00 00 00 00 - 60: 09 0e ff 19 19ff0e09 extb.gt r15,0x200 - 64: 00 02 00 00 - 68: 00 8f 00 18 18008f00 extb.f r0,r1 - 6c: 01 8e 5e 18 185e8e01 extb.f r2,1 - 70: 00 0f e2 1f 1fe20f00 extb.f 0,r4 - 74: 00 0f bf 18 18bf0f00 extb.f r5,0x200 - 78: 00 02 00 00 - 7c: 00 0f df 1f 1fdf0f00 extb.f 0,0x200 - 80: 00 02 00 00 - 84: 01 8f 00 18 18008f01 extb.z.f r0,r1 - 88: 02 0f 3f 18 183f0f02 extb.nz.f r1,0 - 8c: 00 00 00 00 - 90: 0b 0f c1 1f 1fc10f0b extb.lt.f 0,r2 - 94: 00 00 00 00 00000000 - 98: 0c 0f 1f 18 181f0f0c extb.le.f r0,0x200 - 9c: 00 02 00 00 - a0: 04 0f df 1f 1fdf0f04 extb.n.f 0,0x200 - a4: 00 02 00 00 +0x[0-9a-f]+ 202f 0047 extb r0,r1 +0x[0-9a-f]+ 232f 3707 extb fp,sp +0x[0-9a-f]+ 206f 0007 extb r0,0 +0x[0-9a-f]+ 212f 0f87 ffff ffff extb r1,0xffffffff +0x[0-9a-f]+ 262f 7087 extb 0,r2 +0x[0-9a-f]+ 242f 0f87 0000 00ff extb r4,0xff +0x[0-9a-f]+ 262f 0f87 ffff ff00 extb r6,0xffffff00 +0x[0-9a-f]+ 202f 1f87 0000 0100 extb r8,0x100 +0x[0-9a-f]+ 212f 1f87 ffff feff extb r9,0xfffffeff +0x[0-9a-f]+ 232f 1f87 4242 4242 extb r11,0x42424242 +0x[0-9a-f]+ 202f 0f87 0000 0000 extb r0,0 + 44: ARC_32_ME foo +0x[0-9a-f]+ 202f 8047 extb.f r0,r1 +0x[0-9a-f]+ 226f 8047 extb.f r2,0x1 +0x[0-9a-f]+ 262f f107 extb.f 0,r4 +0x[0-9a-f]+ 252f 8f87 0000 0200 extb.f r5,0x200 diff --git a/gas/testsuite/gas/arc/extb.s b/gas/testsuite/gas/arc/extb.s index e872975dc7..050c73b07c 100644 --- a/gas/testsuite/gas/arc/extb.s +++ b/gas/testsuite/gas/arc/extb.s @@ -6,33 +6,16 @@ extb r0,0 extb r1,-1 extb 0,r2 - extb -1,r3 extb r4,255 - extb 255,r5 extb r6,-256 - extb -256,r7 extb r8,256 extb r9,-257 extb r11,0x42424242 - extb 255,256 - extb r0,foo - extb.eq r10,r11 - extb.ne r12,r13 - extb.lt r14,0 - extb.gt r15,512 - extb.f r0,r1 extb.f r2,1 extb.f 0,r4 extb.f r5,512 - extb.f 512,512 - - extb.eq.f r0,r1 - extb.ne.f r1,0 - extb.lt.f 0,r2 - extb.le.f r0,512 - extb.n.f 512,512 diff --git a/gas/testsuite/gas/arc/extensions.d b/gas/testsuite/gas/arc/extensions.d index dc0d80b5f5..73d8a001c6 100644 --- a/gas/testsuite/gas/arc/extensions.d +++ b/gas/testsuite/gas/arc/extensions.d @@ -1,5 +1,6 @@ -#as: -EL -marc8 +#as: -EL #objdump: -dr -EL +#skip: *-*-* .*: +file format elf32-.*arc @@ -9,4 +10,4 @@ Disassembly of section .text: 0: 12 02 00 40 40000212 add.isbusy r0,r0,r1 4: 00 02 60 45 45600200 add rwscreg,r0,r1 8: 00 d8 00 40 4000d800 add r0,r1,roscreg - c: 00 02 a0 45 45a00200 add woscreg,r0,r1
\ No newline at end of file + c: 00 02 a0 45 45a00200 add woscreg,r0,r1 diff --git a/gas/testsuite/gas/arc/extw.d b/gas/testsuite/gas/arc/extw.d index 500f2fa82c..c33768bfb7 100644 --- a/gas/testsuite/gas/arc/extw.d +++ b/gas/testsuite/gas/arc/extw.d @@ -1,51 +1,22 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 90 00 18 18009000 extw r0,r1 - 4: 00 10 6e 1b 1b6e1000 extw fp,sp - 8: 00 90 1f 18 181f9000 extw r0,0 - c: ff 91 3f 18 183f91ff extw r1,-1 - 10: 00 10 e1 1f 1fe11000 extw 0,r2 - 14: 00 90 e1 1f 1fe19000 extw 0,r3 - 18: ff 90 9f 18 189f90ff extw r4,255 - 1c: 00 90 e2 1f 1fe29000 extw 0,r5 - 20: 00 91 df 18 18df9100 extw r6,-256 - 24: 00 90 e3 1f 1fe39000 extw 0,r7 - 28: 00 10 1f 19 191f1000 extw r8,0x100 - 2c: 00 01 00 00 - 30: 00 10 3f 19 193f1000 extw r9,0xffff_feff - 34: ff fe ff ff - 38: 00 10 7f 19 197f1000 extw r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 10 ff 1f 1fff1000 extw 0,0x100 - 44: 00 01 00 00 - 48: 00 10 1f 18 181f1000 extw r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 01 90 45 19 19459001 extw.z r10,r11 - 54: 02 90 86 19 19869002 extw.nz r12,r13 - 58: 0b 10 df 19 19df100b extw.lt r14,0 - 5c: 00 00 00 00 - 60: 09 10 ff 19 19ff1009 extw.gt r15,0x200 - 64: 00 02 00 00 - 68: 00 91 00 18 18009100 extw.f r0,r1 - 6c: 01 90 5e 18 185e9001 extw.f r2,1 - 70: 00 11 e2 1f 1fe21100 extw.f 0,r4 - 74: 00 11 bf 18 18bf1100 extw.f r5,0x200 - 78: 00 02 00 00 - 7c: 00 11 df 1f 1fdf1100 extw.f 0,0x200 - 80: 00 02 00 00 - 84: 01 91 00 18 18009101 extw.z.f r0,r1 - 88: 02 11 3f 18 183f1102 extw.nz.f r1,0 - 8c: 00 00 00 00 - 90: 0b 11 c1 1f 1fc1110b extw.lt.f 0,r2 - 94: 00 00 00 00 00000000 - 98: 0c 11 1f 18 181f110c extw.le.f r0,0x200 - 9c: 00 02 00 00 - a0: 04 11 df 1f 1fdf1104 extw.n.f 0,0x200 - a4: 00 02 00 00 +0x00000000 202f 0048 ext[hw]+ r0,r1 +0x00000004 232f 3708 ext[hw]+ fp,sp +0x00000008 206f 0008 ext[hw]+ r0,0 +0x0000000c 212f 0f88 ffff ffff ext[hw]+ r1,0xffffffff +0x00000014 262f 7088 ext[hw]+ 0,r2 +0x00000018 242f 0f88 0000 00ff ext[hw]+ r4,0xff +0x00000020 262f 0f88 ffff ff00 ext[hw]+ r6,0xffffff00 +0x00000028 202f 1f88 0000 0100 ext[hw]+ r8,0x100 +0x00000030 212f 1f88 ffff feff ext[hw]+ r9,0xfffffeff +0x00000038 232f 1f88 4242 4242 ext[hw]+ r11,0x42424242 +0x00000040 202f 0f88 0000 0000 ext[hw]+ r0,0 + 44: ARC_32_ME foo +0x00000048 202f 8048 ext[hw]+.f r0,r1 +0x0000004c 226f 8048 ext[hw]+.f r2,0x1 +0x00000050 262f f108 ext[hw]+.f 0,r4 +0x00000054 252f 8f88 0000 0200 ext[hw]+.f r5,0x200 diff --git a/gas/testsuite/gas/arc/extw.s b/gas/testsuite/gas/arc/extw.s index 060a8e3532..9cde2aa9f3 100644 --- a/gas/testsuite/gas/arc/extw.s +++ b/gas/testsuite/gas/arc/extw.s @@ -6,33 +6,16 @@ extw r0,0 extw r1,-1 extw 0,r2 - extw -1,r3 extw r4,255 - extw 255,r5 extw r6,-256 - extw -256,r7 extw r8,256 extw r9,-257 extw r11,0x42424242 - extw 255,256 - extw r0,foo - extw.eq r10,r11 - extw.ne r12,r13 - extw.lt r14,0 - extw.gt r15,512 - extw.f r0,r1 extw.f r2,1 extw.f 0,r4 extw.f r5,512 - extw.f 512,512 - - extw.eq.f r0,r1 - extw.ne.f r1,0 - extw.lt.f 0,r2 - extw.le.f r0,512 - extw.n.f 512,512 diff --git a/gas/testsuite/gas/arc/flag.d b/gas/testsuite/gas/arc/flag.d index 55c59ded40..5371439b99 100644 --- a/gas/testsuite/gas/arc/flag.d +++ b/gas/testsuite/gas/arc/flag.d @@ -1,38 +1,26 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 00 a0 1f 1fa00000 flag r0 - 4: 01 80 bf 1f 1fbf8001 flag 1 - 8: 02 80 bf 1f 1fbf8002 flag 2 - c: 04 80 bf 1f 1fbf8004 flag 4 - 10: 08 80 bf 1f 1fbf8008 flag 8 - 14: 10 80 bf 1f 1fbf8010 flag 16 - 18: 20 80 bf 1f 1fbf8020 flag 32 - 1c: 40 80 bf 1f 1fbf8040 flag 64 - 20: 80 80 bf 1f 1fbf8080 flag 128 - 24: 00 00 bf 1f 1fbf0000 flag 0x8000_0001 - 28: 01 00 00 80 - 2c: 0b 00 a0 1f 1fa0000b flag.lt r0 - 30: 09 00 bf 1f 1fbf0009 flag.gt 1 - 34: 01 00 00 00 - 38: 09 00 bf 1f 1fbf0009 flag.gt 2 - 3c: 02 00 00 00 - 40: 09 00 bf 1f 1fbf0009 flag.gt 4 - 44: 04 00 00 00 - 48: 09 00 bf 1f 1fbf0009 flag.gt 8 - 4c: 08 00 00 00 - 50: 09 00 bf 1f 1fbf0009 flag.gt 16 - 54: 10 00 00 00 - 58: 09 00 bf 1f 1fbf0009 flag.gt 32 - 5c: 20 00 00 00 - 60: 09 00 bf 1f 1fbf0009 flag.gt 64 - 64: 40 00 00 00 - 68: 09 00 bf 1f 1fbf0009 flag.gt 128 - 6c: 80 00 00 00 - 70: 0a 00 bf 1f 1fbf000a flag.ge 0x8000_0001 - 74: 01 00 00 80 +0x[0-9a-f]+ 2029 0000 flag r0 +0x[0-9a-f]+ 2069 0040 flag 0x1 +0x[0-9a-f]+ 2069 0080 flag 0x2 +0x[0-9a-f]+ 2069 0100 flag 0x4 +0x[0-9a-f]+ 2069 0200 flag 0x8 +0x[0-9a-f]+ 2069 0400 flag 0x10 +0x[0-9a-f]+ 2069 0800 flag 0x20 +0x[0-9a-f]+ 20a9 0001 flag 64 +0x[0-9a-f]+ 20a9 0002 flag 128 +0x[0-9a-f]+ 2029 0f80 8000 0001 flag 0x80000001 +0x[0-9a-f]+ 20e9 000b flag.lt r0 +0x[0-9a-f]+ 20e9 0069 flag.gt 0x1 +0x[0-9a-f]+ 20e9 00a9 flag.gt 0x2 +0x[0-9a-f]+ 20e9 0129 flag.gt 0x4 +0x[0-9a-f]+ 20e9 0229 flag.gt 0x8 +0x[0-9a-f]+ 20e9 0429 flag.gt 0x10 +0x[0-9a-f]+ 20e9 0829 flag.gt 0x20 +0x[0-9a-f]+ 20e9 0f89 0000 0040 flag.gt 0x40 +0x[0-9a-f]+ 20e9 0f89 0000 0080 flag.gt 0x80 +0x[0-9a-f]+ 20e9 0f8a 8000 0001 flag.ge 0x80000001 diff --git a/gas/testsuite/gas/arc/insn3.d b/gas/testsuite/gas/arc/insn3.d deleted file mode 100644 index c0207a77a4..0000000000 --- a/gas/testsuite/gas/arc/insn3.d +++ /dev/null @@ -1,44 +0,0 @@ -#objdump: -dr -#name: @OC@ - -# Test the @OC@ insn. - -.*: +file format elf32-.*arc - -Disassembly of section .text: -00000000 1800@I3+80@00 @OC@ r0,r1 -00000004 1b6e@I3+00@00 @OC@ fp,sp -00000008 181f@I3+80@00 @OC@ r0,0 -0000000c 183f@I3+81@ff @OC@ r1,-1 -00000010 1fe1@I3+00@00 @OC@ 0,r2 -00000014 1fe1@I3+81@ff @OC@ -1,r3 -00000018 189f@I3+80@ff @OC@ r4,255 -0000001c 1fe2@I3+80@ff @OC@ 255,r5 -00000020 18df@I3+81@00 @OC@ r6,-256 -00000024 1fe3@I3+81@00 @OC@ -256,r7 -00000028 191f@I3+00@00 @OC@ r8,256 -00000030 193f@I3+00@00 @OC@ r9,-257 -00000038 1fc5@I3+00@00 @OC@ 511,r10 -00000040 197f@I3+00@00 @OC@ r11,1111638594 -00000048 1fc6@I3+00@00 @OC@ 305419896,r12 -00000050 1fff@I3+00@ff @OC@ 255,256 -00000058 1fdf@I3+80@ff @OC@ 256,255 -00000060 181f@I3+00@00 @OC@ r0,0 - RELOC: 00000064 R_ARC_32 foo -00000068 1945@I3+80@01 @OC@.eq r10,r11 -0000006c 1986@I3+80@02 @OC@.ne r12,r13 -00000070 19df@I3+00@0b @OC@.lt r14,0 -00000078 19ff@I3+00@09 @OC@.gt r15,512 -00000080 1800@I3+81@00 @OC@.f r0,r1 -00000084 185e@I3+80@01 @OC@.f r2,1 -00000088 1fa2@I3+00@00 @OC@.f 0,r4 -0000008c 18bf@I3+01@00 @OC@.f r5,512 -00000094 1fc3@I3+01@00 @OC@.f 512,r6 -0000009c 1fdf@I3+01@00 @OC@.f 512,512 -000000a4 1800@I3+81@01 @OC@.eq.f r0,r1 -000000a8 183f@I3+01@02 @OC@.ne.f r1,0 -000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2 -000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2 -000000c0 181f@I3+01@0c @OC@.le.f r0,512 -000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2 -000000d0 1fdf@I3+01@04 @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/insn3.s b/gas/testsuite/gas/arc/insn3.s deleted file mode 100644 index f12fb88355..0000000000 --- a/gas/testsuite/gas/arc/insn3.s +++ /dev/null @@ -1,52 +0,0 @@ -# Insn 3 @OC@ test - -# reg,reg - @OC@ r0,r1 - @OC@ fp,sp - -# shimm values - @OC@ r0,0 - @OC@ r1,-1 - @OC@ 0,r2 - @OC@ -1,r3 - @OC@ r4,255 - @OC@ 255,r5 - @OC@ r6,-256 - @OC@ -256,r7 - -# limm values - @OC@ r8,256 - @OC@ r9,-257 - @OC@ 511,r10 - @OC@ r11,0x42424242 - @OC@ 0x12345678,r12 - -# shimm and limm - @OC@ 255,256 - @OC@ 256,255 - -# symbols - @OC@ r0,foo - -# conditional execution - @OC@.eq r10,r11 - @OC@.ne r12,r13 - @OC@.lt r14,0 - @OC@.gt r15,512 - -# flag setting - @OC@.f r0,r1 - @OC@.f r2,1 - @OC@.f 0,r4 - @OC@.f r5,512 - @OC@.f 512,r6 - @OC@.f 512,512 - -# conditional execution + flag setting - @OC@.eq.f r0,r1 - @OC@.ne.f r1,0 - @OC@.lt.f 0,r2 - @OC@.gt.f 1,r2 - @OC@.le.f r0,512 - @OC@.ge.f 512,r2 - @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/j.d b/gas/testsuite/gas/arc/j.d index 87e80042dc..6e28d1fc19 100644 --- a/gas/testsuite/gas/arc/j.d +++ b/gas/testsuite/gas/arc/j.d @@ -1,127 +1,67 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: -00000000 <text_label>: - 0: 00 00 1f 38 381f0000 j 0 <text_label> - - 4: 00 00 00 00 - 4: R_ARC_B26 .text - 8: 00 00 1f 38 381f0000 j 0 <text_label> - - c: 00 00 00 00 - c: R_ARC_B26 .text - 10: 00 00 1f 38 381f0000 j 0 <text_label> - - 14: 00 00 00 00 - 14: R_ARC_B26 .text - 18: 01 00 1f 38 381f0001 jz 0 <text_label> - - 1c: 00 00 00 00 - 1c: R_ARC_B26 .text - 20: 01 00 1f 38 381f0001 jz 0 <text_label> - - 24: 00 00 00 00 - 24: R_ARC_B26 .text - 28: 02 00 1f 38 381f0002 jnz 0 <text_label> - - 2c: 00 00 00 00 - 2c: R_ARC_B26 .text - 30: 02 00 1f 38 381f0002 jnz 0 <text_label> - - 34: 00 00 00 00 - 34: R_ARC_B26 .text - 38: 03 00 1f 38 381f0003 jp 0 <text_label> - - 3c: 00 00 00 00 - 3c: R_ARC_B26 .text - 40: 03 00 1f 38 381f0003 jp 0 <text_label> - - 44: 00 00 00 00 - 44: R_ARC_B26 .text - 48: 04 00 1f 38 381f0004 jn 0 <text_label> - - 4c: 00 00 00 00 - 4c: R_ARC_B26 .text - 50: 04 00 1f 38 381f0004 jn 0 <text_label> - - 54: 00 00 00 00 - 54: R_ARC_B26 .text - 58: 05 00 1f 38 381f0005 jc 0 <text_label> - - 5c: 00 00 00 00 - 5c: R_ARC_B26 .text - 60: 05 00 1f 38 381f0005 jc 0 <text_label> - - 64: 00 00 00 00 - 64: R_ARC_B26 .text - 68: 05 00 1f 38 381f0005 jc 0 <text_label> - - 6c: 00 00 00 00 - 6c: R_ARC_B26 .text - 70: 06 00 1f 38 381f0006 jnc 0 <text_label> - - 74: 00 00 00 00 - 74: R_ARC_B26 .text - 78: 06 00 1f 38 381f0006 jnc 0 <text_label> - - 7c: 00 00 00 00 - 7c: R_ARC_B26 .text - 80: 06 00 1f 38 381f0006 jnc 0 <text_label> - - 84: 00 00 00 00 - 84: R_ARC_B26 .text - 88: 07 00 1f 38 381f0007 jv 0 <text_label> - - 8c: 00 00 00 00 - 8c: R_ARC_B26 .text - 90: 07 00 1f 38 381f0007 jv 0 <text_label> - - 94: 00 00 00 00 - 94: R_ARC_B26 .text - 98: 08 00 1f 38 381f0008 jnv 0 <text_label> - - 9c: 00 00 00 00 - 9c: R_ARC_B26 .text - a0: 08 00 1f 38 381f0008 jnv 0 <text_label> - - a4: 00 00 00 00 - a4: R_ARC_B26 .text - a8: 09 00 1f 38 381f0009 jgt 0 <text_label> - - ac: 00 00 00 00 - ac: R_ARC_B26 .text - b0: 0a 00 1f 38 381f000a jge 0 <text_label> - - b4: 00 00 00 00 - b4: R_ARC_B26 .text - b8: 0b 00 1f 38 381f000b jlt 0 <text_label> - - bc: 00 00 00 00 - bc: R_ARC_B26 .text - c0: 0c 00 1f 38 381f000c jle 0 <text_label> - - c4: 00 00 00 00 - c4: R_ARC_B26 .text - c8: 0d 00 1f 38 381f000d jhi 0 <text_label> - - cc: 00 00 00 00 - cc: R_ARC_B26 .text - d0: 0e 00 1f 38 381f000e jls 0 <text_label> - - d4: 00 00 00 00 - d4: R_ARC_B26 .text - d8: 0f 00 1f 38 381f000f jpnz 0 <text_label> - - dc: 00 00 00 00 - dc: R_ARC_B26 .text - e0: 00 00 1f 38 381f0000 j 0 <text_label> - - e4: 00 00 00 00 - e4: R_ARC_B26 external_text_label - e8: 00 00 1f 38 381f0000 j 0 <text_label> - - ec: 00 00 00 00 +[0-9a-f]+ <text_label>: + 0: 2020 0f80 0000 0000 j 0 + 4: ARC_32_ME text_label + 8: 20e0 0f80 0000 0000 j 0 + c: ARC_32_ME text_label + 10: 20e0 0f80 0000 0000 j 0 + 14: ARC_32_ME text_label + 18: 20e0 0f81 0000 0000 jeq 0 + 1c: ARC_32_ME text_label + 20: 20e0 0f81 0000 0000 jeq 0 + 24: ARC_32_ME text_label + 28: 20e0 0f82 0000 0000 jne 0 + 2c: ARC_32_ME text_label + 30: 20e0 0f82 0000 0000 jne 0 + 34: ARC_32_ME text_label + 38: 20e0 0f83 0000 0000 jp 0 + 3c: ARC_32_ME text_label + 40: 20e0 0f83 0000 0000 jp 0 + 44: ARC_32_ME text_label + 48: 20e0 0f84 0000 0000 jn 0 + 4c: ARC_32_ME text_label + 50: 20e0 0f84 0000 0000 jn 0 + 54: ARC_32_ME text_label + 58: 20e0 0f85 0000 0000 jc 0 + 5c: ARC_32_ME text_label + 60: 20e0 0f85 0000 0000 jc 0 + 64: ARC_32_ME text_label + 68: 20e0 0f85 0000 0000 jc 0 + 6c: ARC_32_ME text_label + 70: 20e0 0f86 0000 0000 jnc 0 + 74: ARC_32_ME text_label + 78: 20e0 0f86 0000 0000 jnc 0 + 7c: ARC_32_ME text_label + 80: 20e0 0f86 0000 0000 jnc 0 + 84: ARC_32_ME text_label + 88: 20e0 0f87 0000 0000 jv 0 + 8c: ARC_32_ME text_label + 90: 20e0 0f87 0000 0000 jv 0 + 94: ARC_32_ME text_label + 98: 20e0 0f88 0000 0000 jnv 0 + 9c: ARC_32_ME text_label + a0: 20e0 0f88 0000 0000 jnv 0 + a4: ARC_32_ME text_label + a8: 20e0 0f89 0000 0000 jgt 0 + ac: ARC_32_ME text_label + b0: 20e0 0f8a 0000 0000 jge 0 + b4: ARC_32_ME text_label + b8: 20e0 0f8b 0000 0000 jlt 0 + bc: ARC_32_ME text_label + c0: 20e0 0f8c 0000 0000 jle 0 + c4: ARC_32_ME text_label + c8: 20e0 0f8d 0000 0000 jhi 0 + cc: ARC_32_ME text_label + d0: 20e0 0f8e 0000 0000 jls 0 + d4: ARC_32_ME text_label + d8: 20e0 0f8f 0000 0000 jpnz 0 + dc: ARC_32_ME text_label + e0: 2020 0f80 0000 0000 j 0 + e4: ARC_32_ME external_text_label + e8: 20a0 0000 j 0 diff --git a/gas/testsuite/gas/arc/j.s b/gas/testsuite/gas/arc/j.s index 64abbf5e12..24a6f38680 100644 --- a/gas/testsuite/gas/arc/j.s +++ b/gas/testsuite/gas/arc/j.s @@ -1,6 +1,6 @@ # j test - -text_label: + +text_label: j text_label jal text_label diff --git a/gas/testsuite/gas/arc/jl.d b/gas/testsuite/gas/arc/jl.d index 3701f9aab3..7330c15594 100644 --- a/gas/testsuite/gas/arc/jl.d +++ b/gas/testsuite/gas/arc/jl.d @@ -1,25 +1,14 @@ -#as: -EL -marc6 -#objdump: -dr -EL +#as: -mcpu=archs +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: -00000000 <text_label>: - 0: 40 02 1f 38 381f0240 jl 0 <text_label> - - 4: 00 00 00 00 - 4: R_ARC_B26 .text - 8: 40 03 1f 38 381f0340 jl.f 0 <text_label> - - c: 00 00 00 00 - c: R_ARC_B26 .text - 10: 02 82 00 38 38008202 jlnz \[r1\] - 14: 40 02 1f 38 381f0240 jl 0 <text_label> - - 18: 00 00 00 00 - 18: R_ARC_B26 .text - 1c: 40 03 1f 38 381f0340 jl.f 0 <text_label> - - 20: 00 00 00 00 - 20: R_ARC_B26 .text +[0-9a-f]+ <text_label>: + 0: 2022 0f80 0000 0000 jl 0 + 4: ARC_32_ME text_label + 8: 20e3 0042 jlne.d \[r1\] + c: 78e0 nop_s + e: 20e2 0f80 0000 0000 jl 0 + 12: ARC_32_ME text_label diff --git a/gas/testsuite/gas/arc/jl.s b/gas/testsuite/gas/arc/jl.s index 74a9e201d4..bb660c7c26 100644 --- a/gas/testsuite/gas/arc/jl.s +++ b/gas/testsuite/gas/arc/jl.s @@ -3,7 +3,6 @@ text_label: jl text_label - jl.f text_label - jlnz.nd [r1] + jlnz.d [r1] + nop_s jlal text_label - jlal.f text_label diff --git a/gas/testsuite/gas/arc/ld.d b/gas/testsuite/gas/arc/ld.d index 2680ae9fdf..eef573f036 100644 --- a/gas/testsuite/gas/arc/ld.d +++ b/gas/testsuite/gas/arc/ld.d @@ -1,16 +1,16 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: -00000000 <.text>: - 0: 00 84 00 00 00008400 ld r0,\[r1,r2\] - 4: 02 84 00 00 00008402 ldb r0,\[r1,r2\] - 8: 08 88 21 00 00218808 ld.a r1,\[r3,r4\] - c: 05 06 21 00 00210605 ldw.x r1,\[r2,r3\] - 10: 0d 88 41 00 0041880d ldw.x.a r2,\[r3,r4\] - 14: 00 80 1f 08 081f8000 ld r0,\[0\] - 18: 1e 80 00 08 0800801e ld r0,\[r1,30\] - 1c: ec 01 21 08 082101ec ld r1,\[r2,-20\] +[0-9a-f]+ <.text>: + 0: 2130 0080 ld r0,\[r1,r2\] + 4: 2132 0080 ldb r0,\[r1,r2\] + 8: 2370 0101 ld.aw r1,\[r3,r4\] + c: 2235 00c1 ld[hw]+.x r1,\[r2,r3\] + 10: 2375 0102 ld[hw]+.aw.x r2,\[r3,r4\] + 14: 1600 7000 0000 0000 ld r0,\[0\] + 1c: 111e 0000 ld r0,\[r1,30\] + 20: 12ec 8001 ld r1,\[r2,-20\] diff --git a/gas/testsuite/gas/arc/ld.s b/gas/testsuite/gas/arc/ld.s index 7d0a5b839f..e77bee51a7 100644 --- a/gas/testsuite/gas/arc/ld.s +++ b/gas/testsuite/gas/arc/ld.s @@ -1,10 +1,10 @@ # ld test - + ld r0,[r1,r2] ldb r0,[r1,r2] ld.a r1,[r3,r4] ldw.x r1,[r2,r3] ldw.x.a r2,[r3,r4] ld r0,[0] - ld r0,[r1,30] - ld r1,[r2,-20] + ld r0,[r1,30] + ld r1,[r2,-20] diff --git a/gas/testsuite/gas/arc/ld2.d b/gas/testsuite/gas/arc/ld2.d index 1f1df97b5d..8e44c41236 100644 --- a/gas/testsuite/gas/arc/ld2.d +++ b/gas/testsuite/gas/arc/ld2.d @@ -1,21 +1,19 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: -00000000 <.text>: - 0: 00 80 00 08 08008000 ld r0,\[r1\] - 4: 01 00 a3 08 08a30001 ld r5,\[r6,1\] - 8: 00 00 7f 0a 0a7f0000 ld r19,\[0\] - c: 00 00 00 00 - c: R_ARC_32 foo - 10: 0a 10 81 08 0881100a ld.a r4,\[r2,10\] - 14: 00 00 3f 08 083f0000 ld r1,\[0x384\] - 18: 84 03 00 00 - 1c: 0f 84 41 08 0841840f ldb r2,\[r3,15\] - 20: fe 09 62 08 086209fe ldw r3,\[r4,-2\] - 24: 00 20 21 08 08212000 lr r1,\[r2\] - 28: 14 a0 3f 08 083fa014 lr r1,\[0x14\] - 2c: 00 a0 1f 08 081fa000 lr r0,\[status\] +[0-9a-f]+ <.text>: + 0: 1100 0000 ld r0,\[r1\] + 4: 1601 0005 ld r5,\[r6,1\] + 8: 1600 7013 0000 0000 ld r19,\[0\] + c: ARC_32_ME foo + 10: 120a 0204 ld.aw r4,\[r2,10\] + 14: 1600 7001 0000 0384 ld r1,\[0x384\] + 1c: 130f 0082 ldb r2,\[r3,15\] + 20: 14fe 8103 ld[hw]+ r3,\[r4,-2\] + 24: 212a 0080 lr r1,\[r2\] + 28: 216a 0500 lr r1,\[0x14\] + 2c: 206a 0000 lr r0,\[0\] diff --git a/gas/testsuite/gas/arc/ld2.s b/gas/testsuite/gas/arc/ld2.s index c18556a237..aae01eca28 100644 --- a/gas/testsuite/gas/arc/ld2.s +++ b/gas/testsuite/gas/arc/ld2.s @@ -7,7 +7,7 @@ ld r1,[900] ldb r2,[r3,15] ldw r3,[r4,-2] - + lr r1,[r2] lr r1,[20] lr r0,[status] diff --git a/gas/testsuite/gas/arc/lp.d b/gas/testsuite/gas/arc/lp.d index 3b1827c389..50bfd4ac00 100644 --- a/gas/testsuite/gas/arc/lp.d +++ b/gas/testsuite/gas/arc/lp.d @@ -1,76 +1,37 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=archs +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: -00000000 <text_label>: - 0: 80 ff ff 37 37ffff80 lp 0 <text_label> - - 4: 00 ff ff 37 37ffff00 lp 0 <text_label> - - 8: 80 fe ff 37 37fffe80 lp 0 <text_label> - - c: 01 fe ff 37 37fffe01 lpz 0 <text_label> - - 10: 81 fd ff 37 37fffd81 lpz 0 <text_label> - - 14: 02 fd ff 37 37fffd02 lpnz 0 <text_label> - - 18: 82 fc ff 37 37fffc82 lpnz 0 <text_label> - - 1c: 03 fc ff 37 37fffc03 lpp 0 <text_label> - - 20: 83 fb ff 37 37fffb83 lpp 0 <text_label> - - 24: 04 fb ff 37 37fffb04 lpn 0 <text_label> - - 28: 84 fa ff 37 37fffa84 lpn 0 <text_label> - - 2c: 05 fa ff 37 37fffa05 lpc 0 <text_label> - - 30: 85 f9 ff 37 37fff985 lpc 0 <text_label> - - 34: 05 f9 ff 37 37fff905 lpc 0 <text_label> - - 38: 86 f8 ff 37 37fff886 lpnc 0 <text_label> - - 3c: 06 f8 ff 37 37fff806 lpnc 0 <text_label> - - 40: 86 f7 ff 37 37fff786 lpnc 0 <text_label> - - 44: 07 f7 ff 37 37fff707 lpv 0 <text_label> - - 48: 87 f6 ff 37 37fff687 lpv 0 <text_label> - - 4c: 08 f6 ff 37 37fff608 lpnv 0 <text_label> - - 50: 88 f5 ff 37 37fff588 lpnv 0 <text_label> - - 54: 09 f5 ff 37 37fff509 lpgt 0 <text_label> - - 58: 8a f4 ff 37 37fff48a lpge 0 <text_label> - - 5c: 0b f4 ff 37 37fff40b lplt 0 <text_label> - - 60: 8c f3 ff 37 37fff38c lple 0 <text_label> - - 64: 0d f3 ff 37 37fff30d lphi 0 <text_label> - - 68: 8e f2 ff 37 37fff28e lpls 0 <text_label> - - 6c: 0f f2 ff 37 37fff20f lppnz 0 <text_label> - - 70: a0 f1 ff 37 37fff1a0 lp.d 0 <text_label> - - 74: 00 f1 ff 37 37fff100 lp 0 <text_label> - - 78: c0 f0 ff 37 37fff0c0 lp.jd 0 <text_label> - - 7c: 21 f0 ff 37 37fff021 lpz.d 0 <text_label> - - 80: 82 ef ff 37 37ffef82 lpnz 0 <text_label> - - 84: 46 ef ff 37 37ffef46 lpnc.jd 0 <text_label> - +[0-9a-f]+ <text_label-0x72>: + 0: 20a8 0e40 lp 72 <text_label> + 4: 20e8 0de0 lp 72 <text_label> + 8: 20e8 0d60 lp 72 <text_label> + c: 20e8 0ce1 lpeq 72 <text_label> + 10: 20e8 0c61 lpeq 72 <text_label> + 14: 20e8 0be2 lpne 72 <text_label> + 18: 20e8 0b62 lpne 72 <text_label> + 1c: 20e8 0ae3 lpp 72 <text_label> + 20: 20e8 0a63 lpp 72 <text_label> + 24: 20e8 09e4 lpn 72 <text_label> + 28: 20e8 0964 lpn 72 <text_label> + 2c: 20e8 08e5 lpc 72 <text_label> + 30: 20e8 0865 lpc 72 <text_label> + 34: 20e8 07e5 lpc 72 <text_label> + 38: 20e8 0766 lpnc 72 <text_label> + 3c: 20e8 06e6 lpnc 72 <text_label> + 40: 20e8 0666 lpnc 72 <text_label> + 44: 20e8 05e7 lpv 72 <text_label> + 48: 20e8 0567 lpv 72 <text_label> + 4c: 20e8 04e8 lpnv 72 <text_label> + 50: 20e8 0468 lpnv 72 <text_label> + 54: 20e8 03e9 lpgt 72 <text_label> + 58: 20e8 036a lpge 72 <text_label> + 5c: 20e8 02eb lplt 72 <text_label> + 60: 20e8 026c lple 72 <text_label> + 64: 20e8 01ed lphi 72 <text_label> + 68: 20e8 016e lpls 72 <text_label> + 6c: 20e8 00ef lppnz 72 <text_label> + 70: 78e0 nop_s diff --git a/gas/testsuite/gas/arc/lp.s b/gas/testsuite/gas/arc/lp.s index 1913976a58..29b07ca723 100644 --- a/gas/testsuite/gas/arc/lp.s +++ b/gas/testsuite/gas/arc/lp.s @@ -1,6 +1,4 @@ # lp test - -text_label: lp text_label lpal text_label @@ -31,10 +29,5 @@ text_label: lpls text_label lppnz text_label - lp.d text_label - lp.nd text_label - lp.jd text_label - - lpeq.d text_label - lpne.nd text_label - lpcc.jd text_label + nop_s +text_label: diff --git a/gas/testsuite/gas/arc/lsr.d b/gas/testsuite/gas/arc/lsr.d index 27247a2fa3..28ff4b96bd 100644 --- a/gas/testsuite/gas/arc/lsr.d +++ b/gas/testsuite/gas/arc/lsr.d @@ -1,51 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 84 00 18 18008400 lsr r0,r1 - 4: 00 04 6e 1b 1b6e0400 lsr fp,sp - 8: 00 84 1f 18 181f8400 lsr r0,0 - c: ff 85 3f 18 183f85ff lsr r1,-1 - 10: 00 04 e1 1f 1fe10400 lsr 0,r2 - 14: 00 84 e1 1f 1fe18400 lsr 0,r3 - 18: ff 84 9f 18 189f84ff lsr r4,255 - 1c: 00 84 e2 1f 1fe28400 lsr 0,r5 - 20: 00 85 df 18 18df8500 lsr r6,-256 - 24: 00 84 e3 1f 1fe38400 lsr 0,r7 - 28: 00 04 1f 19 191f0400 lsr r8,0x100 - 2c: 00 01 00 00 - 30: 00 04 3f 19 193f0400 lsr r9,0xffff_feff - 34: ff fe ff ff - 38: 00 04 7f 19 197f0400 lsr r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 04 ff 1f 1fff0400 lsr 0,0x100 - 44: 00 01 00 00 - 48: 00 04 1f 18 181f0400 lsr r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 01 84 45 19 19458401 lsr.z r10,r11 - 54: 02 84 86 19 19868402 lsr.nz r12,r13 - 58: 0b 04 df 19 19df040b lsr.lt r14,0 - 5c: 00 00 00 00 - 60: 09 04 ff 19 19ff0409 lsr.gt r15,0x200 - 64: 00 02 00 00 - 68: 00 85 00 18 18008500 lsr.f r0,r1 - 6c: 01 84 5e 18 185e8401 lsr.f r2,1 - 70: 00 05 e2 1f 1fe20500 lsr.f 0,r4 - 74: 00 05 bf 18 18bf0500 lsr.f r5,0x200 - 78: 00 02 00 00 - 7c: 00 05 df 1f 1fdf0500 lsr.f 0,0x200 - 80: 00 02 00 00 - 84: 01 85 00 18 18008501 lsr.z.f r0,r1 - 88: 02 05 3f 18 183f0502 lsr.nz.f r1,0 - 8c: 00 00 00 00 - 90: 0b 05 c1 1f 1fc1050b lsr.lt.f 0,r2 - 94: 00 00 00 00 00000000 - 98: 0c 05 1f 18 181f050c lsr.le.f r0,0x200 - 9c: 00 02 00 00 - a0: 04 05 df 1f 1fdf0504 lsr.n.f 0,0x200 - a4: 00 02 00 00 +0x[0-9a-f]+ 2901 0080 lsr r0,r1,r2 +0x[0-9a-f]+ 2b01 371a lsr gp,fp,sp +0x[0-9a-f]+ 2e01 37dd lsr ilink,r30,blink +0x[0-9a-f]+ 2941 0000 lsr r0,r1,0 +0x[0-9a-f]+ 2e01 7080 0000 0000 lsr r0,0,r2 +0x[0-9a-f]+ 2901 00be lsr 0,r1,r2 +0x[0-9a-f]+ 2901 0f80 ffff ffff lsr r0,r1,0xffffffff +0x[0-9a-f]+ 2e01 7080 ffff ffff lsr r0,0xffffffff,r2 +0x[0-9a-f]+ 2901 0f80 0000 00ff lsr r0,r1,0xff +0x[0-9a-f]+ 2e01 7080 0000 00ff lsr r0,0xff,r2 +0x[0-9a-f]+ 2901 0f80 ffff ff00 lsr r0,r1,0xffffff00 +0x[0-9a-f]+ 2e01 7080 ffff ff00 lsr r0,0xffffff00,r2 +0x[0-9a-f]+ 2901 0f80 0000 0100 lsr r0,r1,0x100 +0x[0-9a-f]+ 2e01 7080 ffff feff lsr r0,0xfffffeff,r2 +0x[0-9a-f]+ 2e01 7f80 0000 0100 lsr r0,0x100,0x100 +0x[0-9a-f]+ 2901 0f80 0000 0000 lsr r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 28c1 0080 lsr r0,r0,r2 +0x[0-9a-f]+ 2bc1 0140 lsr r3,r3,r5 +0x[0-9a-f]+ 2ec1 0201 lsr.eq r6,r6,r8 +0x[0-9a-f]+ 29c1 12c1 lsr.eq r9,r9,r11 +0x[0-9a-f]+ 2cc1 1382 lsr.ne r12,r12,r14 +0x[0-9a-f]+ 2fc1 1442 lsr.ne r15,r15,r17 +0x[0-9a-f]+ 2ac1 2503 lsr.p r18,r18,r20 +0x[0-9a-f]+ 2dc1 25c3 lsr.p r21,r21,r23 +0x[0-9a-f]+ 28c1 3684 lsr.n r24,r24,gp +0x[0-9a-f]+ 2bc1 3744 lsr.n fp,fp,ilink +0x[0-9a-f]+ 2ec1 37c5 lsr.c r30,r30,blink +0x[0-9a-f]+ 2bc1 00c5 lsr.c r3,r3,r3 +0x[0-9a-f]+ 2bc1 0205 lsr.c r3,r3,r8 +0x[0-9a-f]+ 2bc1 0106 lsr.nc r3,r3,r4 +0x[0-9a-f]+ 2cc1 0106 lsr.nc r4,r4,r4 +0x[0-9a-f]+ 2cc1 01c6 lsr.nc r4,r4,r7 +0x[0-9a-f]+ 2cc1 0147 lsr.v r4,r4,r5 +0x[0-9a-f]+ 2dc1 0147 lsr.v r5,r5,r5 +0x[0-9a-f]+ 2dc1 0148 lsr.nv r5,r5,r5 +0x[0-9a-f]+ 2dc1 0148 lsr.nv r5,r5,r5 +0x[0-9a-f]+ 2ec1 0009 lsr.gt r6,r6,r0 +0x[0-9a-f]+ 28c1 002a lsr.ge r0,r0,0 +0x[0-9a-f]+ 29c1 006b lsr.lt r1,r1,0x1 +0x[0-9a-f]+ 2bc1 00ed lsr.hi r3,r3,0x3 +0x[0-9a-f]+ 2cc1 012e lsr.ls r4,r4,0x4 +0x[0-9a-f]+ 2dc1 016f lsr.pnz r5,r5,0x5 +0x[0-9a-f]+ 2901 8080 lsr.f r0,r1,r2 +0x[0-9a-f]+ 2941 8040 lsr.f r0,r1,0x1 +0x[0-9a-f]+ 2e01 f080 0000 0001 lsr.f r0,0x1,r2 +0x[0-9a-f]+ 2901 80be lsr.f 0,r1,r2 +0x[0-9a-f]+ 2901 8f80 0000 0200 lsr.f r0,r1,0x200 +0x[0-9a-f]+ 2e01 f080 0000 0200 lsr.f r0,0x200,r2 +0x[0-9a-f]+ 29c1 8081 lsr.f.eq r1,r1,r2 +0x[0-9a-f]+ 28c1 8022 lsr.f.ne r0,r0,0 +0x[0-9a-f]+ 2ac1 808b lsr.f.lt r2,r2,r2 +0x[0-9a-f]+ 2ec1 f0a9 0000 0001 lsr.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 2ec1 ff8c 0000 0200 lsr.f.le 0,0x200,0x200 +0x[0-9a-f]+ 2ec1 f0aa 0000 0200 lsr.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/lsr.s b/gas/testsuite/gas/arc/lsr.s index 3f539d80b4..66f754dda2 100644 --- a/gas/testsuite/gas/arc/lsr.s +++ b/gas/testsuite/gas/arc/lsr.s @@ -1,38 +1,63 @@ # lsr test - lsr r0,r1 - lsr fp,sp - - lsr r0,0 - lsr r1,-1 - lsr 0,r2 - lsr -1,r3 - lsr r4,255 - lsr 255,r5 - lsr r6,-256 - lsr -256,r7 - - lsr r8,256 - lsr r9,-257 - lsr r11,0x42424242 - - lsr 255,256 - - lsr r0,foo - - lsr.eq r10,r11 - lsr.ne r12,r13 - lsr.lt r14,0 - lsr.gt r15,512 - - lsr.f r0,r1 - lsr.f r2,1 - lsr.f 0,r4 - lsr.f r5,512 - lsr.f 512,512 - - lsr.eq.f r0,r1 - lsr.ne.f r1,0 - lsr.lt.f 0,r2 - lsr.le.f r0,512 - lsr.n.f 512,512 + lsr r0,r1,r2 + lsr r26,fp,sp + lsr ilink1,ilink2,blink + + lsr r0,r1,0 + lsr r0,0,r2 + lsr 0,r1,r2 + lsr r0,r1,-1 + lsr r0,-1,r2 + lsr r0,r1,255 + lsr r0,255,r2 + lsr r0,r1,-256 + lsr r0,-256,r2 + + lsr r0,r1,256 + lsr r0,-257,r2 + + lsr r0,256,256 + + lsr r0,r1,foo + + lsr.al r0,r0,r2 + lsr.ra r3,r3,r5 + lsr.eq r6,r6,r8 + lsr.z r9,r9,r11 + lsr.ne r12,r12,r14 + lsr.nz r15,r15,r17 + lsr.pl r18,r18,r20 + lsr.p r21,r21,r23 + lsr.mi r24,r24,r26 + lsr.n r27,r27,r29 + lsr.cs r30,r30,r31 + lsr.c r3,r3,r3 + lsr.lo r3,r3,r8 + lsr.cc r3,r3,r4 + lsr.nc r4,r4,r4 + lsr.hs r4,r4,r7 + lsr.vs r4,r4,r5 + lsr.v r5,r5,r5 + lsr.vc r5,r5,r5 + lsr.nv r5,r5,r5 + lsr.gt r6,r6,r0 + lsr.ge r0,r0,0 + lsr.lt r1,r1,1 + lsr.hi r3,r3,3 + lsr.ls r4,r4,4 + lsr.pnz r5,r5,5 + + lsr.f r0,r1,r2 + lsr.f r0,r1,1 + lsr.f r0,1,r2 + lsr.f 0,r1,r2 + lsr.f r0,r1,512 + lsr.f r0,512,r2 + + lsr.eq.f r1,r1,r2 + lsr.ne.f r0,r0,0 + lsr.lt.f r2,r2,r2 + lsr.gt.f 0,1,2 + lsr.le.f 0,512,512 + lsr.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/math.d b/gas/testsuite/gas/arc/math.d deleted file mode 100644 index ccb79c5ca7..0000000000 --- a/gas/testsuite/gas/arc/math.d +++ /dev/null @@ -1,78 +0,0 @@ -#objdump: -dr -#name: @OC@ - -# Test the @OC@ insn. - -.*: +file format elf32-.*arc - -Disassembly of section .text: -00000000 @IC+0@008400 @OC@ r0,r1,r2 -00000004 @IC+3@4db800 @OC@ r26,fp,sp -00000008 @IC+3@af3e00 @OC@ ilink1,ilink2,blink -0000000c @IC+7@5df800 @OC@ r58,r59,lp_count -00000010 @IC+0@00fe00 @OC@ r0,r1,0 -00000014 @IC+0@1f8400 @OC@ r0,0,r2 -00000018 @IC+7@e08400 @OC@ 0,r1,r2 -0000001c @IC+0@00ffff @OC@ r0,r1,-1 -00000020 @IC+0@1f85ff @OC@ r0,-1,r2 -00000024 @IC+7@e085ff @OC@ -1,r1,r2 -00000028 @IC+0@00feff @OC@ r0,r1,255 -0000002c @IC+0@1f84ff @OC@ r0,255,r2 -00000030 @IC+7@e084ff @OC@ 255,r1,r2 -00000034 @IC+0@00ff00 @OC@ r0,r1,-256 -00000038 @IC+0@1f8500 @OC@ r0,-256,r2 -0000003c @IC+7@e08500 @OC@ -256,r1,r2 -00000040 @IC+0@00fc00 @OC@ r0,r1,256 -00000048 @IC+0@1f0400 @OC@ r0,-257,r2 -00000050 @IC+7@c08400 @OC@ 511,r1,r2 -00000058 @IC+0@1f0400 @OC@ r0,1111638594,r2 -00000060 @IC+7@c0fc00 @OC@ 305419896,r1,305419896 -00000068 @IC+0@1ffcff @OC@ r0,255,256 -00000070 @IC+0@1f7eff @OC@ r0,256,255 -00000078 @IC+7@e0fcff @OC@ 255,r1,256 -00000080 @IC+7@ff04ff @OC@ 255,256,r2 -00000088 @IC+7@c0feff @OC@ 256,r1,255 -00000090 @IC+7@df84ff @OC@ 256,255,r2 -00000098 @IC+0@00fc00 @OC@ r0,r1,0 - RELOC: 0000009c R_ARC_32 foo -000000a0 @IC+0@008400 @OC@ r0,r1,r2 -000000a4 @IC+0@620a00 @OC@ r3,r4,r5 -000000a8 @IC+0@c39001 @OC@.eq r6,r7,r8 -000000ac @IC+1@251601 @OC@.eq r9,r10,r11 -000000b0 @IC+1@869c02 @OC@.ne r12,r13,r14 -000000b4 @IC+1@e82202 @OC@.ne r15,r16,r17 -000000b8 @IC+2@49a803 @OC@.p r18,r19,r20 -000000bc @IC+2@ab2e03 @OC@.p r21,r22,r23 -000000c0 @IC+3@0cb404 @OC@.n r24,r25,r26 -000000c4 @IC+3@6e3a04 @OC@.n fp,sp,ilink1 -000000c8 @IC+3@cfc005 @OC@.c ilink2,blink,r32 -000000cc @IC+4@314605 @OC@.c r33,r34,r35 -000000d0 @IC+4@92cc05 @OC@.c r36,r37,r38 -000000d4 @IC+4@f45206 @OC@.nc r39,r40,r41 -000000d8 @IC+5@55d806 @OC@.nc r42,r43,r44 -000000dc @IC+5@b75e06 @OC@.nc r45,r46,r47 -000000e0 @IC+6@18e407 @OC@.v r48,r49,r50 -000000e4 @IC+6@7a6a07 @OC@.v r51,r52,r53 -000000e8 @IC+6@dbf008 @OC@.nv r54,r55,r56 -000000ec @IC+7@3d7608 @OC@.nv r57,r58,r59 -000000f0 @IC+7@9e0009 @OC@.gt lp_count,lp_count,r0 -000000f4 @IC+0@007c0a @OC@.ge r0,r0,0 -000000fc @IC+0@3f020b @OC@.lt r1,1,r1 -00000104 @IC+7@c0840c @OC@.le 2,r1,r2 -0000010c @IC+0@7f060d @OC@.hi r3,3,r3 -00000114 @IC+7@df080e @OC@.ls 4,4,r4 -0000011c @IC+7@c2fc0f @OC@.pnz 5,r5,5 -00000124 @IC+0@008500 @OC@.f r0,r1,r2 -00000128 @IC+0@00fa01 @OC@.f r0,r1,1 -0000012c @IC+0@1e8401 @OC@.f r0,1,r2 -00000130 @IC+7@a08400 @OC@.f 0,r1,r2 -00000134 @IC+0@00fd00 @OC@.f r0,r1,512 -0000013c @IC+0@1f0500 @OC@.f r0,512,r2 -00000144 @IC+7@c08500 @OC@.f 512,r1,r2 -0000014c @IC+0@008501 @OC@.eq.f r0,r1,r2 -00000150 @IC+0@00fd02 @OC@.ne.f r0,r1,0 -00000158 @IC+0@1f050b @OC@.lt.f r0,0,r2 -00000160 @IC+7@c08509 @OC@.gt.f 0,r1,r2 -00000168 @IC+0@00fd0c @OC@.le.f r0,r1,512 -00000170 @IC+0@1f050a @OC@.ge.f r0,512,r2 -00000178 @IC+7@c08504 @OC@.n.f 512,r1,r2 diff --git a/gas/testsuite/gas/arc/math.s b/gas/testsuite/gas/arc/math.s deleted file mode 100644 index 775169a8a5..0000000000 --- a/gas/testsuite/gas/arc/math.s +++ /dev/null @@ -1,89 +0,0 @@ -# @OC@ test - -# Stay away from operands with duplicate arguments (eg: add r0,r1,r1). -# They will be disassembled as they're macro counterparts (eg: asl r0,r1). - -# reg,reg,reg - @OC@ r0,r1,r2 - @OC@ r26,fp,sp - @OC@ ilink1,ilink2,blink - @OC@ r58,r59,lp_count - -# shimm values - @OC@ r0,r1,0 - @OC@ r0,0,r2 - @OC@ 0,r1,r2 - @OC@ r0,r1,-1 - @OC@ r0,-1,r2 - @OC@ -1,r1,r2 - @OC@ r0,r1,255 - @OC@ r0,255,r2 - @OC@ 255,r1,r2 - @OC@ r0,r1,-256 - @OC@ r0,-256,r2 - @OC@ -256,r1,r2 - -# limm values - @OC@ r0,r1,256 - @OC@ r0,-257,r2 - @OC@ 511,r1,r2 - @OC@ r0,0x42424242,r2 - @OC@ 0x12345678,r1,0x12345678 - -# shimm and limm - @OC@ r0,255,256 - @OC@ r0,256,255 - @OC@ 255,r1,256 - @OC@ 255,256,r2 - @OC@ 256,r1,255 - @OC@ 256,255,r2 - -# symbols - @OC@ r0,r1,foo - -# conditional execution - @OC@.al r0,r1,r2 - @OC@.ra r3,r4,r5 - @OC@.eq r6,r7,r8 - @OC@.z r9,r10,r11 - @OC@.ne r12,r13,r14 - @OC@.nz r15,r16,r17 - @OC@.pl r18,r19,r20 - @OC@.p r21,r22,r23 - @OC@.mi r24,r25,r26 - @OC@.n r27,r28,r29 - @OC@.cs r30,r31,r32 - @OC@.c r33,r34,r35 - @OC@.lo r36,r37,r38 - @OC@.cc r39,r40,r41 - @OC@.nc r42,r43,r44 - @OC@.hs r45,r46,r47 - @OC@.vs r48,r49,r50 - @OC@.v r51,r52,r53 - @OC@.vc r54,r55,r56 - @OC@.nv r57,r58,r59 - @OC@.gt r60,r60,r0 - @OC@.ge r0,r0,0 - @OC@.lt r1,1,r1 - @OC@.le 2,r1,r2 - @OC@.hi r3,3,r3 - @OC@.ls 4,4,r4 - @OC@.pnz 5,r5,5 - -# flag setting - @OC@.f r0,r1,r2 - @OC@.f r0,r1,1 - @OC@.f r0,1,r2 - @OC@.f 0,r1,r2 - @OC@.f r0,r1,512 - @OC@.f r0,512,r2 - @OC@.f 512,r1,r2 - -# conditional execution + flag setting - @OC@.eq.f r0,r1,r2 - @OC@.ne.f r0,r1,0 - @OC@.lt.f r0,0,r2 - @OC@.gt.f 0,r1,r2 - @OC@.le.f r0,r1,512 - @OC@.ge.f r0,512,r2 - @OC@.n.f 512,r1,r2 diff --git a/gas/testsuite/gas/arc/mov.d b/gas/testsuite/gas/arc/mov.d index cff11d7df9..6ce6c55902 100644 --- a/gas/testsuite/gas/arc/mov.d +++ b/gas/testsuite/gas/arc/mov.d @@ -1,68 +1,56 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 82 00 60 60008200 mov r0,r1 - 4: 00 38 6e 63 636e3800 mov fp,sp - 8: 00 fe 1f 60 601ffe00 mov r0,0 - c: ff ff 3f 60 603fffff mov r1,-1 - 10: 00 04 e1 67 67e10400 mov 0,r2 - 14: 00 86 e1 67 67e18600 mov 0,r3 - 18: ff fe 9f 60 609ffeff mov r4,255 - 1c: 00 8a e2 67 67e28a00 mov 0,r5 - 20: 00 ff df 60 60dfff00 mov r6,-256 - 24: 00 8e e3 67 67e38e00 mov 0,r7 - 28: 00 7c 1f 61 611f7c00 mov r8,0x100 - 2c: 00 01 00 00 - 30: 00 7c 3f 61 613f7c00 mov r9,0xffff_feff - 34: ff fe ff ff - 38: 00 7c 7f 61 617f7c00 mov r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 7c ff 67 67ff7c00 mov 0,0x100 - 44: 00 01 00 00 - 48: 00 7c 1f 60 601f7c00 mov r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 00 82 00 60 60008200 mov r0,r1 - 54: 00 08 62 60 60620800 mov r3,r4 - 58: 01 8e c3 60 60c38e01 mov.z r6,r7 - 5c: 01 14 25 61 61251401 mov.z r9,r10 - 60: 02 9a 86 61 61869a02 mov.nz r12,r13 - 64: 02 20 e8 61 61e82002 mov.nz r15,r16 - 68: 03 a6 49 62 6249a603 mov.p r18,r19 - 6c: 03 2c ab 62 62ab2c03 mov.p r21,r22 - 70: 04 b2 0c 63 630cb204 mov.n r24,r25 - 74: 04 38 6e 63 636e3804 mov.n fp,sp - 78: 05 be cf 63 63cfbe05 mov.c ilink2,blink - 7c: 05 44 31 64 64314405 mov.c r33,r34 - 80: 05 ca 92 64 6492ca05 mov.c r36,r37 - 84: 06 50 f4 64 64f45006 mov.nc r39,r40 - 88: 06 d6 55 65 6555d606 mov.nc r42,r43 - 8c: 06 5c b7 65 65b75c06 mov.nc r45,r46 - 90: 07 e2 18 66 6618e207 mov.v r48,r49 - 94: 07 64 39 66 66396407 mov.v r49,r50 - 98: 08 ee 3b 66 663bee08 mov.nv r49,r55 - 9c: 08 74 3d 66 663d7408 mov.nv r49,r58 - a0: 09 78 9e 67 679e7809 mov.gt lp_count,lp_count - a4: 0a 7c 1f 60 601f7c0a mov.ge r0,0 - a8: 00 00 00 00 - ac: 0c 7c df 67 67df7c0c mov.le 0,2 - b0: 02 00 00 00 - b4: 0d 86 61 60 6061860d mov.hi r3,r3 - b8: 0e 08 82 60 6082080e mov.ls r4,r4 - bc: 0f 8a a2 60 60a28a0f mov.pnz r5,r5 - c0: 00 83 00 60 60008300 mov.f r0,r1 - c4: 01 fa 5e 60 605efa01 mov.f r2,1 - c8: 00 87 e1 67 67e18700 mov.f 0,r3 - cc: 00 09 e2 67 67e20900 mov.f 0,r4 - d0: 00 7d bf 60 60bf7d00 mov.f r5,0x200 - d4: 00 02 00 00 - d8: 00 7d df 67 67df7d00 mov.f 0,0x200 - dc: 00 02 00 00 - e0: 01 83 00 60 60008301 mov.z.f r0,r1 - e4: 02 7d 3f 60 603f7d02 mov.nz.f r1,0 - e8: 00 00 00 00 +0x[0-9a-f]+ 200a 0040 mov r0,r1 +0x[0-9a-f]+ 230a 3700 mov fp,sp +0x[0-9a-f]+ 204a 0000 mov r0,0 +0x[0-9a-f]+ 218a 0fff mov r1,-1 +0x[0-9a-f]+ 260a 7080 mov 0,r2 +0x[0-9a-f]+ 248a 0fc3 mov r4,255 +0x[0-9a-f]+ 268a 7fc3 mov 0,255 +0x[0-9a-f]+ 268a 003c mov r6,-256 +0x[0-9a-f]+ 230a 1f80 4242 4242 mov r11,0x42424242 +0x[0-9a-f]+ 260a 7f80 1234 5678 mov 0,0x12345678 +0x[0-9a-f]+ 200a 0f80 0000 0000 mov r0,0 + 34: ARC_32_ME foo +0x[0-9a-f]+ 20ca 0040 mov r0,r1 +0x[0-9a-f]+ 23ca 0100 mov r3,r4 +0x[0-9a-f]+ 26ca 01c1 mov.eq r6,r7 +0x[0-9a-f]+ 21ca 1281 mov.eq r9,r10 +0x[0-9a-f]+ 24ca 1342 mov.ne r12,r13 +0x[0-9a-f]+ 27ca 1402 mov.ne r15,r16 +0x[0-9a-f]+ 22ca 24c3 mov.p r18,r19 +0x[0-9a-f]+ 25ca 2583 mov.p r21,r22 +0x[0-9a-f]+ 20ca 3644 mov.n r24,r25 +0x[0-9a-f]+ 23ca 3704 mov.n fp,sp +0x[0-9a-f]+ 20ca 0045 mov.c r0,r1 +0x[0-9a-f]+ 23ca 0105 mov.c r3,r4 +0x[0-9a-f]+ 26ca 01c5 mov.c r6,r7 +0x[0-9a-f]+ 21ca 1006 mov.nc r9,r0 +0x[0-9a-f]+ 22ca 00c6 mov.nc r2,r3 +0x[0-9a-f]+ 25ca 0186 mov.nc r5,r6 +0x[0-9a-f]+ 20ca 1247 mov.v r8,r9 +0x[0-9a-f]+ 21ca 0087 mov.v r1,r2 +0x[0-9a-f]+ 24ca 0148 mov.nv r4,r5 +0x[0-9a-f]+ 27ca 0208 mov.nv r7,r8 +0x[0-9a-f]+ 20ca 0009 mov.gt r0,r0 +0x[0-9a-f]+ 20ca 002a mov.ge r0,0 +0x[0-9a-f]+ 26ca 704b mov.lt 0,r1 +0x[0-9a-f]+ 26ca 70ac mov.le 0,0x2 +0x[0-9a-f]+ 23ca 00cd mov.hi r3,r3 +0x[0-9a-f]+ 24ca 010e mov.ls r4,r4 +0x[0-9a-f]+ 25ca 014f mov.pnz r5,r5 +0x[0-9a-f]+ 200a 8040 mov.f r0,r1 +0x[0-9a-f]+ 224a 8040 mov.f r2,0x1 +0x[0-9a-f]+ 260a f100 mov.f 0,r4 +0x[0-9a-f]+ 258a 8008 mov.f r5,512 +0x[0-9a-f]+ 20ca 8041 mov.f.eq r0,r1 +0x[0-9a-f]+ 21ca 8022 mov.f.ne r1,0 +0x[0-9a-f]+ 26ca f08b mov.f.lt 0,r2 +0x[0-9a-f]+ 26ca f089 mov.f.gt 0,r2 +0x[0-9a-f]+ 20ca 8f8c 0000 0200 mov.f.le r0,0x200 +0x[0-9a-f]+ 26ca f08a mov.f.ge 0,r2 +0x[0-9a-f]+ 26ca ff84 0000 0200 mov.f.n 0,0x200 diff --git a/gas/testsuite/gas/arc/mov.s b/gas/testsuite/gas/arc/mov.s index fdee0b717e..676bcfae7f 100644 --- a/gas/testsuite/gas/arc/mov.s +++ b/gas/testsuite/gas/arc/mov.s @@ -1,58 +1,64 @@ # mov test +# reg,reg mov r0,r1 mov fp,sp +# shimm values mov r0,0 mov r1,-1 mov 0,r2 - mov -1,r3 mov r4,255 - mov 255,r5 + mov 0,255 mov r6,-256 - mov -256,r7 - mov r8,256 - mov r9,-257 +# limm values mov r11,0x42424242 + mov 0, 0x12345678 - mov 255,256 - - mov r0,foo +# symbols + mov r0,@foo +# conditional execution mov.al r0,r1 mov.ra r3,r4 mov.eq r6,r7 - mov.z r9,r10 + mov.z r9,r10 mov.ne r12,r13 mov.nz r15,r16 mov.pl r18,r19 - mov.p r21,r22 + mov.p r21,r22 mov.mi r24,r25 - mov.n r27,r28 - mov.cs r30,r31 - mov.c r33,r34 - mov.lo r36,r37 - mov.cc r39,r40 - mov.nc r42,r43 - mov.hs r45,r46 - mov.vs r48,r49 - mov.v r49,r50 - mov.vc r49,r55 - mov.nv r49,r58 - mov.gt r60,r60 + mov.n r27,r28 + mov.cs r0,r1 + mov.c r3,r4 + mov.lo r6,r7 + mov.cc r9,r0 + mov.nc r2,r3 + mov.hs r5,r6 + mov.vs r8,r9 + mov.v r1,r2 + mov.vc r4,r5 + mov.nv r7,r8 + mov.gt r0,r0 mov.ge r0,0 - mov.le 2,2 + mov.lt 0,r1 + mov.le 0,2 mov.hi r3,r3 mov.ls r4,r4 mov.pnz r5,r5 +# flag setting mov.f r0,r1 mov.f r2,1 - mov.f 1,r3 mov.f 0,r4 mov.f r5,512 - mov.f 512,512 +# conditional execution + flag setting mov.eq.f r0,r1 mov.ne.f r1,0 + mov.lt.f 0,r2 + mov.gt.f 0,r2 + mov.le.f r0,512 + mov.ge.f 0,r2 + mov.n.f 0,512 diff --git a/gas/testsuite/gas/arc/nop.d b/gas/testsuite/gas/arc/nop.d index 1a714cd970..32e03758a9 100644 --- a/gas/testsuite/gas/arc/nop.d +++ b/gas/testsuite/gas/arc/nop.d @@ -1,9 +1,7 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: ff ff ff 7f 7fffffff nop +0x00000000 78e0 nop_s diff --git a/gas/testsuite/gas/arc/nop.s b/gas/testsuite/gas/arc/nop.s index 02b2681855..615694a470 100644 --- a/gas/testsuite/gas/arc/nop.s +++ b/gas/testsuite/gas/arc/nop.s @@ -1,3 +1,3 @@ # nop test - nop + nop_s diff --git a/gas/testsuite/gas/arc/or.d b/gas/testsuite/gas/arc/or.d index 11e6f3c133..33232d53dc 100644 --- a/gas/testsuite/gas/arc/or.d +++ b/gas/testsuite/gas/arc/or.d @@ -1,85 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 84 00 68 68008400 or r0,r1,r2 - 4: 00 b8 4d 6b 6b4db800 or gp,fp,sp - 8: 00 3e af 6b 6baf3e00 or ilink1,ilink2,blink - c: 00 f8 1d 6f 6f1df800 or r56,r59,lp_count - 10: 00 fe 00 68 6800fe00 or r0,r1,0 - 14: 00 84 1f 68 681f8400 or r0,0,r2 - 18: 00 84 e0 6f 6fe08400 or 0,r1,r2 - 1c: ff ff 00 68 6800ffff or r0,r1,-1 - 20: ff 85 1f 68 681f85ff or r0,-1,r2 - 24: 00 84 e0 6f 6fe08400 or 0,r1,r2 - 28: ff fe 00 68 6800feff or r0,r1,255 - 2c: ff 84 1f 68 681f84ff or r0,255,r2 - 30: 00 84 e0 6f 6fe08400 or 0,r1,r2 - 34: 00 ff 00 68 6800ff00 or r0,r1,-256 - 38: 00 85 1f 68 681f8500 or r0,-256,r2 - 3c: 00 84 e0 6f 6fe08400 or 0,r1,r2 - 40: 00 fc 00 68 6800fc00 or r0,r1,0x100 - 44: 00 01 00 00 - 48: 00 04 1f 68 681f0400 or r0,0xffff_feff,r2 - 4c: ff fe ff ff - 50: ff fc 1f 68 681ffcff or r0,255,0x100 - 54: 00 01 00 00 - 58: ff 7e 1f 68 681f7eff or r0,0x100,255 - 5c: 00 01 00 00 - 60: 00 fc 00 68 6800fc00 or r0,r1,0 - 64: 00 00 00 00 - 64: R_ARC_32 foo - 68: 00 84 00 68 68008400 or r0,r1,r2 - 6c: 00 0a 62 68 68620a00 or r3,r4,r5 - 70: 01 90 c3 68 68c39001 or.z r6,r7,r8 - 74: 01 16 25 69 69251601 or.z r9,r10,r11 - 78: 02 9c 86 69 69869c02 or.nz r12,r13,r14 - 7c: 02 22 e8 69 69e82202 or.nz r15,r16,r17 - 80: 03 a8 49 6a 6a49a803 or.p r18,r19,r20 - 84: 03 2e ab 6a 6aab2e03 or.p r21,r22,r23 - 88: 04 b4 0c 6b 6b0cb404 or.n r24,r25,gp - 8c: 04 3a 6e 6b 6b6e3a04 or.n fp,sp,ilink1 - 90: 05 c0 cf 6b 6bcfc005 or.c ilink2,blink,r32 - 94: 05 46 31 6c 6c314605 or.c r33,r34,r35 - 98: 05 cc 92 6c 6c92cc05 or.c r36,r37,r38 - 9c: 06 52 f4 6c 6cf45206 or.nc r39,r40,r41 - a0: 06 d8 55 6d 6d55d806 or.nc r42,r43,r44 - a4: 06 5e b7 6d 6db75e06 or.nc r45,r46,r47 - a8: 07 e4 18 6e 6e18e407 or.v r48,r49,r50 - ac: 07 6a 1a 6f 6f1a6a07 or.v r56,r52,r53 - b0: 08 f0 1b 6f 6f1bf008 or.nv r56,r55,r56 - b4: 08 76 1d 6f 6f1d7608 or.nv r56,r58,r59 - b8: 09 00 9e 6f 6f9e0009 or.gt lp_count,lp_count,r0 - bc: 0a 7c 00 68 68007c0a or.ge r0,r0,0 - c0: 00 00 00 00 - c4: 0b 02 3f 68 683f020b or.lt r1,1,r1 - c8: 01 00 00 00 - cc: 0d 06 7f 68 687f060d or.hi r3,3,r3 - d0: 03 00 00 00 - d4: 0e 08 df 6f 6fdf080e or.ls 0,4,r4 - d8: 04 00 00 00 - dc: 0f fc c2 6f 6fc2fc0f or.pnz 0,r5,5 - e0: 05 00 00 00 - e4: 00 85 00 68 68008500 or.f r0,r1,r2 - e8: 01 fa 00 68 6800fa01 or.f r0,r1,1 - ec: 01 84 1e 68 681e8401 or.f r0,1,r2 - f0: 00 85 e0 6f 6fe08500 or.f 0,r1,r2 - f4: 00 fd 00 68 6800fd00 or.f r0,r1,0x200 - f8: 00 02 00 00 - fc: 00 05 1f 68 681f0500 or.f r0,0x200,r2 - 100: 00 02 00 00 - 104: 01 85 00 68 68008501 or.z.f r0,r1,r2 - 108: 02 fd 00 68 6800fd02 or.nz.f r0,r1,0 - 10c: 00 00 00 00 - 110: 0b 05 1f 68 681f050b or.lt.f r0,0,r2 - 114: 00 00 00 00 - 118: 09 85 c0 6f 6fc08509 or.gt.f 0,r1,r2 - 11c: 00 00 00 00 00000000 - 120: 0c fd 00 68 6800fd0c or.le.f r0,r1,0x200 - 124: 00 02 00 00 - 128: 0a 05 1f 68 681f050a or.ge.f r0,0x200,r2 - 12c: 00 02 00 00 +0x[0-9a-f]+ 2105 0080 or r0,r1,r2 +0x[0-9a-f]+ 2305 371a or gp,fp,sp +0x[0-9a-f]+ 2605 37dd or ilink,r30,blink +0x[0-9a-f]+ 2145 0000 or r0,r1,0 +0x[0-9a-f]+ 2605 7080 0000 0000 or r0,0,r2 +0x[0-9a-f]+ 2105 00be or 0,r1,r2 +0x[0-9a-f]+ 2105 0f80 ffff ffff or r0,r1,0xffffffff +0x[0-9a-f]+ 2605 7080 ffff ffff or r0,0xffffffff,r2 +0x[0-9a-f]+ 2105 0f80 0000 00ff or r0,r1,0xff +0x[0-9a-f]+ 2605 7080 0000 00ff or r0,0xff,r2 +0x[0-9a-f]+ 2105 0f80 ffff ff00 or r0,r1,0xffffff00 +0x[0-9a-f]+ 2605 7080 ffff ff00 or r0,0xffffff00,r2 +0x[0-9a-f]+ 2105 0f80 0000 0100 or r0,r1,0x100 +0x[0-9a-f]+ 2605 7080 ffff feff or r0,0xfffffeff,r2 +0x[0-9a-f]+ 2605 7f80 0000 0100 or r0,0x100,0x100 +0x[0-9a-f]+ 2105 0f80 0000 0000 or r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 20c5 0080 or r0,r0,r2 +0x[0-9a-f]+ 23c5 0140 or r3,r3,r5 +0x[0-9a-f]+ 26c5 0201 or.eq r6,r6,r8 +0x[0-9a-f]+ 21c5 12c1 or.eq r9,r9,r11 +0x[0-9a-f]+ 24c5 1382 or.ne r12,r12,r14 +0x[0-9a-f]+ 27c5 1442 or.ne r15,r15,r17 +0x[0-9a-f]+ 22c5 2503 or.p r18,r18,r20 +0x[0-9a-f]+ 25c5 25c3 or.p r21,r21,r23 +0x[0-9a-f]+ 20c5 3684 or.n r24,r24,gp +0x[0-9a-f]+ 23c5 3744 or.n fp,fp,ilink +0x[0-9a-f]+ 26c5 37c5 or.c r30,r30,blink +0x[0-9a-f]+ 23c5 00c5 or.c r3,r3,r3 +0x[0-9a-f]+ 23c5 0205 or.c r3,r3,r8 +0x[0-9a-f]+ 23c5 0106 or.nc r3,r3,r4 +0x[0-9a-f]+ 24c5 0106 or.nc r4,r4,r4 +0x[0-9a-f]+ 24c5 01c6 or.nc r4,r4,r7 +0x[0-9a-f]+ 24c5 0147 or.v r4,r4,r5 +0x[0-9a-f]+ 25c5 0147 or.v r5,r5,r5 +0x[0-9a-f]+ 25c5 0148 or.nv r5,r5,r5 +0x[0-9a-f]+ 25c5 0148 or.nv r5,r5,r5 +0x[0-9a-f]+ 26c5 0009 or.gt r6,r6,r0 +0x[0-9a-f]+ 20c5 002a or.ge r0,r0,0 +0x[0-9a-f]+ 21c5 006b or.lt r1,r1,0x1 +0x[0-9a-f]+ 23c5 00ed or.hi r3,r3,0x3 +0x[0-9a-f]+ 24c5 012e or.ls r4,r4,0x4 +0x[0-9a-f]+ 25c5 016f or.pnz r5,r5,0x5 +0x[0-9a-f]+ 2105 8080 or.f r0,r1,r2 +0x[0-9a-f]+ 2145 8040 or.f r0,r1,0x1 +0x[0-9a-f]+ 2605 f080 0000 0001 or.f r0,0x1,r2 +0x[0-9a-f]+ 2105 80be or.f 0,r1,r2 +0x[0-9a-f]+ 2105 8f80 0000 0200 or.f r0,r1,0x200 +0x[0-9a-f]+ 2605 f080 0000 0200 or.f r0,0x200,r2 +0x[0-9a-f]+ 21c5 8081 or.f.eq r1,r1,r2 +0x[0-9a-f]+ 20c5 8022 or.f.ne r0,r0,0 +0x[0-9a-f]+ 22c5 808b or.f.lt r2,r2,r2 +0x[0-9a-f]+ 26c5 f0a9 0000 0001 or.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 26c5 ff8c 0000 0200 or.f.le 0,0x200,0x200 +0x[0-9a-f]+ 26c5 f0aa 0000 0200 or.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/or.s b/gas/testsuite/gas/arc/or.s index e3633526fe..337e3aa86b 100644 --- a/gas/testsuite/gas/arc/or.s +++ b/gas/testsuite/gas/arc/or.s @@ -3,55 +3,50 @@ or r0,r1,r2 or r26,fp,sp or ilink1,ilink2,blink - or r56,r59,lp_count or r0,r1,0 or r0,0,r2 or 0,r1,r2 or r0,r1,-1 or r0,-1,r2 - or -1,r1,r2 or r0,r1,255 or r0,255,r2 - or 255,r1,r2 or r0,r1,-256 or r0,-256,r2 - or -256,r1,r2 or r0,r1,256 or r0,-257,r2 - or r0,255,256 - or r0,256,255 + or r0,256,256 or r0,r1,foo - or.al r0,r1,r2 - or.ra r3,r4,r5 - or.eq r6,r7,r8 - or.z r9,r10,r11 - or.ne r12,r13,r14 - or.nz r15,r16,r17 - or.pl r18,r19,r20 - or.p r21,r22,r23 - or.mi r24,r25,r26 - or.n r27,r28,r29 - or.cs r30,r31,r32 - or.c r33,r34,r35 - or.lo r36,r37,r38 - or.cc r39,r40,r41 - or.nc r42,r43,r44 - or.hs r45,r46,r47 - or.vs r48,r49,r50 - or.v r56,r52,r53 - or.vc r56,r55,r56 - or.nv r56,r58,r59 - or.gt r60,r60,r0 + or.al r0,r0,r2 + or.ra r3,r3,r5 + or.eq r6,r6,r8 + or.z r9,r9,r11 + or.ne r12,r12,r14 + or.nz r15,r15,r17 + or.pl r18,r18,r20 + or.p r21,r21,r23 + or.mi r24,r24,r26 + or.n r27,r27,r29 + or.cs r30,r30,r31 + or.c r3,r3,r3 + or.lo r3,r3,r8 + or.cc r3,r3,r4 + or.nc r4,r4,r4 + or.hs r4,r4,r7 + or.vs r4,r4,r5 + or.v r5,r5,r5 + or.vc r5,r5,r5 + or.nv r5,r5,r5 + or.gt r6,r6,r0 or.ge r0,r0,0 - or.lt r1,1,r1 - or.hi r3,3,r3 - or.ls 4,4,r4 - or.pnz 5,r5,5 + or.lt r1,r1,1 + or.hi r3,r3,3 + or.ls r4,r4,4 + or.pnz r5,r5,5 or.f r0,r1,r2 or.f r0,r1,1 @@ -60,9 +55,9 @@ or.f r0,r1,512 or.f r0,512,r2 - or.eq.f r0,r1,r2 - or.ne.f r0,r1,0 - or.lt.f r0,0,r2 - or.gt.f 0,r1,r2 - or.le.f r0,r1,512 - or.ge.f r0,512,r2 + or.eq.f r1,r1,r2 + or.ne.f r0,r0,0 + or.lt.f r2,r2,r2 + or.gt.f 0,1,2 + or.le.f 0,512,512 + or.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/rlc.d b/gas/testsuite/gas/arc/rlc.d index e83ddc477e..f9d42b3e5e 100644 --- a/gas/testsuite/gas/arc/rlc.d +++ b/gas/testsuite/gas/arc/rlc.d @@ -1,68 +1,22 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 82 00 48 48008200 rlc r0,r1 - 4: 00 38 6e 4b 4b6e3800 rlc fp,sp - 8: 00 fe 1f 48 481ffe00 rlc r0,0 - c: ff ff 3f 48 483fffff rlc r1,-1 - 10: 00 04 e1 4f 4fe10400 rlc 0,r2 - 14: 00 86 e1 4f 4fe18600 rlc 0,r3 - 18: ff fe 9f 48 489ffeff rlc r4,255 - 1c: 00 8a e2 4f 4fe28a00 rlc 0,r5 - 20: 00 ff df 48 48dfff00 rlc r6,-256 - 24: 00 8e e3 4f 4fe38e00 rlc 0,r7 - 28: 00 7c 1f 49 491f7c00 rlc r8,0x100 - 2c: 00 01 00 00 - 30: 00 7c 3f 49 493f7c00 rlc r9,0xffff_feff - 34: ff fe ff ff - 38: 00 7c 7f 49 497f7c00 rlc r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 7c ff 4f 4fff7c00 rlc 0,0x100 - 44: 00 01 00 00 - 48: 00 7c 1f 48 481f7c00 rlc r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 00 82 00 48 48008200 rlc r0,r1 - 54: 00 08 62 48 48620800 rlc r3,r4 - 58: 01 8e c3 48 48c38e01 rlc.z r6,r7 - 5c: 01 14 25 49 49251401 rlc.z r9,r10 - 60: 02 9a 86 49 49869a02 rlc.nz r12,r13 - 64: 02 20 e8 49 49e82002 rlc.nz r15,r16 - 68: 03 a6 49 4a 4a49a603 rlc.p r18,r19 - 6c: 03 2c ab 4a 4aab2c03 rlc.p r21,r22 - 70: 04 b2 0c 4b 4b0cb204 rlc.n r24,r25 - 74: 04 38 6e 4b 4b6e3804 rlc.n fp,sp - 78: 05 be cf 4b 4bcfbe05 rlc.c ilink2,blink - 7c: 05 44 31 4c 4c314405 rlc.c r33,r34 - 80: 05 ca 92 4c 4c92ca05 rlc.c r36,r37 - 84: 06 50 f4 4c 4cf45006 rlc.nc r39,r40 - 88: 06 d6 55 4d 4d55d606 rlc.nc r42,r43 - 8c: 06 5c b7 4d 4db75c06 rlc.nc r45,r46 - 90: 07 e2 18 4e 4e18e207 rlc.v r48,r49 - 94: 07 64 39 4e 4e396407 rlc.v r49,r50 - 98: 08 ee 3b 4e 4e3bee08 rlc.nv r49,r55 - 9c: 08 74 3d 4e 4e3d7408 rlc.nv r49,r58 - a0: 09 78 9e 4f 4f9e7809 rlc.gt lp_count,lp_count - a4: 0a 7c 1f 48 481f7c0a rlc.ge r0,0 - a8: 00 00 00 00 - ac: 0c 7c df 4f 4fdf7c0c rlc.le 0,2 - b0: 02 00 00 00 - b4: 0d 86 61 48 4861860d rlc.hi r3,r3 - b8: 0e 08 82 48 4882080e rlc.ls r4,r4 - bc: 0f 8a a2 48 48a28a0f rlc.pnz r5,r5 - c0: 00 83 00 48 48008300 rlc.f r0,r1 - c4: 01 fa 5e 48 485efa01 rlc.f r2,1 - c8: 00 87 e1 4f 4fe18700 rlc.f 0,r3 - cc: 00 09 e2 4f 4fe20900 rlc.f 0,r4 - d0: 00 7d bf 48 48bf7d00 rlc.f r5,0x200 - d4: 00 02 00 00 - d8: 00 7d df 4f 4fdf7d00 rlc.f 0,0x200 - dc: 00 02 00 00 - e0: 01 83 00 48 48008301 rlc.z.f r0,r1 - e4: 02 7d 3f 48 483f7d02 rlc.nz.f r1,0 - e8: 00 00 00 00 +0x[0-9a-f]+ 202f 004b rlc r0,r1 +0x[0-9a-f]+ 232f 370b rlc fp,sp +0x[0-9a-f]+ 206f 000b rlc r0,0 +0x[0-9a-f]+ 212f 0f8b ffff ffff rlc r1,0xffffffff +0x[0-9a-f]+ 262f 708b rlc 0,r2 +0x[0-9a-f]+ 242f 0f8b 0000 00ff rlc r4,0xff +0x[0-9a-f]+ 262f 0f8b ffff ff00 rlc r6,0xffffff00 +0x[0-9a-f]+ 202f 1f8b 0000 0100 rlc r8,0x100 +0x[0-9a-f]+ 212f 1f8b ffff feff rlc r9,0xfffffeff +0x[0-9a-f]+ 232f 1f8b 4242 4242 rlc r11,0x42424242 +0x[0-9a-f]+ 202f 0f8b 0000 0000 rlc r0,0 + 44: ARC_32_ME foo +0x[0-9a-f]+ 202f 804b rlc.f r0,r1 +0x[0-9a-f]+ 226f 804b rlc.f r2,0x1 +0x[0-9a-f]+ 262f f10b rlc.f 0,r4 +0x[0-9a-f]+ 252f 8f8b 0000 0200 rlc.f r5,0x200 diff --git a/gas/testsuite/gas/arc/rlc.s b/gas/testsuite/gas/arc/rlc.s index 3e5d0932be..29d92eb764 100644 --- a/gas/testsuite/gas/arc/rlc.s +++ b/gas/testsuite/gas/arc/rlc.s @@ -6,53 +6,16 @@ rlc r0,0 rlc r1,-1 rlc 0,r2 - rlc -1,r3 rlc r4,255 - rlc 255,r5 rlc r6,-256 - rlc -256,r7 rlc r8,256 rlc r9,-257 rlc r11,0x42424242 - rlc 255,256 - rlc r0,foo - rlc.al r0,r1 - rlc.ra r3,r4 - rlc.eq r6,r7 - rlc.z r9,r10 - rlc.ne r12,r13 - rlc.nz r15,r16 - rlc.pl r18,r19 - rlc.p r21,r22 - rlc.mi r24,r25 - rlc.n r27,r28 - rlc.cs r30,r31 - rlc.c r33,r34 - rlc.lo r36,r37 - rlc.cc r39,r40 - rlc.nc r42,r43 - rlc.hs r45,r46 - rlc.vs r48,r49 - rlc.v r49,r50 - rlc.vc r49,r55 - rlc.nv r49,r58 - rlc.gt r60,r60 - rlc.ge r0,0 - rlc.le 2,2 - rlc.hi r3,r3 - rlc.ls r4,r4 - rlc.pnz r5,r5 - rlc.f r0,r1 rlc.f r2,1 - rlc.f 1,r3 rlc.f 0,r4 rlc.f r5,512 - rlc.f 512,512 - - rlc.eq.f r0,r1 - rlc.ne.f r1,0 diff --git a/gas/testsuite/gas/arc/ror.d b/gas/testsuite/gas/arc/ror.d index 691736b6d0..cd2e92f7d6 100644 --- a/gas/testsuite/gas/arc/ror.d +++ b/gas/testsuite/gas/arc/ror.d @@ -1,51 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 86 00 18 18008600 ror r0,r1 - 4: 00 06 6e 1b 1b6e0600 ror fp,sp - 8: 00 86 1f 18 181f8600 ror r0,0 - c: ff 87 3f 18 183f87ff ror r1,-1 - 10: 00 06 e1 1f 1fe10600 ror 0,r2 - 14: 00 86 e1 1f 1fe18600 ror 0,r3 - 18: ff 86 9f 18 189f86ff ror r4,255 - 1c: 00 86 e2 1f 1fe28600 ror 0,r5 - 20: 00 87 df 18 18df8700 ror r6,-256 - 24: 00 86 e3 1f 1fe38600 ror 0,r7 - 28: 00 06 1f 19 191f0600 ror r8,0x100 - 2c: 00 01 00 00 - 30: 00 06 3f 19 193f0600 ror r9,0xffff_feff - 34: ff fe ff ff - 38: 00 06 7f 19 197f0600 ror r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 06 ff 1f 1fff0600 ror 0,0x100 - 44: 00 01 00 00 - 48: 00 06 1f 18 181f0600 ror r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 01 86 45 19 19458601 ror.z r10,r11 - 54: 02 86 86 19 19868602 ror.nz r12,r13 - 58: 0b 06 df 19 19df060b ror.lt r14,0 - 5c: 00 00 00 00 - 60: 09 06 ff 19 19ff0609 ror.gt r15,0x200 - 64: 00 02 00 00 - 68: 00 87 00 18 18008700 ror.f r0,r1 - 6c: 01 86 5e 18 185e8601 ror.f r2,1 - 70: 00 07 e2 1f 1fe20700 ror.f 0,r4 - 74: 00 07 bf 18 18bf0700 ror.f r5,0x200 - 78: 00 02 00 00 - 7c: 00 07 df 1f 1fdf0700 ror.f 0,0x200 - 80: 00 02 00 00 - 84: 01 87 00 18 18008701 ror.z.f r0,r1 - 88: 02 07 3f 18 183f0702 ror.nz.f r1,0 - 8c: 00 00 00 00 - 90: 0b 07 c1 1f 1fc1070b ror.lt.f 0,r2 - 94: 00 00 00 00 00000000 - 98: 0c 07 1f 18 181f070c ror.le.f r0,0x200 - 9c: 00 02 00 00 - a0: 04 07 df 1f 1fdf0704 ror.n.f 0,0x200 - a4: 00 02 00 00 +0x[0-9a-f]+ 2903 0080 ror r0,r1,r2 +0x[0-9a-f]+ 2b03 371a ror gp,fp,sp +0x[0-9a-f]+ 2e03 37dd ror ilink,r30,blink +0x[0-9a-f]+ 2943 0000 ror r0,r1,0 +0x[0-9a-f]+ 2e03 7080 0000 0000 ror r0,0,r2 +0x[0-9a-f]+ 2903 00be ror 0,r1,r2 +0x[0-9a-f]+ 2903 0f80 ffff ffff ror r0,r1,0xffffffff +0x[0-9a-f]+ 2e03 7080 ffff ffff ror r0,0xffffffff,r2 +0x[0-9a-f]+ 2903 0f80 0000 00ff ror r0,r1,0xff +0x[0-9a-f]+ 2e03 7080 0000 00ff ror r0,0xff,r2 +0x[0-9a-f]+ 2903 0f80 ffff ff00 ror r0,r1,0xffffff00 +0x[0-9a-f]+ 2e03 7080 ffff ff00 ror r0,0xffffff00,r2 +0x[0-9a-f]+ 2903 0f80 0000 0100 ror r0,r1,0x100 +0x[0-9a-f]+ 2e03 7080 ffff feff ror r0,0xfffffeff,r2 +0x[0-9a-f]+ 2e03 7f80 0000 0100 ror r0,0x100,0x100 +0x[0-9a-f]+ 2903 0f80 0000 0000 ror r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 28c3 0080 ror r0,r0,r2 +0x[0-9a-f]+ 2bc3 0140 ror r3,r3,r5 +0x[0-9a-f]+ 2ec3 0201 ror.eq r6,r6,r8 +0x[0-9a-f]+ 29c3 12c1 ror.eq r9,r9,r11 +0x[0-9a-f]+ 2cc3 1382 ror.ne r12,r12,r14 +0x[0-9a-f]+ 2fc3 1442 ror.ne r15,r15,r17 +0x[0-9a-f]+ 2ac3 2503 ror.p r18,r18,r20 +0x[0-9a-f]+ 2dc3 25c3 ror.p r21,r21,r23 +0x[0-9a-f]+ 28c3 3684 ror.n r24,r24,gp +0x[0-9a-f]+ 2bc3 3744 ror.n fp,fp,ilink +0x[0-9a-f]+ 2ec3 37c5 ror.c r30,r30,blink +0x[0-9a-f]+ 2bc3 00c5 ror.c r3,r3,r3 +0x[0-9a-f]+ 2bc3 0205 ror.c r3,r3,r8 +0x[0-9a-f]+ 2bc3 0106 ror.nc r3,r3,r4 +0x[0-9a-f]+ 2cc3 0106 ror.nc r4,r4,r4 +0x[0-9a-f]+ 2cc3 01c6 ror.nc r4,r4,r7 +0x[0-9a-f]+ 2cc3 0147 ror.v r4,r4,r5 +0x[0-9a-f]+ 2dc3 0147 ror.v r5,r5,r5 +0x[0-9a-f]+ 2dc3 0148 ror.nv r5,r5,r5 +0x[0-9a-f]+ 2dc3 0148 ror.nv r5,r5,r5 +0x[0-9a-f]+ 2ec3 0009 ror.gt r6,r6,r0 +0x[0-9a-f]+ 28c3 002a ror.ge r0,r0,0 +0x[0-9a-f]+ 29c3 006b ror.lt r1,r1,0x1 +0x[0-9a-f]+ 2bc3 00ed ror.hi r3,r3,0x3 +0x[0-9a-f]+ 2cc3 012e ror.ls r4,r4,0x4 +0x[0-9a-f]+ 2dc3 016f ror.pnz r5,r5,0x5 +0x[0-9a-f]+ 2903 8080 ror.f r0,r1,r2 +0x[0-9a-f]+ 2943 8040 ror.f r0,r1,0x1 +0x[0-9a-f]+ 2e03 f080 0000 0001 ror.f r0,0x1,r2 +0x[0-9a-f]+ 2903 80be ror.f 0,r1,r2 +0x[0-9a-f]+ 2903 8f80 0000 0200 ror.f r0,r1,0x200 +0x[0-9a-f]+ 2e03 f080 0000 0200 ror.f r0,0x200,r2 +0x[0-9a-f]+ 29c3 8081 ror.f.eq r1,r1,r2 +0x[0-9a-f]+ 28c3 8022 ror.f.ne r0,r0,0 +0x[0-9a-f]+ 2ac3 808b ror.f.lt r2,r2,r2 +0x[0-9a-f]+ 2ec3 f0a9 0000 0001 ror.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 2ec3 ff8c 0000 0200 ror.f.le 0,0x200,0x200 +0x[0-9a-f]+ 2ec3 f0aa 0000 0200 ror.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/ror.s b/gas/testsuite/gas/arc/ror.s index de2335160f..fadb6787c4 100644 --- a/gas/testsuite/gas/arc/ror.s +++ b/gas/testsuite/gas/arc/ror.s @@ -1,38 +1,63 @@ # ror test - ror r0,r1 - ror fp,sp - - ror r0,0 - ror r1,-1 - ror 0,r2 - ror -1,r3 - ror r4,255 - ror 255,r5 - ror r6,-256 - ror -256,r7 - - ror r8,256 - ror r9,-257 - ror r11,0x42424242 - - ror 255,256 - - ror r0,foo - - ror.eq r10,r11 - ror.ne r12,r13 - ror.lt r14,0 - ror.gt r15,512 - - ror.f r0,r1 - ror.f r2,1 - ror.f 0,r4 - ror.f r5,512 - ror.f 512,512 - - ror.eq.f r0,r1 - ror.ne.f r1,0 - ror.lt.f 0,r2 - ror.le.f r0,512 - ror.n.f 512,512 + ror r0,r1,r2 + ror r26,fp,sp + ror ilink1,ilink2,blink + + ror r0,r1,0 + ror r0,0,r2 + ror 0,r1,r2 + ror r0,r1,-1 + ror r0,-1,r2 + ror r0,r1,255 + ror r0,255,r2 + ror r0,r1,-256 + ror r0,-256,r2 + + ror r0,r1,256 + ror r0,-257,r2 + + ror r0,256,256 + + ror r0,r1,foo + + ror.al r0,r0,r2 + ror.ra r3,r3,r5 + ror.eq r6,r6,r8 + ror.z r9,r9,r11 + ror.ne r12,r12,r14 + ror.nz r15,r15,r17 + ror.pl r18,r18,r20 + ror.p r21,r21,r23 + ror.mi r24,r24,r26 + ror.n r27,r27,r29 + ror.cs r30,r30,r31 + ror.c r3,r3,r3 + ror.lo r3,r3,r8 + ror.cc r3,r3,r4 + ror.nc r4,r4,r4 + ror.hs r4,r4,r7 + ror.vs r4,r4,r5 + ror.v r5,r5,r5 + ror.vc r5,r5,r5 + ror.nv r5,r5,r5 + ror.gt r6,r6,r0 + ror.ge r0,r0,0 + ror.lt r1,r1,1 + ror.hi r3,r3,3 + ror.ls r4,r4,4 + ror.pnz r5,r5,5 + + ror.f r0,r1,r2 + ror.f r0,r1,1 + ror.f r0,1,r2 + ror.f 0,r1,r2 + ror.f r0,r1,512 + ror.f r0,512,r2 + + ror.eq.f r1,r1,r2 + ror.ne.f r0,r0,0 + ror.lt.f r2,r2,r2 + ror.gt.f 0,1,2 + ror.le.f 0,512,512 + ror.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/rrc.d b/gas/testsuite/gas/arc/rrc.d index 9c702cb0cd..446fc0fc3c 100644 --- a/gas/testsuite/gas/arc/rrc.d +++ b/gas/testsuite/gas/arc/rrc.d @@ -1,51 +1,22 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 88 00 18 18008800 rrc r0,r1 - 4: 00 08 6e 1b 1b6e0800 rrc fp,sp - 8: 00 88 1f 18 181f8800 rrc r0,0 - c: ff 89 3f 18 183f89ff rrc r1,-1 - 10: 00 08 e1 1f 1fe10800 rrc 0,r2 - 14: 00 88 e1 1f 1fe18800 rrc 0,r3 - 18: ff 88 9f 18 189f88ff rrc r4,255 - 1c: 00 88 e2 1f 1fe28800 rrc 0,r5 - 20: 00 89 df 18 18df8900 rrc r6,-256 - 24: 00 88 e3 1f 1fe38800 rrc 0,r7 - 28: 00 08 1f 19 191f0800 rrc r8,0x100 - 2c: 00 01 00 00 - 30: 00 08 3f 19 193f0800 rrc r9,0xffff_feff - 34: ff fe ff ff - 38: 00 08 7f 19 197f0800 rrc r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 08 ff 1f 1fff0800 rrc 0,0x100 - 44: 00 01 00 00 - 48: 00 08 1f 18 181f0800 rrc r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 01 88 45 19 19458801 rrc.z r10,r11 - 54: 02 88 86 19 19868802 rrc.nz r12,r13 - 58: 0b 08 df 19 19df080b rrc.lt r14,0 - 5c: 00 00 00 00 - 60: 09 08 ff 19 19ff0809 rrc.gt r15,0x200 - 64: 00 02 00 00 - 68: 00 89 00 18 18008900 rrc.f r0,r1 - 6c: 01 88 5e 18 185e8801 rrc.f r2,1 - 70: 00 09 e2 1f 1fe20900 rrc.f 0,r4 - 74: 00 09 bf 18 18bf0900 rrc.f r5,0x200 - 78: 00 02 00 00 - 7c: 00 09 df 1f 1fdf0900 rrc.f 0,0x200 - 80: 00 02 00 00 - 84: 01 89 00 18 18008901 rrc.z.f r0,r1 - 88: 02 09 3f 18 183f0902 rrc.nz.f r1,0 - 8c: 00 00 00 00 - 90: 0b 09 c1 1f 1fc1090b rrc.lt.f 0,r2 - 94: 00 00 00 00 00000000 - 98: 0c 09 1f 18 181f090c rrc.le.f r0,0x200 - 9c: 00 02 00 00 - a0: 04 09 df 1f 1fdf0904 rrc.n.f 0,0x200 - a4: 00 02 00 00 +0x[0-9a-f]+ 202f 0044 rrc r0,r1 +0x[0-9a-f]+ 232f 3704 rrc fp,sp +0x[0-9a-f]+ 206f 0004 rrc r0,0 +0x[0-9a-f]+ 212f 0f84 ffff ffff rrc r1,0xffffffff +0x[0-9a-f]+ 262f 7084 rrc 0,r2 +0x[0-9a-f]+ 242f 0f84 0000 00ff rrc r4,0xff +0x[0-9a-f]+ 262f 0f84 ffff ff00 rrc r6,0xffffff00 +0x[0-9a-f]+ 202f 1f84 0000 0100 rrc r8,0x100 +0x[0-9a-f]+ 212f 1f84 ffff feff rrc r9,0xfffffeff +0x[0-9a-f]+ 232f 1f84 4242 4242 rrc r11,0x42424242 +0x[0-9a-f]+ 202f 0f84 0000 0000 rrc r0,0 + 44: ARC_32_ME foo +0x[0-9a-f]+ 202f 8044 rrc.f r0,r1 +0x[0-9a-f]+ 226f 8044 rrc.f r2,0x1 +0x[0-9a-f]+ 262f f104 rrc.f 0,r4 +0x[0-9a-f]+ 252f 8f84 0000 0200 rrc.f r5,0x200 diff --git a/gas/testsuite/gas/arc/rrc.s b/gas/testsuite/gas/arc/rrc.s index c0e1780531..26f65519f4 100644 --- a/gas/testsuite/gas/arc/rrc.s +++ b/gas/testsuite/gas/arc/rrc.s @@ -6,33 +6,16 @@ rrc r0,0 rrc r1,-1 rrc 0,r2 - rrc -1,r3 rrc r4,255 - rrc 255,r5 rrc r6,-256 - rrc -256,r7 rrc r8,256 rrc r9,-257 rrc r11,0x42424242 - rrc 255,256 - rrc r0,foo - rrc.eq r10,r11 - rrc.ne r12,r13 - rrc.lt r14,0 - rrc.gt r15,512 - rrc.f r0,r1 rrc.f r2,1 rrc.f 0,r4 rrc.f r5,512 - rrc.f 512,512 - - rrc.eq.f r0,r1 - rrc.ne.f r1,0 - rrc.lt.f 0,r2 - rrc.le.f r0,512 - rrc.n.f 512,512 diff --git a/gas/testsuite/gas/arc/sbc.d b/gas/testsuite/gas/arc/sbc.d index 7fa04901cd..07c147f1aa 100644 --- a/gas/testsuite/gas/arc/sbc.d +++ b/gas/testsuite/gas/arc/sbc.d @@ -1,85 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 84 00 58 58008400 sbc r0,r1,r2 - 4: 00 b8 4d 5b 5b4db800 sbc gp,fp,sp - 8: 00 3e af 5b 5baf3e00 sbc ilink1,ilink2,blink - c: 00 f8 1d 5f 5f1df800 sbc r56,r59,lp_count - 10: 00 fe 00 58 5800fe00 sbc r0,r1,0 - 14: 00 84 1f 58 581f8400 sbc r0,0,r2 - 18: 00 84 e0 5f 5fe08400 sbc 0,r1,r2 - 1c: ff ff 00 58 5800ffff sbc r0,r1,-1 - 20: ff 85 1f 58 581f85ff sbc r0,-1,r2 - 24: 00 84 e0 5f 5fe08400 sbc 0,r1,r2 - 28: ff fe 00 58 5800feff sbc r0,r1,255 - 2c: ff 84 1f 58 581f84ff sbc r0,255,r2 - 30: 00 84 e0 5f 5fe08400 sbc 0,r1,r2 - 34: 00 ff 00 58 5800ff00 sbc r0,r1,-256 - 38: 00 85 1f 58 581f8500 sbc r0,-256,r2 - 3c: 00 84 e0 5f 5fe08400 sbc 0,r1,r2 - 40: 00 fc 00 58 5800fc00 sbc r0,r1,0x100 - 44: 00 01 00 00 - 48: 00 04 1f 58 581f0400 sbc r0,0xffff_feff,r2 - 4c: ff fe ff ff - 50: ff fc 1f 58 581ffcff sbc r0,255,0x100 - 54: 00 01 00 00 - 58: ff 7e 1f 58 581f7eff sbc r0,0x100,255 - 5c: 00 01 00 00 - 60: 00 fc 00 58 5800fc00 sbc r0,r1,0 - 64: 00 00 00 00 - 64: R_ARC_32 foo - 68: 00 84 00 58 58008400 sbc r0,r1,r2 - 6c: 00 0a 62 58 58620a00 sbc r3,r4,r5 - 70: 01 90 c3 58 58c39001 sbc.z r6,r7,r8 - 74: 01 16 25 59 59251601 sbc.z r9,r10,r11 - 78: 02 9c 86 59 59869c02 sbc.nz r12,r13,r14 - 7c: 02 22 e8 59 59e82202 sbc.nz r15,r16,r17 - 80: 03 a8 49 5a 5a49a803 sbc.p r18,r19,r20 - 84: 03 2e ab 5a 5aab2e03 sbc.p r21,r22,r23 - 88: 04 b4 0c 5b 5b0cb404 sbc.n r24,r25,gp - 8c: 04 3a 6e 5b 5b6e3a04 sbc.n fp,sp,ilink1 - 90: 05 c0 cf 5b 5bcfc005 sbc.c ilink2,blink,r32 - 94: 05 46 31 5c 5c314605 sbc.c r33,r34,r35 - 98: 05 cc 92 5c 5c92cc05 sbc.c r36,r37,r38 - 9c: 06 52 f4 5c 5cf45206 sbc.nc r39,r40,r41 - a0: 06 d8 55 5d 5d55d806 sbc.nc r42,r43,r44 - a4: 06 5e b7 5d 5db75e06 sbc.nc r45,r46,r47 - a8: 07 e4 18 5e 5e18e407 sbc.v r48,r49,r50 - ac: 07 6a 1a 5f 5f1a6a07 sbc.v r56,r52,r53 - b0: 08 f0 1b 5f 5f1bf008 sbc.nv r56,r55,r56 - b4: 08 76 1d 5f 5f1d7608 sbc.nv r56,r58,r59 - b8: 09 00 9e 5f 5f9e0009 sbc.gt lp_count,lp_count,r0 - bc: 0a 7c 00 58 58007c0a sbc.ge r0,r0,0 - c0: 00 00 00 00 - c4: 0b 02 3f 58 583f020b sbc.lt r1,1,r1 - c8: 01 00 00 00 - cc: 0d 06 7f 58 587f060d sbc.hi r3,3,r3 - d0: 03 00 00 00 - d4: 0e 08 df 5f 5fdf080e sbc.ls 0,4,r4 - d8: 04 00 00 00 - dc: 0f fc c2 5f 5fc2fc0f sbc.pnz 0,r5,5 - e0: 05 00 00 00 - e4: 00 85 00 58 58008500 sbc.f r0,r1,r2 - e8: 01 fa 00 58 5800fa01 sbc.f r0,r1,1 - ec: 01 84 1e 58 581e8401 sbc.f r0,1,r2 - f0: 00 85 e0 5f 5fe08500 sbc.f 0,r1,r2 - f4: 00 fd 00 58 5800fd00 sbc.f r0,r1,0x200 - f8: 00 02 00 00 - fc: 00 05 1f 58 581f0500 sbc.f r0,0x200,r2 - 100: 00 02 00 00 - 104: 01 85 00 58 58008501 sbc.z.f r0,r1,r2 - 108: 02 fd 00 58 5800fd02 sbc.nz.f r0,r1,0 - 10c: 00 00 00 00 - 110: 0b 05 1f 58 581f050b sbc.lt.f r0,0,r2 - 114: 00 00 00 00 - 118: 09 85 c0 5f 5fc08509 sbc.gt.f 0,r1,r2 - 11c: 00 00 00 00 00000000 - 120: 0c fd 00 58 5800fd0c sbc.le.f r0,r1,0x200 - 124: 00 02 00 00 - 128: 0a 05 1f 58 581f050a sbc.ge.f r0,0x200,r2 - 12c: 00 02 00 00 +0x[0-9a-f]+ 2103 0080 sbc r0,r1,r2 +0x[0-9a-f]+ 2303 371a sbc gp,fp,sp +0x[0-9a-f]+ 2603 37dd sbc ilink,r30,blink +0x[0-9a-f]+ 2143 0000 sbc r0,r1,0 +0x[0-9a-f]+ 2603 7080 0000 0000 sbc r0,0,r2 +0x[0-9a-f]+ 2103 00be sbc 0,r1,r2 +0x[0-9a-f]+ 2103 0f80 ffff ffff sbc r0,r1,0xffffffff +0x[0-9a-f]+ 2603 7080 ffff ffff sbc r0,0xffffffff,r2 +0x[0-9a-f]+ 2103 0f80 0000 00ff sbc r0,r1,0xff +0x[0-9a-f]+ 2603 7080 0000 00ff sbc r0,0xff,r2 +0x[0-9a-f]+ 2103 0f80 ffff ff00 sbc r0,r1,0xffffff00 +0x[0-9a-f]+ 2603 7080 ffff ff00 sbc r0,0xffffff00,r2 +0x[0-9a-f]+ 2103 0f80 0000 0100 sbc r0,r1,0x100 +0x[0-9a-f]+ 2603 7080 ffff feff sbc r0,0xfffffeff,r2 +0x[0-9a-f]+ 2603 7f80 0000 0100 sbc r0,0x100,0x100 +0x[0-9a-f]+ 2103 0f80 0000 0000 sbc r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 20c3 0080 sbc r0,r0,r2 +0x[0-9a-f]+ 23c3 0140 sbc r3,r3,r5 +0x[0-9a-f]+ 26c3 0201 sbc.eq r6,r6,r8 +0x[0-9a-f]+ 21c3 12c1 sbc.eq r9,r9,r11 +0x[0-9a-f]+ 24c3 1382 sbc.ne r12,r12,r14 +0x[0-9a-f]+ 27c3 1442 sbc.ne r15,r15,r17 +0x[0-9a-f]+ 22c3 2503 sbc.p r18,r18,r20 +0x[0-9a-f]+ 25c3 25c3 sbc.p r21,r21,r23 +0x[0-9a-f]+ 20c3 3684 sbc.n r24,r24,gp +0x[0-9a-f]+ 23c3 3744 sbc.n fp,fp,ilink +0x[0-9a-f]+ 26c3 37c5 sbc.c r30,r30,blink +0x[0-9a-f]+ 23c3 00c5 sbc.c r3,r3,r3 +0x[0-9a-f]+ 23c3 0205 sbc.c r3,r3,r8 +0x[0-9a-f]+ 23c3 0106 sbc.nc r3,r3,r4 +0x[0-9a-f]+ 24c3 0106 sbc.nc r4,r4,r4 +0x[0-9a-f]+ 24c3 01c6 sbc.nc r4,r4,r7 +0x[0-9a-f]+ 24c3 0147 sbc.v r4,r4,r5 +0x[0-9a-f]+ 25c3 0147 sbc.v r5,r5,r5 +0x[0-9a-f]+ 25c3 0148 sbc.nv r5,r5,r5 +0x[0-9a-f]+ 25c3 0148 sbc.nv r5,r5,r5 +0x[0-9a-f]+ 26c3 0009 sbc.gt r6,r6,r0 +0x[0-9a-f]+ 20c3 002a sbc.ge r0,r0,0 +0x[0-9a-f]+ 21c3 006b sbc.lt r1,r1,0x1 +0x[0-9a-f]+ 23c3 00ed sbc.hi r3,r3,0x3 +0x[0-9a-f]+ 24c3 012e sbc.ls r4,r4,0x4 +0x[0-9a-f]+ 25c3 016f sbc.pnz r5,r5,0x5 +0x[0-9a-f]+ 2103 8080 sbc.f r0,r1,r2 +0x[0-9a-f]+ 2143 8040 sbc.f r0,r1,0x1 +0x[0-9a-f]+ 2603 f080 0000 0001 sbc.f r0,0x1,r2 +0x[0-9a-f]+ 2103 80be sbc.f 0,r1,r2 +0x[0-9a-f]+ 2103 8f80 0000 0200 sbc.f r0,r1,0x200 +0x[0-9a-f]+ 2603 f080 0000 0200 sbc.f r0,0x200,r2 +0x[0-9a-f]+ 21c3 8081 sbc.f.eq r1,r1,r2 +0x[0-9a-f]+ 20c3 8022 sbc.f.ne r0,r0,0 +0x[0-9a-f]+ 22c3 808b sbc.f.lt r2,r2,r2 +0x[0-9a-f]+ 26c3 f0a9 0000 0001 sbc.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 26c3 ff8c 0000 0200 sbc.f.le 0,0x200,0x200 +0x[0-9a-f]+ 26c3 f0aa 0000 0200 sbc.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/sbc.s b/gas/testsuite/gas/arc/sbc.s index 8eb96464eb..dd18c28080 100644 --- a/gas/testsuite/gas/arc/sbc.s +++ b/gas/testsuite/gas/arc/sbc.s @@ -3,55 +3,50 @@ sbc r0,r1,r2 sbc r26,fp,sp sbc ilink1,ilink2,blink - sbc r56,r59,lp_count sbc r0,r1,0 sbc r0,0,r2 sbc 0,r1,r2 sbc r0,r1,-1 sbc r0,-1,r2 - sbc -1,r1,r2 sbc r0,r1,255 sbc r0,255,r2 - sbc 255,r1,r2 sbc r0,r1,-256 sbc r0,-256,r2 - sbc -256,r1,r2 sbc r0,r1,256 sbc r0,-257,r2 - sbc r0,255,256 - sbc r0,256,255 + sbc r0,256,256 sbc r0,r1,foo - sbc.al r0,r1,r2 - sbc.ra r3,r4,r5 - sbc.eq r6,r7,r8 - sbc.z r9,r10,r11 - sbc.ne r12,r13,r14 - sbc.nz r15,r16,r17 - sbc.pl r18,r19,r20 - sbc.p r21,r22,r23 - sbc.mi r24,r25,r26 - sbc.n r27,r28,r29 - sbc.cs r30,r31,r32 - sbc.c r33,r34,r35 - sbc.lo r36,r37,r38 - sbc.cc r39,r40,r41 - sbc.nc r42,r43,r44 - sbc.hs r45,r46,r47 - sbc.vs r48,r49,r50 - sbc.v r56,r52,r53 - sbc.vc r56,r55,r56 - sbc.nv r56,r58,r59 - sbc.gt r60,r60,r0 + sbc.al r0,r0,r2 + sbc.ra r3,r3,r5 + sbc.eq r6,r6,r8 + sbc.z r9,r9,r11 + sbc.ne r12,r12,r14 + sbc.nz r15,r15,r17 + sbc.pl r18,r18,r20 + sbc.p r21,r21,r23 + sbc.mi r24,r24,r26 + sbc.n r27,r27,r29 + sbc.cs r30,r30,r31 + sbc.c r3,r3,r3 + sbc.lo r3,r3,r8 + sbc.cc r3,r3,r4 + sbc.nc r4,r4,r4 + sbc.hs r4,r4,r7 + sbc.vs r4,r4,r5 + sbc.v r5,r5,r5 + sbc.vc r5,r5,r5 + sbc.nv r5,r5,r5 + sbc.gt r6,r6,r0 sbc.ge r0,r0,0 - sbc.lt r1,1,r1 - sbc.hi r3,3,r3 - sbc.ls 4,4,r4 - sbc.pnz 5,r5,5 + sbc.lt r1,r1,1 + sbc.hi r3,r3,3 + sbc.ls r4,r4,4 + sbc.pnz r5,r5,5 sbc.f r0,r1,r2 sbc.f r0,r1,1 @@ -60,9 +55,9 @@ sbc.f r0,r1,512 sbc.f r0,512,r2 - sbc.eq.f r0,r1,r2 - sbc.ne.f r0,r1,0 - sbc.lt.f r0,0,r2 - sbc.gt.f 0,r1,r2 - sbc.le.f r0,r1,512 - sbc.ge.f r0,512,r2 + sbc.eq.f r1,r1,r2 + sbc.ne.f r0,r0,0 + sbc.lt.f r2,r2,r2 + sbc.gt.f 0,1,2 + sbc.le.f 0,512,512 + sbc.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/sexb.d b/gas/testsuite/gas/arc/sexb.d index 96d35d69e1..bbc4ca588f 100644 --- a/gas/testsuite/gas/arc/sexb.d +++ b/gas/testsuite/gas/arc/sexb.d @@ -1,51 +1,22 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 8a 00 18 18008a00 sexb r0,r1 - 4: 00 0a 6e 1b 1b6e0a00 sexb fp,sp - 8: 00 8a 1f 18 181f8a00 sexb r0,0 - c: ff 8b 3f 18 183f8bff sexb r1,-1 - 10: 00 0a e1 1f 1fe10a00 sexb 0,r2 - 14: 00 8a e1 1f 1fe18a00 sexb 0,r3 - 18: ff 8a 9f 18 189f8aff sexb r4,255 - 1c: 00 8a e2 1f 1fe28a00 sexb 0,r5 - 20: 00 8b df 18 18df8b00 sexb r6,-256 - 24: 00 8a e3 1f 1fe38a00 sexb 0,r7 - 28: 00 0a 1f 19 191f0a00 sexb r8,0x100 - 2c: 00 01 00 00 - 30: 00 0a 3f 19 193f0a00 sexb r9,0xffff_feff - 34: ff fe ff ff - 38: 00 0a 7f 19 197f0a00 sexb r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 0a ff 1f 1fff0a00 sexb 0,0x100 - 44: 00 01 00 00 - 48: 00 0a 1f 18 181f0a00 sexb r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 01 8a 45 19 19458a01 sexb.z r10,r11 - 54: 02 8a 86 19 19868a02 sexb.nz r12,r13 - 58: 0b 0a df 19 19df0a0b sexb.lt r14,0 - 5c: 00 00 00 00 - 60: 09 0a ff 19 19ff0a09 sexb.gt r15,0x200 - 64: 00 02 00 00 - 68: 00 8b 00 18 18008b00 sexb.f r0,r1 - 6c: 01 8a 5e 18 185e8a01 sexb.f r2,1 - 70: 00 0b e2 1f 1fe20b00 sexb.f 0,r4 - 74: 00 0b bf 18 18bf0b00 sexb.f r5,0x200 - 78: 00 02 00 00 - 7c: 00 0b df 1f 1fdf0b00 sexb.f 0,0x200 - 80: 00 02 00 00 - 84: 01 8b 00 18 18008b01 sexb.z.f r0,r1 - 88: 02 0b 3f 18 183f0b02 sexb.nz.f r1,0 - 8c: 00 00 00 00 - 90: 0b 0b c1 1f 1fc10b0b sexb.lt.f 0,r2 - 94: 00 00 00 00 00000000 - 98: 0c 0b 1f 18 181f0b0c sexb.le.f r0,0x200 - 9c: 00 02 00 00 - a0: 04 0b df 1f 1fdf0b04 sexb.n.f 0,0x200 - a4: 00 02 00 00 +0x[0-9a-f]+ 202f 0045 sexb r0,r1 +0x[0-9a-f]+ 232f 3705 sexb fp,sp +0x[0-9a-f]+ 206f 0005 sexb r0,0 +0x[0-9a-f]+ 212f 0f85 ffff ffff sexb r1,0xffffffff +0x[0-9a-f]+ 262f 7085 sexb 0,r2 +0x[0-9a-f]+ 242f 0f85 0000 00ff sexb r4,0xff +0x[0-9a-f]+ 262f 0f85 ffff ff00 sexb r6,0xffffff00 +0x[0-9a-f]+ 202f 1f85 0000 0100 sexb r8,0x100 +0x[0-9a-f]+ 212f 1f85 ffff feff sexb r9,0xfffffeff +0x[0-9a-f]+ 232f 1f85 4242 4242 sexb r11,0x42424242 +0x[0-9a-f]+ 202f 0f85 0000 0000 sexb r0,0 + 44: ARC_32_ME foo +0x[0-9a-f]+ 202f 8045 sexb.f r0,r1 +0x[0-9a-f]+ 226f 8045 sexb.f r2,0x1 +0x[0-9a-f]+ 262f f105 sexb.f 0,r4 +0x[0-9a-f]+ 252f 8f85 0000 0200 sexb.f r5,0x200 diff --git a/gas/testsuite/gas/arc/sexb.s b/gas/testsuite/gas/arc/sexb.s index a2afc3b38b..516ffe47a3 100644 --- a/gas/testsuite/gas/arc/sexb.s +++ b/gas/testsuite/gas/arc/sexb.s @@ -6,33 +6,16 @@ sexb r0,0 sexb r1,-1 sexb 0,r2 - sexb -1,r3 sexb r4,255 - sexb 255,r5 sexb r6,-256 - sexb -256,r7 sexb r8,256 sexb r9,-257 sexb r11,0x42424242 - sexb 255,256 - sexb r0,foo - sexb.eq r10,r11 - sexb.ne r12,r13 - sexb.lt r14,0 - sexb.gt r15,512 - sexb.f r0,r1 sexb.f r2,1 sexb.f 0,r4 sexb.f r5,512 - sexb.f 512,512 - - sexb.eq.f r0,r1 - sexb.ne.f r1,0 - sexb.lt.f 0,r2 - sexb.le.f r0,512 - sexb.n.f 512,512 diff --git a/gas/testsuite/gas/arc/sexw.d b/gas/testsuite/gas/arc/sexw.d index 7b6a612c2f..3c918e2301 100644 --- a/gas/testsuite/gas/arc/sexw.d +++ b/gas/testsuite/gas/arc/sexw.d @@ -1,51 +1,22 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 8c 00 18 18008c00 sexw r0,r1 - 4: 00 0c 6e 1b 1b6e0c00 sexw fp,sp - 8: 00 8c 1f 18 181f8c00 sexw r0,0 - c: ff 8d 3f 18 183f8dff sexw r1,-1 - 10: 00 0c e1 1f 1fe10c00 sexw 0,r2 - 14: 00 8c e1 1f 1fe18c00 sexw 0,r3 - 18: ff 8c 9f 18 189f8cff sexw r4,255 - 1c: 00 8c e2 1f 1fe28c00 sexw 0,r5 - 20: 00 8d df 18 18df8d00 sexw r6,-256 - 24: 00 8c e3 1f 1fe38c00 sexw 0,r7 - 28: 00 0c 1f 19 191f0c00 sexw r8,0x100 - 2c: 00 01 00 00 - 30: 00 0c 3f 19 193f0c00 sexw r9,0xffff_feff - 34: ff fe ff ff - 38: 00 0c 7f 19 197f0c00 sexw r11,0x4242_4242 - 3c: 42 42 42 42 - 40: 00 0c ff 1f 1fff0c00 sexw 0,0x100 - 44: 00 01 00 00 - 48: 00 0c 1f 18 181f0c00 sexw r0,0 - 4c: 00 00 00 00 - 4c: R_ARC_32 foo - 50: 01 8c 45 19 19458c01 sexw.z r10,r11 - 54: 02 8c 86 19 19868c02 sexw.nz r12,r13 - 58: 0b 0c df 19 19df0c0b sexw.lt r14,0 - 5c: 00 00 00 00 - 60: 09 0c ff 19 19ff0c09 sexw.gt r15,0x200 - 64: 00 02 00 00 - 68: 00 8d 00 18 18008d00 sexw.f r0,r1 - 6c: 01 8c 5e 18 185e8c01 sexw.f r2,1 - 70: 00 0d e2 1f 1fe20d00 sexw.f 0,r4 - 74: 00 0d bf 18 18bf0d00 sexw.f r5,0x200 - 78: 00 02 00 00 - 7c: 00 0d df 1f 1fdf0d00 sexw.f 0,0x200 - 80: 00 02 00 00 - 84: 01 8d 00 18 18008d01 sexw.z.f r0,r1 - 88: 02 0d 3f 18 183f0d02 sexw.nz.f r1,0 - 8c: 00 00 00 00 - 90: 0b 0d c1 1f 1fc10d0b sexw.lt.f 0,r2 - 94: 00 00 00 00 00000000 - 98: 0c 0d 1f 18 181f0d0c sexw.le.f r0,0x200 - 9c: 00 02 00 00 - a0: 04 0d df 1f 1fdf0d04 sexw.n.f 0,0x200 - a4: 00 02 00 00 +0x[0-9a-f]+ 202f 0046 sex[wh]+ r0,r1 +0x[0-9a-f]+ 232f 3706 sex[wh]+ fp,sp +0x[0-9a-f]+ 206f 0006 sex[wh]+ r0,0 +0x[0-9a-f]+ 212f 0f86 ffff ffff sex[wh]+ r1,0xffffffff +0x[0-9a-f]+ 262f 7086 sex[wh]+ 0,r2 +0x[0-9a-f]+ 242f 0f86 0000 00ff sex[wh]+ r4,0xff +0x[0-9a-f]+ 262f 0f86 ffff ff00 sex[wh]+ r6,0xffffff00 +0x[0-9a-f]+ 202f 1f86 0000 0100 sex[wh]+ r8,0x100 +0x[0-9a-f]+ 212f 1f86 ffff feff sex[wh]+ r9,0xfffffeff +0x[0-9a-f]+ 232f 1f86 4242 4242 sex[wh]+ r11,0x42424242 +0x[0-9a-f]+ 202f 0f86 0000 0000 sex[wh]+ r0,0 + 44: ARC_32_ME foo +0x[0-9a-f]+ 202f 8046 sex[wh]+.f r0,r1 +0x[0-9a-f]+ 226f 8046 sex[wh]+.f r2,0x1 +0x[0-9a-f]+ 262f f106 sex[wh]+.f 0,r4 +0x[0-9a-f]+ 252f 8f86 0000 0200 sex[wh]+.f r5,0x200 diff --git a/gas/testsuite/gas/arc/sexw.s b/gas/testsuite/gas/arc/sexw.s index 6d05dab03d..68d4e3d352 100644 --- a/gas/testsuite/gas/arc/sexw.s +++ b/gas/testsuite/gas/arc/sexw.s @@ -6,33 +6,16 @@ sexw r0,0 sexw r1,-1 sexw 0,r2 - sexw -1,r3 sexw r4,255 - sexw 255,r5 sexw r6,-256 - sexw -256,r7 sexw r8,256 sexw r9,-257 sexw r11,0x42424242 - sexw 255,256 - sexw r0,foo - sexw.eq r10,r11 - sexw.ne r12,r13 - sexw.lt r14,0 - sexw.gt r15,512 - sexw.f r0,r1 sexw.f r2,1 sexw.f 0,r4 sexw.f r5,512 - sexw.f 512,512 - - sexw.eq.f r0,r1 - sexw.ne.f r1,0 - sexw.lt.f 0,r2 - sexw.le.f r0,512 - sexw.n.f 512,512 diff --git a/gas/testsuite/gas/arc/sleep.d b/gas/testsuite/gas/arc/sleep.d index b6262f6603..624c62558b 100644 --- a/gas/testsuite/gas/arc/sleep.d +++ b/gas/testsuite/gas/arc/sleep.d @@ -1,11 +1,11 @@ -#as: -EL -marc7 -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: 00000000 <main>: - 0: 00 84 00 40 40008400 add r0,r1,r2 - 4: 01 fe ff 1f 1ffffe01 sleep - 8: 00 0a 62 50 50620a00 sub r3,r4,r5 + 0: 2100 0080 add r0,r1,r2 + 4: 216f 013f sleep 0x4 + 8: 2402 0143 sub r3,r4,r5 diff --git a/gas/testsuite/gas/arc/sleep.s b/gas/testsuite/gas/arc/sleep.s index c5797fe6a1..cf656e5038 100644 --- a/gas/testsuite/gas/arc/sleep.s +++ b/gas/testsuite/gas/arc/sleep.s @@ -2,5 +2,5 @@ main: add r0,r1,r2 - sleep + sleep 0x04 sub r3,r4,r5 diff --git a/gas/testsuite/gas/arc/sshift.d b/gas/testsuite/gas/arc/sshift.d deleted file mode 100644 index c0207a77a4..0000000000 --- a/gas/testsuite/gas/arc/sshift.d +++ /dev/null @@ -1,44 +0,0 @@ -#objdump: -dr -#name: @OC@ - -# Test the @OC@ insn. - -.*: +file format elf32-.*arc - -Disassembly of section .text: -00000000 1800@I3+80@00 @OC@ r0,r1 -00000004 1b6e@I3+00@00 @OC@ fp,sp -00000008 181f@I3+80@00 @OC@ r0,0 -0000000c 183f@I3+81@ff @OC@ r1,-1 -00000010 1fe1@I3+00@00 @OC@ 0,r2 -00000014 1fe1@I3+81@ff @OC@ -1,r3 -00000018 189f@I3+80@ff @OC@ r4,255 -0000001c 1fe2@I3+80@ff @OC@ 255,r5 -00000020 18df@I3+81@00 @OC@ r6,-256 -00000024 1fe3@I3+81@00 @OC@ -256,r7 -00000028 191f@I3+00@00 @OC@ r8,256 -00000030 193f@I3+00@00 @OC@ r9,-257 -00000038 1fc5@I3+00@00 @OC@ 511,r10 -00000040 197f@I3+00@00 @OC@ r11,1111638594 -00000048 1fc6@I3+00@00 @OC@ 305419896,r12 -00000050 1fff@I3+00@ff @OC@ 255,256 -00000058 1fdf@I3+80@ff @OC@ 256,255 -00000060 181f@I3+00@00 @OC@ r0,0 - RELOC: 00000064 R_ARC_32 foo -00000068 1945@I3+80@01 @OC@.eq r10,r11 -0000006c 1986@I3+80@02 @OC@.ne r12,r13 -00000070 19df@I3+00@0b @OC@.lt r14,0 -00000078 19ff@I3+00@09 @OC@.gt r15,512 -00000080 1800@I3+81@00 @OC@.f r0,r1 -00000084 185e@I3+80@01 @OC@.f r2,1 -00000088 1fa2@I3+00@00 @OC@.f 0,r4 -0000008c 18bf@I3+01@00 @OC@.f r5,512 -00000094 1fc3@I3+01@00 @OC@.f 512,r6 -0000009c 1fdf@I3+01@00 @OC@.f 512,512 -000000a4 1800@I3+81@01 @OC@.eq.f r0,r1 -000000a8 183f@I3+01@02 @OC@.ne.f r1,0 -000000b0 1fc1@I3+01@0b @OC@.lt.f 0,r2 -000000b8 1fc1@I3+01@09 @OC@.gt.f 1,r2 -000000c0 181f@I3+01@0c @OC@.le.f r0,512 -000000c8 1fc1@I3+01@0a @OC@.ge.f 512,r2 -000000d0 1fdf@I3+01@04 @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/sshift.s b/gas/testsuite/gas/arc/sshift.s deleted file mode 100644 index e2fa661fa5..0000000000 --- a/gas/testsuite/gas/arc/sshift.s +++ /dev/null @@ -1,52 +0,0 @@ -# Single shift @OC@ test - -# reg,reg - @OC@ r0,r1 - @OC@ fp,sp - -# shimm values - @OC@ r0,0 - @OC@ r1,-1 - @OC@ 0,r2 - @OC@ -1,r3 - @OC@ r4,255 - @OC@ 255,r5 - @OC@ r6,-256 - @OC@ -256,r7 - -# limm values - @OC@ r8,256 - @OC@ r9,-257 - @OC@ 511,r10 - @OC@ r11,0x42424242 - @OC@ 0x12345678,r12 - -# shimm and limm - @OC@ 255,256 - @OC@ 256,255 - -# symbols - @OC@ r0,foo - -# conditional execution - @OC@.eq r10,r11 - @OC@.ne r12,r13 - @OC@.lt r14,0 - @OC@.gt r15,512 - -# flag setting - @OC@.f r0,r1 - @OC@.f r2,1 - @OC@.f 0,r4 - @OC@.f r5,512 - @OC@.f 512,r6 - @OC@.f 512,512 - -# conditional execution + flag setting - @OC@.eq.f r0,r1 - @OC@.ne.f r1,0 - @OC@.lt.f 0,r2 - @OC@.gt.f 1,r2 - @OC@.le.f r0,512 - @OC@.ge.f 512,r2 - @OC@.n.f 512,512 diff --git a/gas/testsuite/gas/arc/st.d b/gas/testsuite/gas/arc/st.d index 813f1aa33f..ea4f523262 100644 --- a/gas/testsuite/gas/arc/st.d +++ b/gas/testsuite/gas/arc/st.d @@ -1,42 +1,32 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=archs +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: -00000000 <.text>: - 0: 00 02 01 10 10010200 st r1,\[r2\] - 4: 0e 02 01 10 1001020e st r1,\[r2,14\] - 8: 00 02 41 10 10410200 stb r1,\[r2\] - c: 0e 82 01 11 1101820e st.a r1,\[r3,14\] - 10: 02 02 81 11 11810202 stw.a r1,\[r2,2\] - 14: 00 02 1f 10 101f0200 st r1,\[0x384\] - 18: 84 03 00 00 - 1c: 00 7e 41 10 10417e00 stb 0,\[r2\] - 20: f8 7f 01 10 10017ff8 st -8,\[r2,-8\] - 24: 50 7e 1f 10 101f7e50 st 80,\[0x2ee\] - 28: 9e 02 00 00 - 2c: 00 04 1f 10 101f0400 st r2,\[0\] - 30: 00 00 00 00 - 30: R_ARC_32 foo - 34: 02 02 01 14 14010202 st.di r1,\[r2,2\] - 38: 03 02 01 15 15010203 st.a.di r1,\[r2,3\] - 3c: 04 02 81 15 15810204 stw.a.di r1,\[r2,4\] - 40: 04 7c 06 10 10067c04 st 80,\[r12,4\] - 44: 50 00 00 00 - 44: R_ARC_32 .text - 48: 04 7c 06 10 10067c04 st 20,\[r12,4\] - 4c: 14 00 00 00 - 4c: R_ARC_B26 .text - 50: 00 02 01 12 12010200 sr r1,\[r2\] - 54: 0e 82 1f 12 121f820e sr r1,\[0xe\] - 58: 00 fc 00 12 1200fc00 sr 0x3e8,\[r1\] - 5c: e8 03 00 00 - 60: 64 7e 01 12 12017e64 sr 100,\[r2\] - 64: 00 02 1f 12 121f0200 sr r1,\[0x2710\] - 68: 10 27 00 00 - 6c: 64 7e 1f 12 121f7e64 sr 100,\[0x2710\] - 70: 10 27 00 00 - 74: 64 fc 1f 12 121ffc64 sr 0x2710,\[0x64\] - 78: 10 27 00 00 +[0-9a-f]+ <.L1-0x40>: + 0: 1a00 0040 st r1,\[r2\] + 4: 1a0e 0040 st r1,\[r2,14\] + 8: 1a00 0042 stb r1,\[r2\] + c: 1b0e 0048 st.aw r1,\[r3,14\] + 10: 1a02 004c st[hw]+.aw r1,\[r2,2\] + 14: 1e00 7040 0000 0384 st r1,\[0x384\] + 1c: 1a00 0003 stb 0,\[r2\] + 20: 1af8 8e01 st 56,\[r2,-8\] + 24: 1e00 7080 0000 0000 st r2,\[0\] + 28: ARC_32_ME foo + 2c: 1a02 0060 st.di r1,\[r2,2\] + 30: 1a03 0068 st.di.aw r1,\[r2,3\] + 34: 1a04 006c st[hw]+.di.aw r1,\[r2,4\] + 38: 1c04 1f80 0000 0000 st 0,\[r12,4\] + 3c: ARC_32_ME .L1 + +[0-9a-f]+ <.L1>: + 40: 212b 0080 sr r1,\[r2\] + 44: 216b 0380 sr r1,\[0xe\] + 48: 262b 7040 0000 03e8 sr 0x3e8,\[r1\] + 50: 262b 7080 0000 0064 sr 0x64,\[r2\] + 58: 212b 0f80 0000 2710 sr r1,\[0x2710\] + 60: 266b 7fc0 0000 0064 sr 0x64,\[0x3f\] + 68: 26ab 7901 0000 2710 sr 0x2710,\[100\] diff --git a/gas/testsuite/gas/arc/st.s b/gas/testsuite/gas/arc/st.s index 9acd9f5aa9..546d7250f0 100644 --- a/gas/testsuite/gas/arc/st.s +++ b/gas/testsuite/gas/arc/st.s @@ -8,14 +8,12 @@ st r1,[900] stb 0,[r2] st -8,[r2,-8] - st 80,[750] - st r2,[foo] + st r2,[@foo] st.di r1,[r2,2] st.a.di r1,[r2,3] stw.a.di r1,[r2,4] - st .L1,[r12,4] - st .L1@h30,[r12,4] + st @.L1,[r12,4] .L1: sr r1,[r2] @@ -23,5 +21,5 @@ sr 1000, [r1] sr 100, [r2] sr r1,[10000] - sr 100,[10000] + sr 100,[63] sr 10000,[100] diff --git a/gas/testsuite/gas/arc/sub.d b/gas/testsuite/gas/arc/sub.d index e1c333d032..81b5a1411f 100644 --- a/gas/testsuite/gas/arc/sub.d +++ b/gas/testsuite/gas/arc/sub.d @@ -1,85 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 84 00 50 50008400 sub r0,r1,r2 - 4: 00 b8 4d 53 534db800 sub gp,fp,sp - 8: 00 3e af 53 53af3e00 sub ilink1,ilink2,blink - c: 00 f8 1d 57 571df800 sub r56,r59,lp_count - 10: 00 fe 00 50 5000fe00 sub r0,r1,0 - 14: 00 84 1f 50 501f8400 sub r0,0,r2 - 18: 00 84 e0 57 57e08400 sub 0,r1,r2 - 1c: ff ff 00 50 5000ffff sub r0,r1,-1 - 20: ff 85 1f 50 501f85ff sub r0,-1,r2 - 24: 00 84 e0 57 57e08400 sub 0,r1,r2 - 28: ff fe 00 50 5000feff sub r0,r1,255 - 2c: ff 84 1f 50 501f84ff sub r0,255,r2 - 30: 00 84 e0 57 57e08400 sub 0,r1,r2 - 34: 00 ff 00 50 5000ff00 sub r0,r1,-256 - 38: 00 85 1f 50 501f8500 sub r0,-256,r2 - 3c: 00 84 e0 57 57e08400 sub 0,r1,r2 - 40: 00 fc 00 50 5000fc00 sub r0,r1,0x100 - 44: 00 01 00 00 - 48: 00 04 1f 50 501f0400 sub r0,0xffff_feff,r2 - 4c: ff fe ff ff - 50: ff fc 1f 50 501ffcff sub r0,255,0x100 - 54: 00 01 00 00 - 58: ff 7e 1f 50 501f7eff sub r0,0x100,255 - 5c: 00 01 00 00 - 60: 00 fc 00 50 5000fc00 sub r0,r1,0 - 64: 00 00 00 00 - 64: R_ARC_32 foo - 68: 00 84 00 50 50008400 sub r0,r1,r2 - 6c: 00 0a 62 50 50620a00 sub r3,r4,r5 - 70: 01 90 c3 50 50c39001 sub.z r6,r7,r8 - 74: 01 16 25 51 51251601 sub.z r9,r10,r11 - 78: 02 9c 86 51 51869c02 sub.nz r12,r13,r14 - 7c: 02 22 e8 51 51e82202 sub.nz r15,r16,r17 - 80: 03 a8 49 52 5249a803 sub.p r18,r19,r20 - 84: 03 2e ab 52 52ab2e03 sub.p r21,r22,r23 - 88: 04 b4 0c 53 530cb404 sub.n r24,r25,gp - 8c: 04 3a 6e 53 536e3a04 sub.n fp,sp,ilink1 - 90: 05 c0 cf 53 53cfc005 sub.c ilink2,blink,r32 - 94: 05 46 31 54 54314605 sub.c r33,r34,r35 - 98: 05 cc 92 54 5492cc05 sub.c r36,r37,r38 - 9c: 06 52 f4 54 54f45206 sub.nc r39,r40,r41 - a0: 06 d8 55 55 5555d806 sub.nc r42,r43,r44 - a4: 06 5e b7 55 55b75e06 sub.nc r45,r46,r47 - a8: 07 e4 18 56 5618e407 sub.v r48,r49,r50 - ac: 07 6a 1a 57 571a6a07 sub.v r56,r52,r53 - b0: 08 f0 1b 57 571bf008 sub.nv r56,r55,r56 - b4: 08 76 1d 57 571d7608 sub.nv r56,r58,r59 - b8: 09 00 9e 57 579e0009 sub.gt lp_count,lp_count,r0 - bc: 0a 7c 00 50 50007c0a sub.ge r0,r0,0 - c0: 00 00 00 00 - c4: 0b 02 3f 50 503f020b sub.lt r1,1,r1 - c8: 01 00 00 00 - cc: 0d 06 7f 50 507f060d sub.hi r3,3,r3 - d0: 03 00 00 00 - d4: 0e 08 df 57 57df080e sub.ls 0,4,r4 - d8: 04 00 00 00 - dc: 0f fc c2 57 57c2fc0f sub.pnz 0,r5,5 - e0: 05 00 00 00 - e4: 00 85 00 50 50008500 sub.f r0,r1,r2 - e8: 01 fa 00 50 5000fa01 sub.f r0,r1,1 - ec: 01 84 1e 50 501e8401 sub.f r0,1,r2 - f0: 00 85 e0 57 57e08500 sub.f 0,r1,r2 - f4: 00 fd 00 50 5000fd00 sub.f r0,r1,0x200 - f8: 00 02 00 00 - fc: 00 05 1f 50 501f0500 sub.f r0,0x200,r2 - 100: 00 02 00 00 - 104: 01 85 00 50 50008501 sub.z.f r0,r1,r2 - 108: 02 fd 00 50 5000fd02 sub.nz.f r0,r1,0 - 10c: 00 00 00 00 - 110: 0b 05 1f 50 501f050b sub.lt.f r0,0,r2 - 114: 00 00 00 00 - 118: 09 85 c0 57 57c08509 sub.gt.f 0,r1,r2 - 11c: 00 00 00 00 00000000 - 120: 0c fd 00 50 5000fd0c sub.le.f r0,r1,0x200 - 124: 00 02 00 00 - 128: 0a 05 1f 50 501f050a sub.ge.f r0,0x200,r2 - 12c: 00 02 00 00 +0x[0-9a-f]+ 2102 0080 sub r0,r1,r2 +0x[0-9a-f]+ 2302 371a sub gp,fp,sp +0x[0-9a-f]+ 2602 37dd sub ilink,r30,blink +0x[0-9a-f]+ 2142 0000 sub r0,r1,0 +0x[0-9a-f]+ 2602 7080 0000 0000 sub r0,0,r2 +0x[0-9a-f]+ 2102 00be sub 0,r1,r2 +0x[0-9a-f]+ 2102 0f80 ffff ffff sub r0,r1,0xffffffff +0x[0-9a-f]+ 2602 7080 ffff ffff sub r0,0xffffffff,r2 +0x[0-9a-f]+ 2102 0f80 0000 00ff sub r0,r1,0xff +0x[0-9a-f]+ 2602 7080 0000 00ff sub r0,0xff,r2 +0x[0-9a-f]+ 2102 0f80 ffff ff00 sub r0,r1,0xffffff00 +0x[0-9a-f]+ 2602 7080 ffff ff00 sub r0,0xffffff00,r2 +0x[0-9a-f]+ 2102 0f80 0000 0100 sub r0,r1,0x100 +0x[0-9a-f]+ 2602 7080 ffff feff sub r0,0xfffffeff,r2 +0x[0-9a-f]+ 2602 7f80 0000 0100 sub r0,0x100,0x100 +0x[0-9a-f]+ 2102 0f80 0000 0000 sub r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 20c2 0080 sub r0,r0,r2 +0x[0-9a-f]+ 23c2 0140 sub r3,r3,r5 +0x[0-9a-f]+ 26c2 0201 sub.eq r6,r6,r8 +0x[0-9a-f]+ 21c2 12c1 sub.eq r9,r9,r11 +0x[0-9a-f]+ 24c2 1382 sub.ne r12,r12,r14 +0x[0-9a-f]+ 27c2 1442 sub.ne r15,r15,r17 +0x[0-9a-f]+ 22c2 2503 sub.p r18,r18,r20 +0x[0-9a-f]+ 25c2 25c3 sub.p r21,r21,r23 +0x[0-9a-f]+ 20c2 3684 sub.n r24,r24,gp +0x[0-9a-f]+ 23c2 3744 sub.n fp,fp,ilink +0x[0-9a-f]+ 26c2 37c5 sub.c r30,r30,blink +0x[0-9a-f]+ 23c2 00c5 sub.c r3,r3,r3 +0x[0-9a-f]+ 23c2 0205 sub.c r3,r3,r8 +0x[0-9a-f]+ 23c2 0106 sub.nc r3,r3,r4 +0x[0-9a-f]+ 24c2 0106 sub.nc r4,r4,r4 +0x[0-9a-f]+ 24c2 01c6 sub.nc r4,r4,r7 +0x[0-9a-f]+ 24c2 0147 sub.v r4,r4,r5 +0x[0-9a-f]+ 25c2 0147 sub.v r5,r5,r5 +0x[0-9a-f]+ 25c2 0148 sub.nv r5,r5,r5 +0x[0-9a-f]+ 25c2 0148 sub.nv r5,r5,r5 +0x[0-9a-f]+ 26c2 0009 sub.gt r6,r6,r0 +0x[0-9a-f]+ 20c2 002a sub.ge r0,r0,0 +0x[0-9a-f]+ 21c2 006b sub.lt r1,r1,0x1 +0x[0-9a-f]+ 23c2 00ed sub.hi r3,r3,0x3 +0x[0-9a-f]+ 24c2 012e sub.ls r4,r4,0x4 +0x[0-9a-f]+ 25c2 016f sub.pnz r5,r5,0x5 +0x[0-9a-f]+ 2102 8080 sub.f r0,r1,r2 +0x[0-9a-f]+ 2142 8040 sub.f r0,r1,0x1 +0x[0-9a-f]+ 2602 f080 0000 0001 sub.f r0,0x1,r2 +0x[0-9a-f]+ 2102 80be sub.f 0,r1,r2 +0x[0-9a-f]+ 2102 8f80 0000 0200 sub.f r0,r1,0x200 +0x[0-9a-f]+ 2602 f080 0000 0200 sub.f r0,0x200,r2 +0x[0-9a-f]+ 21c2 8081 sub.f.eq r1,r1,r2 +0x[0-9a-f]+ 20c2 8022 sub.f.ne r0,r0,0 +0x[0-9a-f]+ 22c2 808b sub.f.lt r2,r2,r2 +0x[0-9a-f]+ 26c2 f0a9 0000 0001 sub.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 26c2 ff8c 0000 0200 sub.f.le 0,0x200,0x200 +0x[0-9a-f]+ 26c2 f0aa 0000 0200 sub.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/sub.s b/gas/testsuite/gas/arc/sub.s index 6dd5009b86..963ae22f33 100644 --- a/gas/testsuite/gas/arc/sub.s +++ b/gas/testsuite/gas/arc/sub.s @@ -3,55 +3,50 @@ sub r0,r1,r2 sub r26,fp,sp sub ilink1,ilink2,blink - sub r56,r59,lp_count sub r0,r1,0 sub r0,0,r2 sub 0,r1,r2 sub r0,r1,-1 sub r0,-1,r2 - sub -1,r1,r2 sub r0,r1,255 sub r0,255,r2 - sub 255,r1,r2 sub r0,r1,-256 sub r0,-256,r2 - sub -256,r1,r2 sub r0,r1,256 sub r0,-257,r2 - sub r0,255,256 - sub r0,256,255 + sub r0,256,256 sub r0,r1,foo - sub.al r0,r1,r2 - sub.ra r3,r4,r5 - sub.eq r6,r7,r8 - sub.z r9,r10,r11 - sub.ne r12,r13,r14 - sub.nz r15,r16,r17 - sub.pl r18,r19,r20 - sub.p r21,r22,r23 - sub.mi r24,r25,r26 - sub.n r27,r28,r29 - sub.cs r30,r31,r32 - sub.c r33,r34,r35 - sub.lo r36,r37,r38 - sub.cc r39,r40,r41 - sub.nc r42,r43,r44 - sub.hs r45,r46,r47 - sub.vs r48,r49,r50 - sub.v r56,r52,r53 - sub.vc r56,r55,r56 - sub.nv r56,r58,r59 - sub.gt r60,r60,r0 + sub.al r0,r0,r2 + sub.ra r3,r3,r5 + sub.eq r6,r6,r8 + sub.z r9,r9,r11 + sub.ne r12,r12,r14 + sub.nz r15,r15,r17 + sub.pl r18,r18,r20 + sub.p r21,r21,r23 + sub.mi r24,r24,r26 + sub.n r27,r27,r29 + sub.cs r30,r30,r31 + sub.c r3,r3,r3 + sub.lo r3,r3,r8 + sub.cc r3,r3,r4 + sub.nc r4,r4,r4 + sub.hs r4,r4,r7 + sub.vs r4,r4,r5 + sub.v r5,r5,r5 + sub.vc r5,r5,r5 + sub.nv r5,r5,r5 + sub.gt r6,r6,r0 sub.ge r0,r0,0 - sub.lt r1,1,r1 - sub.hi r3,3,r3 - sub.ls 4,4,r4 - sub.pnz 5,r5,5 + sub.lt r1,r1,1 + sub.hi r3,r3,3 + sub.ls r4,r4,4 + sub.pnz r5,r5,5 sub.f r0,r1,r2 sub.f r0,r1,1 @@ -60,9 +55,9 @@ sub.f r0,r1,512 sub.f r0,512,r2 - sub.eq.f r0,r1,r2 - sub.ne.f r0,r1,0 - sub.lt.f r0,0,r2 - sub.gt.f 0,r1,r2 - sub.le.f r0,r1,512 - sub.ge.f r0,512,r2 + sub.eq.f r1,r1,r2 + sub.ne.f r0,r0,0 + sub.lt.f r2,r2,r2 + sub.gt.f 0,1,2 + sub.le.f 0,512,512 + sub.ge.f 0,512,2 diff --git a/gas/testsuite/gas/arc/swi.d b/gas/testsuite/gas/arc/swi.d index 58654ecfe1..385f2a3952 100644 --- a/gas/testsuite/gas/arc/swi.d +++ b/gas/testsuite/gas/arc/swi.d @@ -1,11 +1,11 @@ -#as: -EL -marc8 -#objdump: -dr -EL +#as: -mcpu=archs +#objdump: -dr --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: 00000000 <main>: - 0: 00 84 00 40 40008400 add r0,r1,r2 - 4: 02 fe ff 1f 1ffffe02 swi - 8: 00 0a 62 50 50620a00 sub r3,r4,r5 + 0: 2100 0080 add r0,r1,r2 + 4: 226f 003f swi + 8: 2402 0143 sub r3,r4,r5 diff --git a/gas/testsuite/gas/arc/warn.exp b/gas/testsuite/gas/arc/warn.exp index 3f048537db..a94857bbb2 100644 --- a/gas/testsuite/gas/arc/warn.exp +++ b/gas/testsuite/gas/arc/warn.exp @@ -19,6 +19,6 @@ if [istarget arc*-*-*] { load_lib gas-dg.exp dg-init - dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/warn*.s]] "" "" + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*warn*.s $srcdir/$subdir/*err*.s]] "" "" dg-finish } diff --git a/gas/testsuite/gas/arc/warn.s b/gas/testsuite/gas/arc/warn.s index 6df1185dad..e89aa99fb2 100644 --- a/gas/testsuite/gas/arc/warn.s +++ b/gas/testsuite/gas/arc/warn.s @@ -3,14 +3,10 @@ ; { dg-do assemble { target arc-*-* } } b.d foo - mov r0,256 ; { dg-warning "8 byte instruction in delay slot" "8 byte instruction in delay slot" } + mov r0,256 - j.d foo ; { dg-warning "8 byte jump instruction with delay slot" "8 byte jump instruction with delay slot" } + j.d foo ; { dg-warning "inappropriate arguments for opcode" "inappropriate arguments for opcode" } mov r0,r1 foo: -.extCoreRegister roscreg,45,r,can_shortcut -.extCoreRegister woscreg,46,w,can_shortcut - .section .text - add r0,woscreg,r1 ; { dg-warning "Error: attempt to read writeonly register" } - add roscreg,r1,r2 ; { dg-warning "Error: attempt to set readonly register" } + diff --git a/gas/testsuite/gas/arc/xor.d b/gas/testsuite/gas/arc/xor.d index 46fdeddca2..6a635a7d6f 100644 --- a/gas/testsuite/gas/arc/xor.d +++ b/gas/testsuite/gas/arc/xor.d @@ -1,85 +1,61 @@ -#as: -EL -#objdump: -dr -EL +#as: -mcpu=arc700 +#objdump: -dr --prefix-addresses --show-raw-insn -.*: +file format elf32-.*arc +.*: +file format .*arc.* Disassembly of section .text: - -00000000 <.text>: - 0: 00 84 00 78 78008400 xor r0,r1,r2 - 4: 00 b8 4d 7b 7b4db800 xor gp,fp,sp - 8: 00 3e af 7b 7baf3e00 xor ilink1,ilink2,blink - c: 00 f8 1d 7f 7f1df800 xor r56,r59,lp_count - 10: 00 fe 00 78 7800fe00 xor r0,r1,0 - 14: 00 84 1f 78 781f8400 xor r0,0,r2 - 18: 00 84 e0 7f 7fe08400 xor 0,r1,r2 - 1c: ff ff 00 78 7800ffff xor r0,r1,-1 - 20: ff 85 1f 78 781f85ff xor r0,-1,r2 - 24: 00 84 e0 7f 7fe08400 xor 0,r1,r2 - 28: ff fe 00 78 7800feff xor r0,r1,255 - 2c: ff 84 1f 78 781f84ff xor r0,255,r2 - 30: 00 84 e0 7f 7fe08400 xor 0,r1,r2 - 34: 00 ff 00 78 7800ff00 xor r0,r1,-256 - 38: 00 85 1f 78 781f8500 xor r0,-256,r2 - 3c: 00 84 e0 7f 7fe08400 xor 0,r1,r2 - 40: 00 fc 00 78 7800fc00 xor r0,r1,0x100 - 44: 00 01 00 00 - 48: 00 04 1f 78 781f0400 xor r0,0xffff_feff,r2 - 4c: ff fe ff ff - 50: ff fc 1f 78 781ffcff xor r0,255,0x100 - 54: 00 01 00 00 - 58: ff 7e 1f 78 781f7eff xor r0,0x100,255 - 5c: 00 01 00 00 - 60: 00 fc 00 78 7800fc00 xor r0,r1,0 - 64: 00 00 00 00 - 64: R_ARC_32 foo - 68: 00 84 00 78 78008400 xor r0,r1,r2 - 6c: 00 0a 62 78 78620a00 xor r3,r4,r5 - 70: 01 90 c3 78 78c39001 xor.z r6,r7,r8 - 74: 01 16 25 79 79251601 xor.z r9,r10,r11 - 78: 02 9c 86 79 79869c02 xor.nz r12,r13,r14 - 7c: 02 22 e8 79 79e82202 xor.nz r15,r16,r17 - 80: 03 a8 49 7a 7a49a803 xor.p r18,r19,r20 - 84: 03 2e ab 7a 7aab2e03 xor.p r21,r22,r23 - 88: 04 b4 0c 7b 7b0cb404 xor.n r24,r25,gp - 8c: 04 3a 6e 7b 7b6e3a04 xor.n fp,sp,ilink1 - 90: 05 c0 cf 7b 7bcfc005 xor.c ilink2,blink,r32 - 94: 05 46 31 7c 7c314605 xor.c r33,r34,r35 - 98: 05 cc 92 7c 7c92cc05 xor.c r36,r37,r38 - 9c: 06 52 f4 7c 7cf45206 xor.nc r39,r40,r41 - a0: 06 d8 55 7d 7d55d806 xor.nc r42,r43,r44 - a4: 06 5e b7 7d 7db75e06 xor.nc r45,r46,r47 - a8: 07 e4 18 7e 7e18e407 xor.v r48,r49,r50 - ac: 07 6a 1a 7f 7f1a6a07 xor.v r56,r52,r53 - b0: 08 f0 1b 7f 7f1bf008 xor.nv r56,r55,r56 - b4: 08 76 1d 7f 7f1d7608 xor.nv r56,r58,r59 - b8: 09 00 9e 7f 7f9e0009 xor.gt lp_count,lp_count,r0 - bc: 0a 7c 00 78 78007c0a xor.ge r0,r0,0 - c0: 00 00 00 00 - c4: 0b 02 3f 78 783f020b xor.lt r1,1,r1 - c8: 01 00 00 00 - cc: 0d 06 7f 78 787f060d xor.hi r3,3,r3 - d0: 03 00 00 00 - d4: 0e 08 df 7f 7fdf080e xor.ls 0,4,r4 - d8: 04 00 00 00 - dc: 0f fc c2 7f 7fc2fc0f xor.pnz 0,r5,5 - e0: 05 00 00 00 - e4: 00 85 00 78 78008500 xor.f r0,r1,r2 - e8: 01 fa 00 78 7800fa01 xor.f r0,r1,1 - ec: 01 84 1e 78 781e8401 xor.f r0,1,r2 - f0: 00 85 e0 7f 7fe08500 xor.f 0,r1,r2 - f4: 00 fd 00 78 7800fd00 xor.f r0,r1,0x200 - f8: 00 02 00 00 - fc: 00 05 1f 78 781f0500 xor.f r0,0x200,r2 - 100: 00 02 00 00 - 104: 01 85 00 78 78008501 xor.z.f r0,r1,r2 - 108: 02 fd 00 78 7800fd02 xor.nz.f r0,r1,0 - 10c: 00 00 00 00 - 110: 0b 05 1f 78 781f050b xor.lt.f r0,0,r2 - 114: 00 00 00 00 - 118: 09 85 c0 7f 7fc08509 xor.gt.f 0,r1,r2 - 11c: 00 00 00 00 00000000 - 120: 0c fd 00 78 7800fd0c xor.le.f r0,r1,0x200 - 124: 00 02 00 00 - 128: 0a 05 1f 78 781f050a xor.ge.f r0,0x200,r2 - 12c: 00 02 00 00 +0x[0-9a-f]+ 2107 0080 xor r0,r1,r2 +0x[0-9a-f]+ 2307 371a xor gp,fp,sp +0x[0-9a-f]+ 2607 37dd xor ilink,r30,blink +0x[0-9a-f]+ 2147 0000 xor r0,r1,0 +0x[0-9a-f]+ 2607 7080 0000 0000 xor r0,0,r2 +0x[0-9a-f]+ 2107 00be xor 0,r1,r2 +0x[0-9a-f]+ 2107 0f80 ffff ffff xor r0,r1,0xffffffff +0x[0-9a-f]+ 2607 7080 ffff ffff xor r0,0xffffffff,r2 +0x[0-9a-f]+ 2107 0f80 0000 00ff xor r0,r1,0xff +0x[0-9a-f]+ 2607 7080 0000 00ff xor r0,0xff,r2 +0x[0-9a-f]+ 2107 0f80 ffff ff00 xor r0,r1,0xffffff00 +0x[0-9a-f]+ 2607 7080 ffff ff00 xor r0,0xffffff00,r2 +0x[0-9a-f]+ 2107 0f80 0000 0100 xor r0,r1,0x100 +0x[0-9a-f]+ 2607 7080 ffff feff xor r0,0xfffffeff,r2 +0x[0-9a-f]+ 2607 7f80 0000 0100 xor r0,0x100,0x100 +0x[0-9a-f]+ 2107 0f80 0000 0000 xor r0,r1,0 + 68: ARC_32_ME foo +0x[0-9a-f]+ 20c7 0080 xor r0,r0,r2 +0x[0-9a-f]+ 23c7 0140 xor r3,r3,r5 +0x[0-9a-f]+ 26c7 0201 xor.eq r6,r6,r8 +0x[0-9a-f]+ 21c7 12c1 xor.eq r9,r9,r11 +0x[0-9a-f]+ 24c7 1382 xor.ne r12,r12,r14 +0x[0-9a-f]+ 27c7 1442 xor.ne r15,r15,r17 +0x[0-9a-f]+ 22c7 2503 xor.p r18,r18,r20 +0x[0-9a-f]+ 25c7 25c3 xor.p r21,r21,r23 +0x[0-9a-f]+ 20c7 3684 xor.n r24,r24,gp +0x[0-9a-f]+ 23c7 3744 xor.n fp,fp,ilink +0x[0-9a-f]+ 26c7 37c5 xor.c r30,r30,blink +0x[0-9a-f]+ 23c7 00c5 xor.c r3,r3,r3 +0x[0-9a-f]+ 23c7 0205 xor.c r3,r3,r8 +0x[0-9a-f]+ 23c7 0106 xor.nc r3,r3,r4 +0x[0-9a-f]+ 24c7 0106 xor.nc r4,r4,r4 +0x[0-9a-f]+ 24c7 01c6 xor.nc r4,r4,r7 +0x[0-9a-f]+ 24c7 0147 xor.v r4,r4,r5 +0x[0-9a-f]+ 25c7 0147 xor.v r5,r5,r5 +0x[0-9a-f]+ 25c7 0148 xor.nv r5,r5,r5 +0x[0-9a-f]+ 25c7 0148 xor.nv r5,r5,r5 +0x[0-9a-f]+ 26c7 0009 xor.gt r6,r6,r0 +0x[0-9a-f]+ 20c7 002a xor.ge r0,r0,0 +0x[0-9a-f]+ 21c7 006b xor.lt r1,r1,0x1 +0x[0-9a-f]+ 23c7 00ed xor.hi r3,r3,0x3 +0x[0-9a-f]+ 24c7 012e xor.ls r4,r4,0x4 +0x[0-9a-f]+ 25c7 016f xor.pnz r5,r5,0x5 +0x[0-9a-f]+ 2107 8080 xor.f r0,r1,r2 +0x[0-9a-f]+ 2147 8040 xor.f r0,r1,0x1 +0x[0-9a-f]+ 2607 f080 0000 0001 xor.f r0,0x1,r2 +0x[0-9a-f]+ 2107 80be xor.f 0,r1,r2 +0x[0-9a-f]+ 2107 8f80 0000 0200 xor.f r0,r1,0x200 +0x[0-9a-f]+ 2607 f080 0000 0200 xor.f r0,0x200,r2 +0x[0-9a-f]+ 21c7 8081 xor.f.eq r1,r1,r2 +0x[0-9a-f]+ 20c7 8022 xor.f.ne r0,r0,0 +0x[0-9a-f]+ 22c7 808b xor.f.lt r2,r2,r2 +0x[0-9a-f]+ 26c7 f0a9 0000 0001 xor.f.gt 0,0x1,0x2 +0x[0-9a-f]+ 26c7 ff8c 0000 0200 xor.f.le 0,0x200,0x200 +0x[0-9a-f]+ 26c7 f0aa 0000 0200 xor.f.ge 0,0x200,0x2 diff --git a/gas/testsuite/gas/arc/xor.s b/gas/testsuite/gas/arc/xor.s index 090107ac3c..56f3c6e926 100644 --- a/gas/testsuite/gas/arc/xor.s +++ b/gas/testsuite/gas/arc/xor.s @@ -3,55 +3,50 @@ xor r0,r1,r2 xor r26,fp,sp xor ilink1,ilink2,blink - xor r56,r59,lp_count xor r0,r1,0 xor r0,0,r2 xor 0,r1,r2 xor r0,r1,-1 xor r0,-1,r2 - xor -1,r1,r2 xor r0,r1,255 xor r0,255,r2 - xor 255,r1,r2 xor r0,r1,-256 xor r0,-256,r2 - xor -256,r1,r2 xor r0,r1,256 xor r0,-257,r2 - xor r0,255,256 - xor r0,256,255 + xor r0,256,256 xor r0,r1,foo - xor.al r0,r1,r2 - xor.ra r3,r4,r5 - xor.eq r6,r7,r8 - xor.z r9,r10,r11 - xor.ne r12,r13,r14 - xor.nz r15,r16,r17 - xor.pl r18,r19,r20 - xor.p r21,r22,r23 - xor.mi r24,r25,r26 - xor.n r27,r28,r29 - xor.cs r30,r31,r32 - xor.c r33,r34,r35 - xor.lo r36,r37,r38 - xor.cc r39,r40,r41 - xor.nc r42,r43,r44 - xor.hs r45,r46,r47 - xor.vs r48,r49,r50 - xor.v r56,r52,r53 - xor.vc r56,r55,r56 - xor.nv r56,r58,r59 - xor.gt r60,r60,r0 + xor.al r0,r0,r2 + xor.ra r3,r3,r5 + xor.eq r6,r6,r8 + xor.z r9,r9,r11 + xor.ne r12,r12,r14 + xor.nz r15,r15,r17 + xor.pl r18,r18,r20 + xor.p r21,r21,r23 + xor.mi r24,r24,r26 + xor.n r27,r27,r29 + xor.cs r30,r30,r31 + xor.c r3,r3,r3 + xor.lo r3,r3,r8 + xor.cc r3,r3,r4 + xor.nc r4,r4,r4 + xor.hs r4,r4,r7 + xor.vs r4,r4,r5 + xor.v r5,r5,r5 + xor.vc r5,r5,r5 + xor.nv r5,r5,r5 + xor.gt r6,r6,r0 xor.ge r0,r0,0 - xor.lt r1,1,r1 - xor.hi r3,3,r3 - xor.ls 4,4,r4 - xor.pnz 5,r5,5 + xor.lt r1,r1,1 + xor.hi r3,r3,3 + xor.ls r4,r4,4 + xor.pnz r5,r5,5 xor.f r0,r1,r2 xor.f r0,r1,1 @@ -60,9 +55,9 @@ xor.f r0,r1,512 xor.f r0,512,r2 - xor.eq.f r0,r1,r2 - xor.ne.f r0,r1,0 - xor.lt.f r0,0,r2 - xor.gt.f 0,r1,r2 - xor.le.f r0,r1,512 - xor.ge.f r0,512,r2 + xor.eq.f r1,r1,r2 + xor.ne.f r0,r0,0 + xor.lt.f r2,r2,r2 + xor.gt.f 0,1,2 + xor.le.f 0,512,512 + xor.ge.f 0,512,2 diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp index 496e01a4ff..fc81da1e4f 100644 --- a/gas/testsuite/gas/elf/elf.exp +++ b/gas/testsuite/gas/elf/elf.exp @@ -90,6 +90,7 @@ if { [is_elf_format] } then { # optimization because it interfers with link-time relaxation of # function prologues. if {![istarget "mn10300-*-*"] + && ![istarget "arc-*-*"] && ![istarget "xtensa*-*-*"] && ![istarget "msp430*-*-*"] && ![istarget "nds32*-*-*"] @@ -148,7 +149,7 @@ if { [is_elf_format] } then { # against ordinary symbols into relocations against section symbols. # This is usually revealed by the error message: # symbol `sym' required but not present - setup_xfail "m681*-*-*" "m68hc*-*-*" + setup_xfail "m681*-*-*" "m68hc*-*-*" "arc-*-*" run_dump_test redef run_dump_test equ-reloc } |